JPH07120503A - Waveform recorder - Google Patents

Abstract

PURPOSE:To analyze the mutual relation between recording signal. waveforms captured with trigger pulses having different-occurrence time as origins by controlling respective address control circuits based on different pulses or delay pulses generated with the different trigger pulses as origins. CONSTITUTION:A clock oscillator 7 supplies clocks for specifying timing for operation to an ADD-converters 2, 14, 18 and address control circuits 8, 16, 20. A trigger circuit 10 generates a trigger pulse when an input signal crosses a predetermined level. The control circuits 2, 14, 18 frequency-divide clock signals generated by the oscillator 7 for counting the output clocks, count the clocks to a specified value with the trigger pulse generated by the circuit 10 or a delay pulse output from a delay timer 11 as an origin, and control recording of waveform data in waveform memories in respective channels based on the trigger pulse or the delay pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform recording device such as a digital oscilloscope, and more particularly to a waveform recording device which can record waveforms having different time points as reference points on the same screen.

[0002]

2. Description of the Related Art A digital oscilloscope A / D-converts an input signal, temporarily records the waveform data in a waveform memory, then D / A-converts it, and displays the waveform on a display device such as a cathode ray tube. To do.

When the structure of the electronic device to be measured becomes complicated, it is not enough to check the signal waveform at one location of the electronic device, and it becomes necessary to simultaneously observe the operations of a plurality of circuit parts which are related to each other. In order to respond to such a point, the conventional digital oscilloscope has a plurality of channels that take in the signals of each circuit part, and the signals input from each channel are A / D converted in parallel and provided for each channel. After being temporarily recorded in the waveform memory, D / A conversion is performed and signal waveforms of a plurality of channels are displayed on one screen of the display device using the same time axis.

The waveform memory sequentially stores the A / D converted waveform data. When the number of input waveform data exceeds the memory length, the old data is sequentially erased and the newly input data is continuously stored. The memory update of the waveform memory is stopped based on the trigger pulse generated when the input signal crosses a certain level, and the waveform data representing the waveform of the input signal is held in the waveform memory.

Many conventional digital oscilloscopes are equipped with a post counter. This post counter counts the number of A / D converted waveform data to be input to the waveform memory based on the trigger pulse generated from the input signal, and when the preset value is reached, the waveform data is sent to the waveform memory. Stop the record update operation.

Therefore, assuming that the memory length of the waveform memory is M bytes and the numerical value preset in the post counter is N, the waveform data before the trigger pulse base point is MN bytes, and the following data is stored in the waveform memory. Is recorded in N bytes, and the waveform in the time zone before and after the trigger pulse is generated can be reproduced and displayed on a display device such as a cathode ray tube.

Further, the delay timer is activated by the trigger pulse, and the post timer is activated after the delay time set by the delay timer has elapsed. The waveform data after the delay time is also recorded. Has been.

Further, in Japanese Patent Laid-Open No. 61-93963, a digital oscilloscope of the type which does not have a post counter and stops recording / updating of a waveform memory by a trigger pulse is provided with a delay independently for each of a plurality of channels. A configuration for giving or setting the same delay time for all of a plurality of channels is disclosed.

[0009]

In the conventional digital oscilloscope, when one trigger pulse is generated,
A delay timer or a post counter is started based on the trigger pulse. Therefore, in the waveform memory of each channel, signal waveforms that appear in each circuit portion are recorded based on the signal that generated the trigger pulse, and these are displayed on the display screen.

However, in the conventional digital oscilloscope, when the trigger pulse is continuously generated,
Waveforms with the trigger pulse at different time points as the base points cannot be displayed on the same screen or compared and analyzed.

The present invention is to improve the above conventional points, and when a trigger pulse is repeatedly generated, a signal waveform in which a trigger pulse having a different generation time is used as a reference point is generated by each of the waveform memories of a plurality of channels. It is an object of the present invention to provide a waveform recording device capable of recording a waveform, displaying those waveforms on the same screen, and analyzing the relationship between these signal waveforms.

[0012]

Therefore, in the present invention, a signal having a plurality of channels and inputted to each channel is A /.
In a waveform recording device including an A / D converter for D conversion and a waveform memory for recording the waveform data of an A / D converted input signal, a trigger pulse is output based on the level of a signal input to a reference channel. Trigger generating means, a delay pulse generating means for generating a delay pulse after a lapse of a set time based on the trigger pulse, and an address control for controlling the recording of the waveform data in the waveform memory of each channel based on the trigger pulse or the delay pulse. Means and each of the address control means is set to perform the control based on a different trigger pulse or a delay pulse generated based on a different trigger pulse.

Further, the sample rate of the waveform data recorded in the waveform memory can be changed by the address control means.

Further, there is provided an arithmetic means for performing an arithmetic operation using the waveform data recorded in each waveform memory.

[0015]

Therefore, when the trigger pulse is repeatedly generated from the trigger generating means, the recording operation of the waveform memory of another channel is controlled for each trigger pulse, and the phenomenon captured at different measurement points is recorded in each waveform memory. To be done.

When comparing the waveforms of the signals input to the respective channels, by changing the sample rate of the waveform data recorded in the waveform memory, for example, a compressed signal and an uncompressed signal are kept in the same state. It becomes possible to compare.

By calculating the waveform data recorded in each waveform memory by the calculating means, it becomes possible to observe the difference signal and the like.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a waveform recording apparatus according to an embodiment of the present invention includes a channel 1 (CH1) and a channel 2
(CH2) and channel 3 (CH3) input terminals 91,
92, 93 and A to A / D convert the signal input from each terminal
The waveform data output from the A / D converters 2, 14, 18 and the preamplifiers 1, 13, 17 that adjust the gain of the input signal so that the A / D converter does not overflow, and the A / D converters 2, 14, 18 are temporarily stored. Waveform memory to record 3, 1
5, 19 and address control circuits 8, 16 and 20 for controlling the recording of the waveform data in the waveform memories 3, 15 and 19, and A /
D converters 2, 14, 18 and address control circuits 8, 1
A clock oscillator 7 that supplies a clock for designating the operation timing to 6 and 20, a trigger circuit 10 that generates a trigger pulse when the input signal crosses a certain level, and a delay pulse after a certain delay time when the trigger pulse is input. The delay timer 11 for outputting the waveform data, the display memory 4 for storing the waveform data held in the waveform memories 3, 15, 19 and the waveform data stored in the display memory 4 are connected to each other by the data transfer bus. The waveform data stored in the display memory 4 and the calculation circuit 21 for performing calculation between
It is provided with an X signal generator 5 and a Y signal generator 9 that generate an X signal and a Y signal for A / A conversion and display on the cathode ray tube 6.

The address control circuits 8, 16 and 20 include a frequency divider for dividing the clock signal generated by the clock oscillator 7, an address counter for counting the clock output from the frequency divider, and a trigger circuit. It includes a post counter that counts clocks up to a set value based on the trigger pulse generated in 10 or the delay pulse output from the delay timer 11.

This waveform recording apparatus has an input terminal 91 of CH1.
When the signal shown in A of FIG. 2 is input to, the operation is as follows. In FIG. 2, A, B, and C represent the voltage or current waveform of the input signal, T represents the timing of recording the input signal, and the horizontal axis represents the passage of time.

The input signal A is A / D by the preamplifier 1.
The amplitude is attenuated or amplified to match the dynamic range of the converter 2. The A / D converter 2 performs A / D conversion on the signal amplified by the preamplifier 1 in synchronism with the clock signal generated by the clock oscillator 7.

A part of the input signal attenuated or amplified by the preamplifier 1 is input to the trigger circuit 10, and the trigger circuit 10
Generates a trigger pulse when the input signal level crosses a constant level value. In FIG. 2, T ₀ indicates the time when the trigger pulse is generated.

Address control circuit 8 receives the trigger pulse generated by trigger circuit 10 and the clock signal generated by clock oscillator 7, and repeats the following operation. For easy understanding, the frequency of the clock signal is 10 Mc / s, and the memory length of the waveform memory 3 is 1 k.
It is a word, and it is assumed that there are address numbers from 1 to 1024.

In the address control circuit 8, the frequency divider divides the clock signal, the address counter counts the output of the frequency divider from 1 to 1024, and then returns to 1 again to 10
Count up to 24 and repeat continuously.

The count value of the address counter of the address control circuit 8 is sent to the address bus of the waveform memory 3 as address information. Therefore, when the frequency division ratio of the frequency divider is 1, the waveform data generated by the A / D converter 2 is
According to the clock signal from the clock oscillator 7, the waveform memory 3 is sequentially recorded from addresses 1 to 1024 and then again from address 1 and is continuously repeated.

When the trigger circuit 10 generates a trigger pulse at T ₀ in FIG. 2, this trigger pulse activates the post counter of the address control circuit 8 and starts the operation of counting the clock output from the frequency divider.

Assuming that the set numerical value of the post counter is 700 and the frequency division ratio of the frequency divider of the address control circuit 8 is 1, the sample rate of the clock oscillator 7 is 10 Mc / s (that is, 0. 700 times of 1 μs cycle),
That is, the counting operation of the address counter of the address control circuit 8 is stopped after 70 μs.

As a result, the waveform memory 3 is switched to the operation of holding the record of the waveform data. Waveform memory 3
Since the memory length is capable of storing 1024 pieces of data, the time interval of waveform data that can be recorded and held is 102.4.
μs. Therefore, the recorded and held data has a waveform of 32.4 μs before the trigger pulse is generated and 70 μs after that. In FIG. 2A, the waveform data between T1 and T2 is recorded and held, and T1 and T2 are the waveform recording period in CH1.

The waveform data recorded and held in the waveform memory 3 is transferred to the data input bus of the display memory 4 through the data output bus and stored in the display memory 4.
The stored data is reproduced and displayed on the tube surface by the X signal generator 5 including the D / A converter, the Y signal generator 9 and the cathode ray tube 6.

In FIG. 3, the waveform of the signal of CH1 reproduced and displayed on the surface of the cathode ray tube 6 is shown as a.

The sample rate of the waveform data recorded in the waveform memory 3 can be changed by changing the frequency division ratio of the frequency divider of the address control circuit 8. This is because the sample rate of the A / D converter 2 is determined by the clock rate of the clock oscillator 7, but the address counter of the address control circuit 8 counts according to the output of the frequency divider that divides the clock signal of the oscillator 7. In order to perform the operation, the waveform data that can be captured by the waveform memory 3 is A /
This is because the data output from the D converter 2 is limited to only the data whose timing matches the output of the frequency divider.

For example, assuming that the frequency division ratio of the frequency divider is 1/2, the waveform data output from the A / D converter 2 is
Only the data for once in twice in the order of elapsed time is the waveform memory 3
Recorded in. Therefore, the sample rate at the time of waveform acquisition is 5 Mc / s. This waveform is displayed on the cathode ray tube in a state in which the waveform of FIG.

Next, recording of the waveform of the signal input to CH2 will be described.

CH2 input terminal corresponding to CH1 input
It is assumed that the signal shown in B of FIG. 2 is input to 92. Depending on this signal input, preamplifier 13, A / D converter
14, the waveform memory 15 and the address control circuit 16 are CH1
The same operation as the preamplifier 1, A / D converter 2, waveform memory 3 and address control circuit 8 at the input is repeated.

However, the starting time of the post counter in the address control circuit 16 differs from the starting time of the post counter in the address control circuit 8 depending on how the address control circuit 16 or the trigger circuit 10 is set.

Now, the trigger circuit 10 outputs the trigger pulse to the delay timer 11 at the same time as the address control circuit 8, and the post counter of the address control circuit 16 ignores the trigger pulse directly input from the trigger circuit 10, It is assumed that it is set to start only by the delay pulse input from the delay timer 11.

The delay timer 11 is activated by a trigger pulse input from the trigger circuit 10 and generates a delay pulse after a set time has elapsed. The post counter of the address control circuit 16 is activated by this delay pulse. That is, this delay pulse functions as a trigger pulse for the CH1 address control circuit 8.

If the numerical value set in the post counter of the address control circuit 16 is 1024 and the frequency division ratio of the frequency divider of the address control circuit 16 is 1, the post counter will receive the delayed pulse after input. , Clock oscillator 7
After 1024 times the sample rate of 10 Mc / s (that is, a period of 0.1 μs), that is, 102.4 μs, the counting operation of the address counter of the address control circuit 16 is stopped. As a result, the waveform memory 15 switches to the operation of holding the record of the waveform data.

Since the waveform memory 15 has a memory length capable of storing 1024 pieces of data, the time interval of waveform data that can be recorded and held is 102.4 μs. Therefore, the waveform data input from the A / D converter 14 is recorded and held within the period of 102.4 μs after the generation of the delay pulse. This period (T _{3 to} T _{4 in} FIG. 2) is the CH2 waveform recording period. The delay time set in the delay timer 11 corresponds to T _{0 to} T ₃ in FIG.

The waveform data recorded and held in the waveform memory 15 is transferred to the data input bus of the display memory 4 through the data output bus and stored in the display memory 4. In the display memory 4, a part of the waveform data of A in FIG. 2 has already been recorded. Therefore, at this point, the data stored in the display memory 4 is converted into an analog signal by the X signal generator 5 and the Y signal generator 9, and then the data is displayed on the CRT.
Display the phenomenon. In FIG. 3, the waveforms reproduced and displayed on the cathode ray tube by these data are shown as a and b.

When the trigger circuit 10 repeatedly generates the trigger pulse, it is possible to capture the waveform data of the input signal in CH1 and CH2 based on different trigger pulses.

In this case, the trigger circuit 10 sets the trigger circuit 10 to output the first trigger pulse to the address control circuit 8 and the subsequent trigger pulses to the delay timer 11, and , The address control circuit 16 post counter is not sensitive to the trigger pulse directly input from the trigger circuit 10, and is activated only by the delay pulse input from the delay timer 11.
Set to 16.

Therefore, the first trigger pulse generated by the trigger circuit 10 is input to the address control circuit 8, and the waveform memory 3 holds the waveform of the input signal of CH1 in the procedure described above. The subsequent trigger pulse generated by the trigger circuit 10 is input to the delay timer 11, and the delay timer 11
Restarts each time, and generates a delay pulse after a lapse of a certain delay time.

The post counter of the address control circuit 16 is activated by the delay pulse of the delay timer 11,
After counting a certain number of clocks, the recording and updating of the waveform memory 15 is stopped, and the waveform memory 15 switches the operation to hold the waveform data.

Thus, the waveform memory 15 can capture the waveform of the signal input to CH2 based on the second trigger pulse.

In this case, the trigger circuit 10 does not switch the output destination of the trigger pulse, and in the address control circuit 16, the first delay pulse input does not activate the post counter and the second delay pulse is not activated. You can achieve the same result by setting the post counter to start starting with.

Now, for the signal input to the input terminal 93 of CH3, the preamplifier 17, the A / D converter 18, the waveform memory 19 and the address control circuit 20 use the preamplifier 1 of CH1, the A / D converter 2, and the waveform. The same operation as memory 3 and address control circuit 8 is performed.

However, the address control circuit 20 is a trigger circuit.
When 10 is set to switch the output destination of the trigger pulse, the trigger circuit 10 starts the post counter based on the second delay pulse output from the delay timer 11, and the trigger circuit 10 When the output destination is set not to be switched, the post counter is set to be activated based on the delay pulse output third.

As a result, when the trigger circuit 10 generates a trigger pulse after the waveform data has been fetched into the CH1 and CH2 waveform memories 3 and 15, the delay timer 11 is restarted and the delay time elapses. Generate a pulse,
The post counter of the address control circuit 20 is activated by this delay pulse.

When the numerical value set in the post counter of the address control circuit 20 is 1024 and the frequency division ratio of the frequency divider is 1 as in the case of the post counter of the address control circuit 16, the waveform memory is 19 is the waveform memory 15
Similarly, the waveform is held for 102.4 μs after the delay pulse is input. In FIG. 2, the waveform input to CH3 is C
In also represents a waveform recording period CH3 at T ₅ through T _6.

The waveform data recorded and held in the waveform memory 19 is transferred to and stored in the display memory 4. The display memory 4 has already recorded a part of the waveform data of A and B in FIG. Therefore, when the data stored in the display memory 4 is analog-converted by the X signal generator 5 and the Y signal generator 9 and then displayed on the cathode ray tube 6, as shown in a, b, c of FIG. Three phenomena are displayed.

Further, in this waveform recording apparatus, the trigger circuit
When 10 outputs trigger pulses one after another, the post counters of the address control circuits 16 and 20 in CH2 and CH3 are activated one after another by these trigger pulses.
A so-called “retrigger mode” is also possible.

In the case of this re-trigger mode, the post counter of the address control circuit 16 prepares to count with the first delay pulse from the delay timer 11 and starts the counting operation with the trigger pulse input thereafter. The address control circuit 16 is set, and the address counter is controlled so that the post counter of the address control circuit 20 prepares for counting with the next delay pulse from the delay timer 11 and starts the counting operation with the trigger pulse input after that. Set up circuit 20.

Therefore, the post counters of the address control circuits 16 and 20 are started by the designated delay pulse of the delay timer 11, but the start of counting is delayed until the trigger pulse is received after the generation of the delay pulse. When the trigger pulse is input, the post counter counts the set number and then stops the counting operation of the address counter.

As a result, the CH1 input signal waveform is recorded based on the first trigger pulse, the CH2 input signal waveform is recorded based on the second trigger pulse, and the CH3 input signal waveform is recorded based on the third trigger pulse. It is recorded based on the trigger pulse of. The recorded signal waveforms are displayed on one screen on the cathode ray tube 6.

In this case, if a signal output from the same circuit portion of the electronic device is input to each of CHs 1, 2, and 3, changes with time of the signal passing through the circuit portion can be seen.

It is also possible to set the address control circuits 16 and 20 for CH2 and CH3 to continue to operate alternately in response to the generation of a trigger pulse.

Next, the operation of analyzing the waveform data in the waveform recording apparatus of the embodiment will be described. In this waveform recording device, it is possible to compare and analyze the waveforms of the signals input from the respective channels. Further, in order to carry out the comparison and analysis, the sample rate in waveform recording of each signal can be adjusted.

The adjustment of the sample rate is performed by using the frequency dividers of the address control circuits 8, 16 and 20 described above.

For example, when the signal shown in D of FIG. 4 is input to CH1 and the signal shown in E of FIG. 4 is input to CH2, C
Set the division ratio of the divider in the H1 address control circuit 8 to 1
/ 2 and the frequency division ratio of the frequency divider in the CH2 address control circuit 16 is set to 1.

In CH1, of the waveform data output from the A / D converter 2, only the data for every two times is recorded in the waveform memory 3 in the order of elapsed time. Therefore, the sample rate at the time of waveform acquisition is 5 Mc / s, and the waveform recording period is 204.8 μs (T _{7 to} T _{9 in} FIG. 4). The waveform data obtained at this time is displayed on the screen of the cathode ray tube 6 as shown in FIG.
It is displayed like d.

On the other hand, in CH2, since the frequency division ratio of the frequency divider of the address control circuit 16 is 1, the waveform data output from the A / D converter 14 is recorded in the waveform memory 15 as it is. Therefore, the sample rate is 10 Mc / s, and the waveform recording period is 102.4 μ after generation of the delay pulse.
s (T _{8 to} T _{10 in} FIG. 4). This waveform data is displayed on the screen of the cathode ray tube 6 as shown in FIG.

As described above, in the waveform recording apparatus of the embodiment,
By changing the division ratio of the frequency dividers included in the address control circuits 8, 16 and 20, the sample rate of the waveform data recorded in the waveform memories 3, 15 and 19 of the respective channels is changed, whereby the waveforms are changed. The recording time can be set for each channel.

Further, the arithmetic circuit 21 inputs the waveform data of a desired channel among a plurality of waveform data stored in the display memory 4 via the data transfer bus and executes arithmetic operations such as four arithmetic operations. The calculation result is transferred again to the display memory 4 via the data transfer bus. As a result, the waveform data after calculation is displayed on the screen of the cathode ray tube 6. As an example of the calculation, ed of FIG. 5 displays the result of subtracting the waveform d from the waveform e.

In this waveform recording device, the data recorded in the waveform memories 3, 15 and 19 are not only displayed on the cathode ray tube 6 but also sent from the memory corresponding to the display memory 4 to other devices. It is also possible to adopt a configuration in which data is directly transferred from the waveform memory to an external device. In the latter case, the waveform analysis work can be shared by the external device.

Further, the waveform display can be performed by converting the data of a plurality of waveforms stored in the display memory into another display system, for example, data such as a video signal.

In the embodiment, the case where the number of channels is 3 has been described, but it is clear from the description of the operation of the embodiment that the number of channels does not matter. When the number of channels is set to n, the delayed waveform for n channels can be displayed on the screen of the same cathode ray tube 6 by stopping the waveform input operation when the waveform data of the input signal of n channels is obtained. it can.

[0068]

As is apparent from the above description of the embodiments, the waveform recording apparatus of the present invention has the following effects. 1. It is possible to perform waveform observation on signals under measurement applied to a plurality of channels with reference to different time points. 2. By calculating waveform data at different time points, it is possible to execute waveform analysis beyond the concept of time. In particular, it is possible to provide an analysis means suitable for correcting a time delay such as analysis of a signal under measurement in a transmission system in which a time delay occurs and executing an operation represented by a difference signal for analysis. 3. The sample rate of the waveform data to be recorded can be set for each channel, and the waveforms can be displayed on the same time axis in a form that allows easy comparison. Therefore, it is possible to provide a waveform observing unit suitable for technical experiments such as time compression.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a waveform recording apparatus according to an embodiment of the present invention,

FIG. 2 is a waveform diagram showing a signal input to each channel of the waveform recording device,

FIG. 3 is a waveform diagram displayed on the screen of the waveform recording device,

FIG. 4 is another waveform diagram showing a signal input to the waveform recording device,

FIG. 5 is a waveform diagram displayed on the screen after being processed by the waveform recording device.

[Explanation of symbols]

 1, 13, 17 Preamplifier 2, 14, 18 A / D converter 3, 15, 19 Waveform memory 4 Display memory 5 X signal generator 6 CRT 7 Clock oscillator 8, 16, 20 Address control circuit 9 Y signal generator 10 Trigger Circuit 11 Delay timer 21 Arithmetic circuit

Claims (3)

[Claims] 1. An A / D converter having a plurality of channels, which A / D-converts a signal input to each channel,
A waveform recording apparatus comprising: a waveform memory for recording the waveform data of a D-converted input signal; a trigger generating unit that outputs a trigger pulse based on the level of the signal input to a reference channel; A delay pulse generating means for generating a delay pulse after a lapse of a set time from a base point, and an address control means for controlling recording of waveform data in the waveform memory of each channel based on the trigger pulse or the delay pulse are provided. A waveform recording apparatus, wherein each of the control means is set so as to perform the control based on a different trigger pulse or a delayed pulse generated based on a different trigger pulse. 2. The waveform recording apparatus according to claim 1, wherein a sample rate of the waveform data recorded in the waveform memory can be changed by the address control means. 3. The waveform recording apparatus according to claim 1, further comprising arithmetic means for performing an arithmetic operation using the waveform data recorded in each of the waveform memories.