JPH07120368B2 - Crosstalk noise analysis method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of analyzing crosstalk noise generated in a transmission line such as a printed wiring board.

[0002]

2. Description of the Related Art Conventionally, in the case of analyzing this kind of crosstalk noise, logical connection information of circuit elements of an electric circuit and physical connection information such as a parallel length of a pattern on a printed wiring board are also used. In addition, crosstalk noise is analyzed by performing transmission line simulation with a circuit simulator or a transmission line simulator.

[0003]

However, in the conventional crosstalk noise analysis method, the other transmission lines close to the transmission line to be analyzed and the timing of the change in the signals of those transmission lines are unknown. Therefore, conventionally, the analysis is performed under the virtual timing condition that the transmission line to be analyzed is most affected by the crosstalk noise, and if there is a problem in the analysis result, the design change is taken. In addition, even if there is a problem in the analysis result, it is unlikely that the actual circuit will have a virtual timing condition and there will be no problem in design quality, but even in such a case, it is common to make a design change. It was As described above, in the conventional case, it is difficult to accurately analyze the crosstalk noise, and there is a problem that an unnecessary design change is caused.

The present invention has been made in view of such circumstances, and enables more accurate analysis of crosstalk noise, thereby eliminating wasteful design changes,
The purpose of the present invention is to provide a crosstalk noise analysis method capable of improving design efficiency.

[0005]

The crosstalk noise analysis method of the present invention comprises a logical connection information storage means for storing logical connection information of an electric circuit to be analyzed, and a physical connection of the electric circuit. physical connection information storage means for storing connection information, a delay analysis means for analyzing a delay in the transmission line of the signal of said electrical circuit, the physical connection information and the said physical connection information storage means Timing for detecting the timing of signal change of the transmission line to be verified and the transmission line adjacent thereto from the analysis result of the delay analysis means
And an information detection means, said logical connection information storage means
Logical connection information, the physical of the physical connection information storage means
Connection information, and the row Ukoto transmission line simulation based on the timing information of the timing information detection unit
By, is characterized in that analyzing the crosstalk noise.

[0006]

In the present invention, the delay analysis means analyzes the signal delay of the transmission line, and the timing information detection means uses the analysis result and the physical connection information of the electric circuit to transmit the signal to be verified.
Detecting a timing of a change in the transmission line and the transmission line of the signal close to it. Logical timing information and electrical circuits obtained in crosstalk noise analyzing means, the row transmission line simulation based on the physical connection information Ukoto
The crosstalk noise is analyzed by. Therefore, the circuit
Not only the logical connection information and physical connection information of
By performing the transmission line simulation using the timing information of the signal change of the test transmission line and the transmission line adjacent thereto , the crosstalk noise can be accurately analyzed.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the crosstalk noise analysis method of the present invention. In FIG. 1, reference numeral 1 is a logical connection information storage means for storing logical connection information of an electric circuit to be analyzed. This logical connection information is what is called a net list, and is logical connection information indicating how each element such as a gate circuit or a flip-flop circuit on the circuit is connected. 2 is a physical connection information storage means for storing the physical connection information of the electric circuit.
That is, the physical connection information is the physical connection information after layout when actually arranging each circuit element of the electric circuit on the printed wiring board and connecting each circuit element with the printed wiring pattern. This is information that represents the physical positional relationship of the transmission lines such as the parallel wiring length.

Reference numeral 3 denotes a test for storing test pattern information for performing timing simulation.
It is a pattern information storage means. The test pattern information for predetermined timing simulation such as the condition of the input signal input to the input pin of the electric circuit is stored in this. Reference numeral 4 is a delay analysis means for performing timing simulation. Here, a timing simulator is used as the delay analysis unit 4. To the delay analysis means 4, the logical and physical connection information of the logical connection information storage means 1 and the physical connection information storage means 2 and the test pattern information of the test pattern information storage means 3 described above are sent, and the delay analysis is performed. The means 4 executes the timing simulation using these pieces of information. Here, when performing the timing simulation, since the physical connection information is used as described above, the time taken for the signal to propagate through the transmission line conforms to the actual circuit. The timing simulation can be performed under the same conditions as the actual circuit by adding the connection information.

In this way, the delay analysis means 4 can
A simulation is performed, and how a signal changes at a predetermined observation point A signal delay in an element that drives on a transmission line is output as a result of the timing simulation. The result of this simulation is stored in the delay analysis result storage means 5. The simulation result of the delay analysis result storage means 5 and the connection information of the physical connection information storage means 2 are sent to the timing information detection means 6, where they are applied to the transmission line to be analyzed based on the above two pieces of information. The timing of the change in the signal of the transmission line adjacent to the transmission line is detected.

FIG. 2 is a diagram showing an example of a wiring pattern on a printed wiring board. Here, the wiring 11 in the same layer is provided in parallel to the wiring 10 and the wiring 10
On the other hand, the lower wiring 12 is also provided in parallel. Therefore, the wiring 10 is capacitively coupled and inductively coupled with the wirings 11 and 12, and receives crosstalk noise due to changes in signals of these wirings 11 and 12. The physical connection information of such wiring is, of course, the physical connection information storage means 2
It is stored in. FIG. 3 is a diagram in which the wiring shown in FIG. 2 is modeled as a circuit of a transmission line. Where wiring 1
The change of the signal of 0, 11, and 12 is the driver 1 respectively.
The timing information detecting means 6 detects the timing of the change of the signal of each wiring by the respective drivers 13 , 14 , and 15.

The obtained timing information is stored in the timing information storage means 7. The timing information of the timing information storage means 7 is sent to the crosstalk noise analysis means 8, and the crosstalk noise analysis means 8 executes a transmission line simulation based on this timing information and the above-mentioned logical connection information and physical connection information. . For example, the figure
2 and the wiring 10 described in FIG.
And the required transmission line to be verified.
And the wiring 1 that is close to the wiring 10.
Transmission line stain using the timing information of signals 1 and 12
Perform an operation. As a result, how much crosstalk noise leaks from the other transmission line into the analysis target transmission line is analyzed. This completes the series of crosstalk noise analysis processing. If there is a problem as a result of this analysis, the design change of the circuit or layout is taken, and if there is no problem, the circuit design and the layout design are finished assuming that the design standard is satisfied.

As described above, in the present embodiment, the transmission line simulation is performed based on not only the logical connection information and the physical connection information but also the timing information of the signal change of the transmission line close to the analysis target transmission line. As a result, the simulation can be performed under the conditions according to the actual circuit operation, and the crosstalk noise can be analyzed more accurately than in the conventional case. Therefore, even if there is no problem in design quality as in the past, there is no waste of making design changes, and since it is only necessary to make design changes when necessary, it is possible to greatly improve design efficiency compared with the conventional design. .

FIG. 4 is a block diagram showing another embodiment of the present invention. In the embodiment of FIG. 1, the delay analysis means 4 analyzes the delay of the signal on the transmission line by performing a timing simulation based on the test pattern information and the like. -The same delay analysis processing is performed by the timing verifier. The delay analysis means 9 drives the transmission line of the circuit by comprehensively performing path traces on all paths based on the connection information of the logical connection information storage means 1 and the physical connection information storage means 2. The delay time of the signal in the element is analyzed. That is, the timing of the signal change at each path point on the circuit based on the change of the clock signal is analyzed. Therefore, the delay time of the signal of the circuit is analyzed as in the timing simulation of the embodiment of FIG. 1, and the obtained result is stored in the delay analysis result storage means 5.

In the timing information detecting means 6, similar to the embodiment of FIG. 1, based on the physical connection information and the result obtained by the delay analyzing means 9, the change of the signal of the transmission line close to the transmission line to be analyzed is detected. Timing is detected. Further, the crosstalk noise analyzing means 8 performs a transmission line simulation based on the above timing information, logical connection information and physical connection information, and analyzes the crosstalk noise. This completes the series of analysis processing for crosstalk noise in the transmission line. Therefore, also in this embodiment, the crosstalk noise can be analyzed exactly as in the embodiment of FIG.

[0015]

As described above, the present invention is based on the theory of circuits.
Not only physical connection information and physical connection information, but also verified transmission
Timing information of signals on the transmission line and transmission lines adjacent to it
By performing transmission line simulations using
The simulation under conditions that match the actual circuit operation.
Therefore, the crosstalk noise can be analyzed more accurately than before . Therefore, as in the past
Even if there is no problem with the design quality, we will make design changes.
There is an effect that unnecessary design changes can be eliminated and the design efficiency can be significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a crosstalk noise analysis method of the present invention.

FIG. 2 is a diagram showing wiring of a printed wiring board as an example of a transmission line that is an analysis target of crosstalk noise.

FIG. 3 is a diagram in which the wiring of FIG. 2 is modeled as a circuit of a transmission line.

FIG. 4 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 logical connection information storage means 2 physical connection information storage means 3 test pattern information storage means 4, 9 delay analysis means 5 delay analysis result storage means 6 timing information detection means 7 timing information storage means 8 crosstalk noise analysis means

Claims (3)

[Claims] 1. A and logical connection information storage means for storing the logical connection information of the electric circuit to be analyzed, the physical connection information for storing physical connection information of the electric circuit
Information storage means, delay analysis means for analyzing a signal delay of a transmission line in the electric circuit, and the physical connection information
Timing information for detecting a physical connection information and timing of change of the signal transmission line adjacent the analysis result to the transmission line and its verification target of the delay analysis means storage means
And a distribution detection means, logical of the logical connection information storage means
Physical connection information, physical contact <br/> connection information of said physical connection information storage means, and a transmission line simulation in the row Ukoto based on the timing information of the timing information detection unit
A crosstalk noise analysis method characterized by analyzing crosstalk noise. 2. The delay analysis means is based on predetermined test pattern information for timing simulation and respective connection information stored in the logical connection information storage means and the physical connection information storage means. 2. The crosstalk noise analysis method according to claim 1, wherein the delay analysis of the signal is performed by performing a timing simulation. 3. The delay analysis means comprehensively performs a path trace based on the respective connection information stored in the logical connection information storage means and the physical connection information storage means, thereby delaying a signal. The crosstalk noise analysis method according to claim 1, wherein analysis is performed.