JPH07118727B2 - Digital 4-phase modulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a four-phase phase modulator, and more particularly to a digital waveform in which the modulation circuit is entirely digitalized and has a high degree of freedom in terms of modulation speed and modulation output frequency. Digital 4 of compound molding
The present invention relates to a phase modulator.

[Conventional technology]

Conventionally, as means for digitally shaping a signal equivalent to a signal obtained by a normal phase modulation means, there is, for example, JP-A-53-24763.

In the above prior art, a table index type filter by ROM is used for the waveform shaping filter, the response characteristics of the filter corresponding to the modulation output frequency, sampling rate, etc. are stored in ROM, and the output corresponding to the input signal is output from ROM. Then, the waveforms are synthesized by digitally converting into a modulated waveform.

[Problems to be solved by the invention]

The above-mentioned conventional technique is a method of writing the response characteristics of the filter corresponding to the modulation output frequency and the sampling rate in the ROM of the table index type digital filter using the ROM used for the waveform shaping filter. There is a problem in that it is necessary to change the contents of the ROM in the case of changing or changing the modulation output frequency, and it is not possible to cope with the case where the same circuit is adapted to various transmission speeds.

It is an object of the present invention to provide a digital quadrature phase modulator which can easily obtain a desired modulation output frequency.

[Means for solving problems]

According to the present invention, in order to solve the above problems, the sampling period of the output signal of the waveform shaping digital filter corresponding to the two series of input data I and Q of the four-phase phase modulation is 1 / m (m) for each of I and Q. Is a positive integer of 2 or more), a means for interpolating the time interval in the sampling period with m-1 data is used. Then, the I and Q data after the interpolation are thinned out every other I and Q at different timings, and the polarity of the thinned data is inverted every other one, that is, +
By alternately multiplying 1 and -1 and adding the I and Q outputs, the output waveform of the four-phase modulation is digitally combined. This composite output is D / A converted, and the output is passed through a low-pass filter for harmonic elimination,
Get analog modulation output.

[Action]

In the waveform synthesizing process, the frequency of the modulation output can be selected by arbitrarily setting the value of the interpolation number m. Further, when various values are taken as the cycle of the waveform shaping digital filter output, the modulation output frequency is set to a constant value by selecting the value of the interpolation number m corresponding to each cycle. You can

Further, if the sampling number of the waveform shaping digital filter for the input data I and Q is a constant number n (n is a positive integer) per one cycle of the input data, the waveform shaping digital filter clock is set to the cycle of the input data I and Q. It is possible to match with the corresponding period, and the circuit of the waveform shaping filter can be made the same. Then, if the interpolation number m is selected corresponding to the cycle of the input data, the modulation output frequency can be made constant regardless of the cycle of the input data.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows the waveform of each part in FIG. 1 imitating an analog waveform. In FIG. 1, 1-1 and 1-2 are input data I and Q for four phase modulation, 2-1 and 2-2 are waveform shaping digital filters, and 3 and 3, respectively.
-1,3-2 is an interpolation circuit, 4-1 and 4-2 are data selection circuits,
Reference numerals 5-1 and 5-2 are sign inversion circuits, 6 is an addition circuit, 7 is a D / A converter, 8 is a low-pass filter, and 9 is a modulation output signal.

Next, the operation of FIG. 1 will be described. Input data I in Fig. 1,
Q is, for example, a signal having a waveform shown in FIG. 2 (a), which is shaped by the waveform shaping filters 2-1 and 2-2 so that the frequency spectrum of the modulation output has a shape suitable for transmission. . The output of this waveform shaping filter is shown in FIG. FIG. 2B is a diagram in which one cycle of the input data in FIG. 2A is sampled by 4 and the above-described value of n is 4. As this waveform shaping filter, a table index type digital filter using a ROM as disclosed in the above-cited Japanese Patent Laid-Open No. 53-24763 can be applied as an example.

Waveform shaping digital filter output is interpolator 3-1 and 3
At -2, data is interpolated with m-1 data so that the data cycle becomes 1 / m. The analog waveform of the output of the interpolation circuit is as shown in FIG. FIG. 2 (c) shows the complement count m = 4.
The waveform in the case of is imitated and displayed as an analog waveform.

The interpolated output is thinned out every other time slot by the data selection circuits 4-1 and 4-2 at different timings on the I side and the Q side, and the output is output by the sign inversion circuits 5-1 and 5-2. 1
The sign is inverted every other data. The analog waveform output of the sign inversion circuit is as shown in FIG.

This output is added in the adder circuit 6, and the output is
The D / A converter 7 converts the analog signal, the low-pass filter 8 removes the harmonic component, and the modulated output wave 9 is output to the output terminal. The analog waveform of the output of the adder circuit 6 is
As shown by the solid line in FIG. 2 (e), the low-pass filter 8
The output waveform of is the waveform shown by the dotted line in FIG.

FIG. 3 shows an embodiment of the interpolation circuits 3-1 and 3-2 and the clock generation circuit of FIG.
2, 13, 16, 19 are latch circuits, 14 is a subtraction circuit, 15 is a division circuit, 17 is an addition circuit, 18 is a selector circuit, 20 is an interpolation circuit output signal, 31 is a clock oscillator, 33, 32, 34 Is a frequency divider, 35
Is a clock output synchronized with the input data, and 36 is a waveform shaping digital filter clock output.

In FIG. 3, the interpolation circuit input signal 11, that is, the waveform shaping filter output is temporarily stored in the latch circuits 12 and 13. The latch circuit 12 stores data one time slot after the latch circuit 13. The subtraction circuit 14 obtains the difference between the data temporarily stored in the latch circuits 12 and 13, that is, the difference between the outputs of the digital filters temporally adjacent to each other. The difference is calculated for each data after the interpolation, and this is temporarily stored in the latch circuit 16.

The output of the latch circuit 16 is the output of the interpolation circuit in the adder circuit 17.
20 is added together and sent to the selector circuit 18. Immediately after the interpolation circuit input data is stored in the latch circuits 12 and 13, the selector circuit 18 selects and outputs the output of the latch circuit 13. That is, the data one time slot before is output. The result is stored in the latch circuit 19 and the output signal
Output as 20. Next, the selector circuit 18 is switched to the adder 17 side, adds the value stored in the latch circuit 19 and the above-mentioned difference for each interpolation stored in the latch circuit 16, and stores the result in the latch circuit 19. The generated data is updated and is output as the output signal 20. The above operation is repeated m-1 times, and at the m-th time, the input data is shifted to the latch circuits 12 and 13, respectively, so that m-1
Interpolation of the γ section of the waveform shaping filter output can be performed with this data.

Note that the above example is an example using the simplest linear interpolation, but it goes without saying that a more accurate interpolation method can be used.

The clock oscillator 31 shown in FIG. 3 is an original oscillator for supplying a clock necessary for each part of the present invention.
Then, a clock having the same cycle as the data rate after interpolation is formed and used as a latch pulse of the latch circuit 19. The output of the frequency dividing circuit 32 is 1 / m by the frequency dividing circuit 33 to form data before interpolation, that is, a clock having the same cycle as the digital filter output, and the latch circuits 12 and 13 and the selector circuit 18 are formed.
It is used as a pulse to operate. Further frequency divider
The output of 33 is divided by 1 / n in the frequency dividing circuit 34 to form a clock having the same cycle as the input data 1-1 and 1-2 of FIG. 1 and used in the digital filters 2-1 and 2-2. To be When the input data 1-1 and 1-2 are synchronized by an external clock, the clock and the output 35 of the frequency dividing circuit 34 in FIG. 3 are phase-compared, and the clock oscillator 31 is used by the PLL circuit. Phase synchronization should be taken.

FIG. 4 shows an embodiment of the data selection circuits 4-1 and 4-2 of FIG. 1, 41 and 42 are data selection circuit inputs, 43 and 44 are flip-flop circuits, and 45 and 46 are output circuits. . In the above, the quantity represented by a plurality of bits is represented by one line or one circuit. Further, 47 is a clock input synchronized with the inputs 41 and 42, 48 is a frequency dividing circuit with a frequency dividing ratio of 1/2, and 49 is a phase inverting circuit.

In FIG. 3, the input data 41 is a clock obtained by dividing the clock input 47 by 1/2 by the frequency dividing circuit 48, and is temporarily stored in the output by the flip-flop circuit 43. Meanwhile input data
42 is a clock obtained by inverting the frequency-divided clock by the phase inverting circuit 49 and temporarily stored in the flip-flop circuit 44. That is, since the input data 41 and 42 are stored once every two clocks, and the inputs 41 and 42 are temporarily stored with mutually inverted clocks, 1
It is possible to obtain outputs 45 and 46 which are decimated by time slots.

FIG. 5 shows another embodiment of the present invention. In the figure, reference numeral 5 is a sign inverting circuit for inverting the sign every two time slots. Others are the same as in FIG. In the embodiment of FIG. 1, after the data is thinned out by the data selection circuits 4-1, 4-2, the sign is inverted by the sign inversion circuits 5-1 and 5-2, respectively, and then added. The embodiment is different in that after the outputs of the data selection circuits 4-1 and 4-2 are added, the sign is inverted every two time slots. Everything else is the same as that of the embodiment shown in FIG. 1, and the characteristics of the waveform-synthesized modulator circuit output are exactly the same.

When the present invention is applied to the offset four-phase phase modulation in which the data switching point is shifted by a half cycle between the input data I and Q among the four-phase phase modulation, when the input data is used for the waveform shaping digital filter. After shifting I or Q by half a cycle, the filter may be operated at a sampling rate n times the transmission rate of the input data and output at the same I and Q timing. The operations after the interpolation can be performed exactly the same. However, the value of n must be an even number in order to obtain a waveform shaping filter output at the same I and Q timing.

〔The invention's effect〕

According to the present invention, since the four-phase phase modulation waveform is synthesized after interpolating one time slot of the waveform shaping digital filter output data with a plurality of data, the modulation output frequency is changed in the contents of the waveform shaping digital filter. Instead, the desired frequency can be set only by changing the number of interpolations.

Further, even if the cycle of the waveform shaping digital filter output changes variously, the modulation output frequency can be made a constant value by selecting the interpolation number to an appropriate value. Further, if the sampling number of the waveform shaping digital filter for one time slot of the input data is kept constant, the output frequency will be kept constant if the interpolation number is also selected correspondingly when the transmission rate of the input data changes. It is possible to

As an example, the input data transmission rates are 16 Kb / s and 32 I and Q respectively.
When obtaining 4-phase phase modulated waves of Kb / s, 48Kb / s, 64Kb / s, 96Kb / s, 128Kb / s, 256Kb / s, if the sampling number of the waveform shaping digital filter in one cycle of input data is 16 ,
By setting the number of interpolations to 48, 24, 16, 12, 8, 6, and 3, respectively, the modulation output frequency can be 3.072 MHz. Further, if the number of interpolations is doubled, the modulation output frequency can be 6.144 MHz.

When this modulator is applied to a wireless line using this function, the transmission rate can be instantly lowered and a certain level of line quality can be maintained by changing the number of interpolations when the line condition deteriorates. Also, if this modulator is applied as a common standby device for the modulators of multiple radios with different transmission rates, the standby number can be changed by changing the number of interpolations to match the transmission rate of the active device when switching to the active device. It is possible to easily switch between the active machine and the standby machine according to the transmission speed of the active machine and to prepare the standby machine economically.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram in the main part of the embodiment shown in FIG. 3, FIG. 3 is an embodiment of the interpolation circuit shown in FIG.
FIG. 5 shows an embodiment of the data selection circuit of FIG. 1, and FIG. 5 shows another embodiment of the present invention. 2-1, 2-2 ... Waveform shaping digital filter, 3-1, 3
-2 ... Interpolation circuit, 4-1 and 4-2 ... Data selection circuit,
5-1 and 5-2 ... Code conversion circuit, 6 ... Adder, 7 ...
Digital-analog conversion circuit, 8 ... Low-pass filter.

Claims (2)

[Claims] 1. A digital four-phase phase modulator having a waveform shaping digital filter corresponding to two series of input data I, Q, wherein the sampling period of the waveform shaping digital filter is 1 / m (I / Q) respectively. (m is a positive integer of 2 or more) means for interpolating the time interval of the sampling cycle with m-1 data, and I, after interpolation by the interpolation means.
A means for thinning out every other Q data at different timings from I and Q is provided, and the composite output of the I and Q data after thinning out is subjected to digital / analog conversion to make a four-phase phase modulated wave of an arbitrary frequency. A digital quadrature phase modulator, which is characterized in that 2. The output timing of either the I side or the Q side of the waveform shaping digital filter is set to 1/2 of the fundamental period of the input of the waveform shaping digital filter according to claim 1. A digital 4-phase modulator that delays.