JPH07111631A - Video signal processor - Google Patents

Abstract

PURPOSE:To detect the location of a scene change and to easily perform a desired image processing in the scene change by a user. CONSTITUTION:Supplied digital signals A are supplied as signals B delayed by one-frame in a memory 2 to a memory 8 and a subtraction circuit 3. The difference value calculated in the subtraction circuit 3 is supplied to an absolute value sum circuit 4, the calculation of the total sum of the absolute values of the difference value corresponding to one frame and the averaging are performed, and they are supplied to a comparison circuit 5. The comparison circuit 5 compares the supplied signals and threshold TH and supplies a comparison output signal f to a memory control circuit 7. The memory control circuit 7 reads a writing control signal Winh for a memory 8 when the signal f changes to '1' and supplies the writing control signal to the memory 8. In the memory 8, the image just before a scene change is rewritten to the image on and after the scene change in accordance with the signal Winh and the image is outputted as an output signal C to an output terminal 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus suitable for application to an image reproducing apparatus such as a VTR or an optical video disk reproducing apparatus, an editing apparatus and the like.

[0002]

2. Description of the Related Art Conventionally, there has been a technique for replacing images before and after a scene change with a cross fader.
However, this scene change is judged based on the intention of the software production side, and after the software production is distributed to the user, the user may change the scene change from the crossfader. It cannot be processed.

[0003]

However, when the user responds to the demand to replace the image before the scene change with the image after the scene change by a different method, there is no method that can be easily realized. To change the processing of the scene change point to another method different from the crossfader, find the position of the scene change, determine the cut length and scene change method, and change the IN point,
It is necessary to set the OUT point, use the editing machine, and edit the whole story again, which is a troublesome work.

Therefore, the present invention relates to a video signal processing device which is composed of a simple circuit and can perform a user-oriented scene change.

[0005]

SUMMARY OF THE INVENTION According to the present invention, in a video signal processing device to which a video signal is supplied and which processes a scene change included in the video signal, the sum of absolute values of frame differences is compared with a threshold value. By detecting the scene change of the video signal, and in response to the detection of the detecting means, the stored scene immediately before the scene change is rewritten to the scene after the scene change, and the size of the rewritten portion or A video signal processing device comprising: a control means for controlling the density so as to change with time.

[0006]

By providing a circuit for detecting a scene change, the position of the scene change can be known. By controlling the rewriting of the memory in which the output image is stored, the user can set the image switching process at the scene change portion as desired.

[0007]

FIG. 1 shows the configuration of an embodiment of the present invention. The input signal supplied from the input terminal 1 of FIG. 1 is a luminance signal and a color difference signal after Y / C separation of a video reproduction signal of a VTR, an LD (optical video disc reproduction device), etc. It is an 8-bit digital signal AD-converted by fs1 and fs2, respectively. Since the present invention uses the same signal processing method for the luminance signal and the color difference signal, the luminance signal is shown as an example in this embodiment.

In FIG. 1, the input 8-bit luminance signal A is supplied from the input terminal 1 to the memory 2 and the subtraction circuit 3, respectively. The signal A is delayed by one frame by the memory 2. The output signal B of the memory 2 is supplied to the subtraction circuit 3 and the memory 8, respectively. The difference (AB) between the signal A of the current frame and the signal B of the previous frame is calculated for each pixel in the subtraction circuit 3, and the calculation result, that is, the difference value is supplied from the subtraction circuit 3 to the absolute value sum circuit 4. To be done. The structure of the absolute value sum circuit 4 is shown in FIG.

As shown in FIG. 3, the difference value supplied from the input terminal 11, that is, the subtraction circuit 3 is
The absolute value circuit 12 converts the absolute value. The absolute value difference of the calculation result of the absolute value circuit 12 is the absolute value circuit 1
It is supplied from 2 to the adder circuit 13. The supplied absolute value differences are integrated in the adder circuit 13 over the period of one frame, and the total sum of the absolute difference values for each pixel is calculated for one frame. The output of the adder circuit 13 is supplied to the averaging circuit 14 and divided by the total number of pixels in one frame. The average value of the divided absolute difference values is supplied from the averaging circuit 14 to the register 15.

The register 15 outputs the supplied average value from the output terminal 17 in synchronization with the frame clock input from the terminal 16. Further, in order to simplify the hardware, the representative points in the frame may be extracted and the processing of the absolute value sum circuit 4 may be performed on the representative points. After the processing of the absolute value sum circuit 4 is completed, the average value is supplied from the absolute value sum circuit 4 to the comparison circuit 5.

In the comparison circuit 5 to which the average value is supplied from the absolute value sum circuit 4, the average value is compared with the threshold value TH supplied from the terminal 6. When the supplied average value is larger than the threshold value TH, the output signal f of the comparison circuit 5 becomes a high level (represented by `1 '), and when the supplied average value is smaller than the threshold value TH, the comparison circuit 5 5 output signal f
Is low level (denoted as `0 '). That is, as a result of the scene change, a large difference occurs between the frames before and after the scene change.
The output signal f of 1 becomes "1". The output signal f of the comparison circuit 5 is supplied to the memory control circuit 7.

A timing chart of this embodiment is shown in FIG. FIG. 2 shows a case where a scene change occurs between the frame clocks T _n and T ₀ . Image F ₀ of signal A of the current frame and image F of signal B one frame before
_n and _n are processed in the absolute value sum circuit 4, and the output signal (average value per pixel) of the absolute value sum circuit 4 is supplied from the terminal 6 in the comparison circuit 5 at the next frame clock T _1. Is larger than the threshold TH that is set. In that case, the output signal f of the comparison circuit 5 changes from "0" to "1". Then, at the next frame clock T ₂ ,
Since the average value is smaller than the threshold value TH, the signal f is
Change from `1 'to` 0'.

The memory control circuit 7 to which the signal f is supplied from the comparison circuit 5 is a write control signal Win of the memory 8.
The h (write inhibit) signal is generated as described later. The write control signal Winh is a control signal for rewriting the image immediately before the scene change, which is supplied to the memory 8, to the image after the scene change.

In the example of FIG. 2, the write control signal W starts from the frame clock T ₂ and ends at T ₃ , T ₄ , ... T _29.
The `0 'section of inh gradually expands. The memory 8 is writable while the write control signal Winh is "0". Therefore, the content of the memory 8 is rewritten from the memory 2 to the new content (that is, the image after the scene change) by gradually expanding the period of "0". Further, FIG. 7 shows the time change of the reproduced image corresponding to the output signal C read from the memory 8. FIG. 7A shows
1 shows the time change of the image corresponding to the input signal A supplied to 1, and FIGS. 7B to 7F show the time change of the output image. Figure 7
B is an example of upper and lower wipes in which images are gradually switched from the lower part to the upper part of the screen.

Here, an example of the configuration of the above-mentioned memory control circuit 7 is shown in FIG. In the example of FIG. 4, the signal (output signal of the comparison circuit 5 in FIG. 1) f supplied from the input terminal 21 is supplied to the register 22 and the NAND gate 24, respectively. This signal f is delayed by one pixel clock in synchronization with the pixel clock supplied from the terminal 23, and the inverted output of the register 22 is supplied to the NAND gate 24. That is, the register 22 and the NAND gate 24 generate a differential pulse when the value of the supplied signal f rises from "0" to "1". The generated rising differential pulse is supplied to the clear terminal CLR of the counter 25.

The counter 25 starts counting operation of the line clock input from the terminal 26 after being cleared by the differential pulse supplied from the NAND gate 24. The line clock supplied from the terminal 26 is also supplied to the clock input terminal of the register 29. The output of the counter 25 is supplied to the ROM 27 as the address ADR. The data described later corresponding to the address ADR is read from the ROM 27.

The data read from the ROM 27 outputs the write control signal Winh to the output terminal 30 in synchronization with the line clock supplied from the terminal 26 by passing through the register 29. Also, the ROM 27
Also outputs an enable signal EN to the counter 25. In this example, since the scene change is completed in 30 frames, the enable signal EN of the counter 25 becomes inactive when the data for 30 frames is output, and the counting operation of the counter is stopped.

FIG. 5 shows a timing chart of the memory control circuit 7 of this embodiment. In FIG. 5, the write control signal Winh in the parenthesis is an example when the upper and lower wipes are performed from the upper part of the screen different from this embodiment.

FIG. 6 shows an example of data previously written in the ROM 27. The data in the ROM 27 is wiped up and down from the lower part of the screen in synchronization with the line clock. During the first frame clock T ₀ after the scene change, all the write control signals Winh
It is “0”, and at this time, the image F _n just before the scene change is written in the memory 8.

Here, FIG. 6 will be described. The dotted line shown in FIG. 6 indicates the boundary of one frame. Enable signal EN
Is an address (0
(-15749), all show "1". Also, in this embodiment, the address changes in synchronization with the line clock. The change of the write control signal Winh corresponding to the address will be described below.

In the period of the frame clock T ₀ , that is, in the address ( ₀ to 524), the write control signal Winh
Shows all `0 ', the memory 8, the image F <sub>n</sub> of immediately before a scene change is written. At the address (525 to 1049) corresponding to the period of the next frame clock T <sub>1</sub> , the write control signal Winh changes to the address (525 to
989) indicates `1 ', and the address (990 to 104)
In 9), it indicates `0 '. This is because the 60 scanning lines corresponding to the lower position of the screen of the image F _n immediately before the scene change stored in the memory 8 are rewritten into the 60 scanning lines corresponding to the same position of the image F ₀ , and the output signal C is output. As Figure 7
Generating an image of a F _a of B.

At the address (1050 to 1574) in the period of the frame clock T ₂ , the write control signal Winh
Indicates `1 'at the address (1050 to 1497),
The address (1498 to 1574) indicates `0`.
As a result, 77 scanning lines corresponding to the lower position of the screen of the image F _n immediately before the scene change held in the memory 8 correspond to the same position of the image F ₁ as in the above.
Rewriting to the scanning line of the book, and as an output signal C, F _b of FIG.
Generate an image of. In this way, in the data shown in FIG. 6, the size of the portion rewritten into the scene after the scene change changes with time.

The memory 8 supplied with the write control signal Winh from the memory control circuit 7 is gradually rewritten from the lower part of the screen to the image after the scene change as described above. As the image advances, the write control signal Winh becomes `
The area of 0'is expanded, and the area occupied by the image after the scene change is expanded. Therefore, the output image is generated such that the image corresponding to the time change after the scene change is wiped up and down from the lower part of the screen from the image immediately before the scene change.

Of course, when the upper and lower wipes are applied from the upper part of the screen, data different from the data shown in FIG.
It can be realized by writing in the OM 27 in advance. The time change of the output image at this time is shown in FIG. 7C. FIG. 7C is the same as FIG. 7A.
From the image Fn immediately before the scene change to the images F _{0 to} F ₂₉ after the scene change are the images wiped up and down from the upper part of the screen. Further, in the case of randomly switching the image on a line-by-line basis, similarly, it is possible to write data different from the data of the embodiment in the ROM 27 in advance.

In such a plurality of image switching methods, a memory (ROM 27) having a large capacity is prepared, a plurality of image switching data are written in advance in the memory (ROM 27), and a switching signal is supplied from the terminal 28. It is also possible to select a user's favorite process from a plurality of image switching data.

As another example of the processing, it is possible to change the line clock supplied from the terminal 26 to the counter 25 to a pixel-based clock (pixel clock).
In this case, an image in which the image immediately before the scene change is wiped from the left side or the right side of the screen by the image after the scene change is generated. Here, FIG. 7D shows the time change of the output image of the image Fn immediately before the scene change of FIG. 7A to the images F _{0 to} F ₂₉ after the scene change after the left and right wipe processing from the left part of the screen. In contrast to FIG. 7D, FIG. 7E shows the image F after the scene change.
_{0 to} F ₂₉ show the time change of the output image which has been subjected to the left and right wipe processing from the right part of the screen.

Further, by gradually decreasing the area "1" of the write control signal Winh on a pixel-by-pixel basis, the image immediately before the scene change and the image after the scene change may be switched on a pixel-by-pixel basis. Output image is obtained. FIG. 7F shows the time change of the output image when the image Fn immediately before the scene change of FIG. 7A to the images F _{0 to} F ₂₉ after the scene change are wiped in pixel units, that is, when the pixel random process is performed.

As the image switching data stored in the ROM, a method of recording the address and data of the change point may be used instead of storing all the data of each pixel or each line. This example will be described with reference to FIG. When the scene is changed, the address is "0".
The operation which is incremented by `+1 'starts from.
When the address is `0 ', the write control signal Winh is`
0 ', and the enable signal EN becomes'1'. Then, when the address `525 'which is the change point is reached,
The write control signal Winh changes from "0" to "1". After that, when the change point address is '990',
The write control signal Winh changes from "1" to "0". Further, the enable signal EN has the address `1575.
When it reaches 0 ', it changes from' 1 'to' 0 '.

That is, the write control signal Winh or the enable signal EN is "1" to "0", or
By holding the address that changes from "0" to "1" in the ROM and by holding the changed values of the write control signal Winh and the enable signal EN in the ROM, the write control signal and the enable signal are read, and Change the signal. Further, when reaching the address which is the change point, the respective values of the write control signal and the enable signal can be changed to signals different from the signals before reaching the address which is the change point.

[0030]

As described above, according to the present invention, by controlling the memory to be stored, it is possible to easily perform various user-oriented automatic scene change detections and various replacements of scenes before and after the scene change, which cannot be done conventionally. To summarize the effect, a user-oriented scene change different from the crossfader can be performed with a simple circuit configuration. By installing the above-mentioned automatic cross fader in a video playback device or an editing device, the editing function can be enhanced and the video editing can be made more enjoyable.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a crossfader according to the present invention.

FIG. 2 is an example of a schematic diagram showing a timing chart of the crossfader of the present invention.

FIG. 3 is an example of a block diagram constituting an absolute value sum circuit according to the present invention.

FIG. 4 is an example of a block diagram constituting a memory control circuit according to the present invention.

FIG. 5 is an example of a schematic diagram showing a timing chart of the memory control circuit according to the present invention.

FIG. 6 is an example of a write control signal held in the memory control circuit according to the present invention.

FIG. 7 is an example of a diagram showing a plurality of scene change methods of the present invention.

[Explanation of symbols]

 2, 8 memory 3 subtraction circuit 4 absolute value sum circuit 5 comparison circuit 7 memory control signal

Claims (1)

[Claims] 1. A video signal processing apparatus which is supplied with a video signal and which processes a scene change included in the video signal, compares the sum of absolute values of frame differences with a threshold value, In response to the detection by the detecting means for detecting a scene change, the stored scene immediately before the scene change is rewritten to the scene after the scene change, and the size or density of the rewritten portion is temporal. A video signal processing device, comprising: a control means for controlling so that the video signal processing device changes.