JPH07109877B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a DRAM (Dynamic Random Access Memory).
The present invention relates to a semiconductor memory device having an improved cell structure and a manufacturing method thereof.

(Prior Art) Referring to FIG. 5 and FIG. 6, a DRAM according to the prior art
The cell will be described.

FIG. 5 (a) and FIG. 5 (b) are based on the prior art.
In a plan view and a cross-sectional view of a DRAM cell, this cell is called a crosspoint cell.

In the plan view of FIG. 5A, the word line 10 of the DRAM cell is
A cell for 1 bit is formed at the intersection of 1 and the bit line 102. A capacitor having a so-called trench structure is used for the storage element of the DRAM cell, and the semiconductor substrate 10
A trench groove 103 is formed at 0.

FIG. 5B is a sectional view taken along section BB in FIG. 5A, and as shown in this sectional view, the semiconductor substrate 100 is
A P-type diffusion layer 104 is formed inside, and a P ⁺ -type diffusion layer 105 having a high impurity concentration is formed below the P-type diffusion layer 104,
A trench groove 103 is formed through the two diffusion layers, and a capacitor electrode 107 is formed in the trench groove 103.
And the word line 101 is formed. Further, the semiconductor substrate 100 is insulated from the semiconductor substrate 100 by the gate oxide film 106 and the capacitor insulating film 109 except for the buried contact portion 108.

As the operation of this DRAM cell, the potential applied to the bit line 102 increases the potential of the word line 101, and the P-type diffusion layer 104 near the gate oxide film 106 is inverted. Transmitted. On the other hand, since the buried contact 108 is connected to the capacitor electrode 107, the capacitor electrode 107 and the capacitor insulating film 109 are connected.
A charge is stored and stored in a MIS (Metal Insulator Semicondoctor) type capacitor formed between the P ⁺ type diffusion layer 105 and the P ⁺ type diffusion layer 105 facing each other.

According to the conventional semiconductor memory device having such a configuration, not only the capacitor but also the transfer gate region is buried inside the trench groove 103, so that the degree of integration can be considerably improved in the plane direction of the semiconductor memory device. However, there is a limit in improving the degree of integration, that is, miniaturizing the device. The limit of miniaturization will be described with reference to FIG.

As shown in FIG. 6, if the minimum size determined by the photolithography process and the like is F, and the alignment margin between different photolithography processes is 0.2F, the smallest semiconductor memory device that can be manufactured is manufactured. The length of one side of the trench groove is F, which is the minimum dimension described above, and the line widths of the word line and the bit line are respectively.
Since 1.4F and the interval between each word line and each bit line are 1.0F, the length of one side of the cell region is 0.5F + 0.2F + 1.0F + 0.2F + 0.5F = 2.4F. Therefore, the minimum area of a cell for 1 bit is 2.4F × 2.4F = 5.76F ² .

If the area of the cell for 1 bit is further reduced, the photo-etching technology will be greatly improved and improved, the resolution,
And there is no other way than to improve the alignment accuracy.

(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and a semiconductor memory device capable of realizing a higher degree of integration without relying on a significant improvement in the photoetching technique and It is an object to provide a manufacturing method thereof.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device according to the present invention has a base body having a convex wall having an insulator on the surface, and one side surface, an upper surface,
And a semiconductor layer formed on the other side surface facing the one side surface. Further, of this semiconductor layer, it will be one electrode of a capacitor provided in the semiconductor layer facing a part of one side surface of the wall and in the semiconductor layer facing a part of the other side surface of the wall, respectively. First and second regions of the first conductivity type;
A third region of the first conductivity type, which is provided in the semiconductor layer facing the upper surface of the wall and serves as a terminal for connecting to the bit line;
In the semiconductor layer between the first region and the third region and the second region
Insulating layers on the surfaces of the fourth and fifth regions of the second conductivity type and the first and second regions, respectively, which are provided in the semiconductor layer between the region and the third region. And the other electrode of the capacitor provided via the first and second gate electrodes, which are provided on the surfaces of the fourth and fifth regions via the insulating layer and are coupled to different word lines, respectively. When,
And a cell structure including. And, the wall has a lengthwise direction when viewed from a plane, and a plurality of walls are provided,
Each of the plurality of walls is characterized in that a plurality of cell structures having the above-mentioned structure are arranged along the lengthwise direction of the walls so as to be separated from each other.

(Operation) The semiconductor memory device having the above-described configuration has a so-called "U" -shaped semiconductor layer that is fitted to a convex wall having an insulator on its surface. A plurality of the semiconductor layers are arranged apart from each other along the longitudinal direction of the wall. A cell is formed in each of these semiconductor layers, and two cells using the third region as a common region are obtained. Therefore, a cell having a current path along the side surface of the wall can be obtained for each side surface of the wall, and more cells can be integrated in a small plane area. For example, the integration is doubled by having cells on each side of the wall, compared to known cross-point cells, which have one cell in one trench. That is, in the semiconductor memory device having the above configuration, a 2-bit cell can be obtained within the 1-bit cell area required by the crosspoint cell.

Therefore, without resorting to a significant improvement in photo-etching technology,
It is possible to obtain a semiconductor memory device that can realize a higher degree of integration.

(Embodiment) A semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to FIGS.

1A to 1F are cross-sectional views showing a method of manufacturing a DRAM cell according to an embodiment of the present invention in the order of steps.

In FIG. 1A, the first single crystal silicon layer 2 is grown on the insulator layer 1 by using, for example, a vapor phase growth method.
Next, a photoresist 3 is deposited on the entire surface and patterned into a predetermined shape, and the insulator layer 1 and the single crystal silicon layer 2 are etched by using the photoresist 3 having the predetermined shape as a mask to form a wall 4 of the insulator layer. To do. At this time, the distance between the walls 4 is approximately equal to the thickness of the wall 4.

In FIG. 1 (b), after removing the photoresist 3,
A second silicon layer 'is formed on the entire surface by, for example, vapor phase epitaxy.
Grow. At this time, the single crystal silicon 2'is grown by using the first single crystal silicon 2 as a seed crystal. Next, for example, B (boron), which is a P-type impurity, is ion-implanted into the silicon layer 2'and thermally diffused to form the second single crystal silicon layer 2 '.
To P-type. Next, RIE (Reactive Ion Etchin
Using the method g), the P-type single crystal silicon layer 2'is etched so that it remains only on the upper surface and the side surface of the wall 4 of the insulator layer.

In FIG. 1 (c), a silicon oxide layer 5 is formed between the silicon layers 2'formed in the grooves between the walls 4 of the respective insulator layers by, for example, a CVD (Chemical Vapor Deposition) method. Is deposited and etched up to, for example, a capacitor formation region up to half the depth of the groove. Subsequently, for example, As (arsenic) which is an N-type impurity is ion-implanted into the silicon oxide layer 5, and the entire surface is covered with a protective film 6 made of an oxide film,
After that, when heat treatment for activating the impurity ions is performed, the silicon oxide layer 5 is removed from the single crystal silicon layer 2 '.
N-type impurities are thermally diffused into the single-crystal silicon layer 2 ′, and the single-crystal silicon layer 2 ′ is doped with N-type only near the silicon oxide film 5.
N type diffusion layer 7 is formed.

In FIG. 1 (d), the silicon oxide film 5 and the protective film 6 are removed to remove the P-type single crystal silicon layer 2'and the first
The N-type diffusion layer 7 is exposed, and then the first thermal oxide film 8 is formed on the entire surface. This first thermal oxide film 8 will become a capacitor insulating film in a later step. Then, in the groove between each insulating layer wall 4 a first polysilicon layer 9 is deposited, for example CVD.
Method is used to deposit and etching is performed up to the capacitor formation region to form the capacitor electrode 9.

Next, in FIG. 1E, the first thermal oxide film 8 above the capacitor electrode 9 is removed. The first thermal oxide film 8 remaining in this step becomes the capacitor insulating film 8. Next, the second thermal oxide film 10 is formed on the entire surface by thermal oxidation. At this time, since the oxidation rate of polysilicon is high,
A thermal oxide film 10 thicker than the others is formed on the capacitor electrode 9 made of this. This second thermal oxide film 10 will become a gate insulating film in a later step. Then, in the groove between the walls 4 of each insulator layer, a second polysilicon layer 11 is formed, for example CV.
It is deposited by the D method, and etching is performed up to the transistor formation region partitioned by the thermal oxide film 10. This second polysilicon layer 11 will become a gate electrode in a later step. Next, for example, N-type impurity As (arsenic) is ion-implanted into the P-type silicon semiconductor layer 2 ′ on the upper wall 4 of the insulating layer through the second thermal oxide film 10 to thermally diffuse the P-type silicon semiconductor. A second N-type diffusion layer 7'having a conductivity type opposite to that of the layer 2'is formed. This time,
The P-type silicon semiconductor layer 2 ′ which is protected by the second polysilicon layer 11 and is not N-type doped is a P-type diffusion layer.
Remains as 13. In this way, on the side surface of the groove formed in the insulating layer 1, that is, on the side surface of the wall 4 of the insulating layer, an element region is formed by the N type diffusion layers 7, 7'and the P type diffusion layer 13. . Next, the second polysilicon layer 11 is formed by using the RIE method.
Is etched into a predetermined shape to form the gate electrode 11.

Finally, in FIG. 1 (f), a silicon oxide film 14 is deposited by using the CVD method. Next, the second N-type diffusion layer 7 '
The silicon oxide film 14 and the second thermal oxide film 10 are removed so that the oxide film is exposed. After that, Al (aluminum) is deposited on the entire surface by, for example, a sputtering method and patterned into a predetermined shape to form the bit line 15, whereby the semiconductor memory device according to the embodiment of the present invention is manufactured.

According to the semiconductor memory device having such a cell structure, the single crystal silicon layer 2'is provided on the side surface of the groove formed in the insulator layer 1, that is, the side surface of the wall 4 of the insulator layer. The layer 2'is laterally divided to form the N-type diffusion layers 7 and 7'and the P-type diffusion layer 13 so that the device region of the cell is formed on the side surface of the groove, that is, the side surface of the wall 4 of the insulating layer. To form. Therefore, it is possible to form a 2-bit cell in the smallest area of a conventional 1-bit cell, and always double the highest technology of that era without relying on the drastic improvement of photo-etching technology. It is possible to manufacture a semiconductor memory device having a degree of integration higher than that of the highest technology, that is, a degree of integration comparable to the next generation.

Next, the semiconductor memory device manufactured according to the above embodiment will be described with reference to FIGS. 2 (a) and 2 (b).

FIG. 2A is a plan view of a semiconductor memory device manufactured by the method of manufacturing a semiconductor memory device according to the above embodiment.

In FIG. 2A, a word line 11 as a gate electrode is formed around a wall 4 of an insulating layer via a gate insulating film 10, and a gate electrode around the wall 4 of an adjacent insulating layer is formed. Is insulated from the word line 11 by the insulating layer 14. A bit line 15 is formed on the upper part of these, and in the region where the bit line 15 and the word line 11 as a gate electrode formed on both sides of the wall 4 of the insulating layer intersect, the wall 4 of the insulating layer 4 is formed. An N-type diffusion layer 7'is formed on the upper surface of each of the P-type diffusion layer 7'and the N-type diffusion layer 7 (not shown in the plan view).
Are formed.

Further, FIG. 2 (b) is a sectional view taken along the line AA shown in FIG. 2 (b).
FIG. 3B is a cross-sectional view taken along with, and is the same cross-sectional view as FIG.

Next, a first modification of the embodiment of the present invention will be described with reference to FIG.

In the above embodiment, the insulator layer 1 was etched to form the insulator layer wall 4. However, as shown in FIG. 3, the insulator layer was formed on the silicon semiconductor substrate 16, and the insulator layer 1 was formed. Wall 4
May be formed.

With this structure, the second semiconductor layer 2'can be grown as a single crystal by using the silicon semiconductor substrate 16 as a seed crystal.

Next, a second modification of the embodiment of the present invention will be described with reference to FIGS. 4 (a) and 4 (b).

In the second modified example, an insulator layer is formed on the silicon semiconductor substrate 16 similar to the first modified example, and this is patterned to form the wall 4 of the insulator layer.
As shown in FIG. 4 (a), when the insulator layer is etched, the insulator layer is left in the groove between the walls 4 of the insulator layer at the portion in contact with the silicon semiconductor substrate 16. And the silicon semiconductor substrate 16 is exposed so that the exposed portion 17 is formed. afterwards,
A silicon layer 2'is formed. With such a structure, the second silicon layer 2'can be grown as a single crystal by using the exposed portion 17 of the silicon semiconductor substrate in the groove as a seed crystal.

Next, in FIG. 4 (b), this silicon layer 2'is etched so as to remain on the upper surface and the side surface of the wall 4 of the insulator layer.

According to this structure, since the insulator layer 4'is interposed between the silicon semiconductor substrate 16 and the silicon layer 2 ', the leak between adjacent cells is reduced.

Although the semiconductor layer forming the element region is grown from single crystal silicon in the above-described embodiments and modifications, it is needless to say that polycrystalline silicon may be used.

As described above, according to the semiconductor memory device described in the embodiment,
By forming the wall of the insulator layer and forming the element region on the side surface and the upper surface of this wall, the minimum area of the cell for 1 bit is 5.76F ^{2 where} F is the minimum dimension of the photo-etching technology in that era. It is possible to form a cell for 2 bits in the area of 2 times, and always have twice the degree of integration as that of a semiconductor memory device having a conventional cell structure manufactured by using the best photo-etching technique in that era. A semiconductor memory device having a cell structure and a method for manufacturing the same can be provided.

Further, in the method of manufacturing the semiconductor memory device having such a cell structure, the word line as the capacitor electrode and the gate electrode can be formed in a self-aligned manner.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of realizing a higher degree of integration and a method of manufacturing the same, without relying on a great improvement in the photo-etching technique.

[Brief description of drawings]

1 (a) to 1 (f) are sectional views showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention in the order of manufacturing steps, FIGS. 2 (a) and 2 (b). FIG. 1 is a plan view and a cross-sectional view of the semiconductor memory device showing the manufacturing process in FIG. 1, FIG. 3 is a cross-sectional view showing a first modification of the embodiment of the present invention, and FIGS. 4B is a sectional view showing a second modification of the embodiment of the present invention, and FIGS. 5A to 5B are a plan view and a sectional view of a semiconductor memory device according to the prior art, and FIG. FIG. 1 is a plan view for explaining the minimum area of a 1-bit cell according to the related art. 1 ... Insulator layer, 2 and 2 '... Single crystal silicon layer, 3 ...
... Photoresist, 4 ... Insulator layer wall, 4 '... Region for insulating semiconductor layer from substrate, 5 ... Silicon oxide film, 6
...... Protective film, 7 ... N-type diffusion layer, 8 ... Thermal oxide film, 9 ...
… Capacitor electrode, 10… Thermal oxide film, 11… Gate electrode, 13… P-type diffusion layer, 14… Insulator layer, 15… Bit line, 16… Silicon semiconductor substrate, 17… Silicon semiconductor Exposed part of substrate 16, 100 ... Silicon semiconductor substrate, 1
01 …… bit line, 102 …… word line, 103 …… trench groove, 104 …… P type diffusion layer, 105 …… P ⁺ type diffusion layer, 106 ……
Gate insulating film, 107 ... Capacitor electrode, 108 ... Buried contact, 109 ... Capacitor insulating film.

Claims (2)

[Claims] 1. A substrate having a convex wall having an insulator on a surface thereof, a semiconductor layer formed on one side surface of the wall, an upper surface of the wall and another side surface facing the one side surface, A first conductive type first electrode which is provided in the semiconductor layer facing a part of the side surface and in the semiconductor layer facing a part of the other side surface and serves as one electrode of a capacitor;
A second region; a third region of the first conductivity type, which is provided in the semiconductor layer facing the upper surface and serves as a terminal for connecting to a bit line; the first region and the third region; A second conductivity type fourth provided in the semiconductor layer between the second region and the third region, and in the semiconductor layer between the second region and the third region.
A fifth region, the other electrode of the capacitor provided on the surfaces of the first and second regions via an insulating layer, and an insulating layer on the surfaces of the fourth and fifth regions, respectively. A cell structure including first and second gate electrodes coupled to different word lines, which are provided through the wall, and the wall has a longitudinal direction when viewed from a plane, and a plurality of cells are provided. In each of the plurality of walls, a plurality of the cell structures are arranged along the longitudinal direction of the walls so as to be separated from each other. 2. A step of forming, on a base, a plurality of convex walls having an insulator on the surface and having a lengthwise direction when viewed from a plane, one side surface of the wall, an upper surface of the wall and the one side surface. A step of forming a semiconductor layer on the other side surface facing to, a step of determining the conductivity type of the semiconductor layer as a first conductivity type, the semiconductor layer is etched, and along the longitudinal direction of the wall, One step of separating the semiconductor layers into a plurality of electrodes, and one electrode of the capacitor in each of the semiconductor layers facing a part of the one side surface and in each of the semiconductor layers facing a part of the other side surface. Forming first and second regions of a second conductivity type respectively; forming another electrode of the capacitor on the surface of the first and second regions via an insulating layer, respectively; On each of the semiconductor layers facing the other part of the one side surface, and on the other side surface Wherein each of the facing parts on the surface of the semiconductor layer through an insulating layer, first as a different word line from each other,
Forming a second gate electrode, and forming a third region of the second conductivity type, which is a terminal for connecting to a bit line, in each of the semiconductor layers facing the upper surface, and the remaining portion In the semiconductor layer between the first region and the third region and in the semiconductor layer between the second region and the third region, respectively, a fourth conductivity type fourth and a fourth conductivity type 5. A method for manufacturing a semiconductor memory device, comprising: