JPH07107116A - Packet switching system - Google Patents

Abstract

PURPOSE:To provide a high performance packet switching system which can conduct independently low speed scheduling in each input port by mounting a low speed buffer of a large capacity, and also, mounting a high speed shared buffer of a small quantity. CONSTITUTION:This packet switching system is constituted so that input buffers 101-1 to 101-N installed in accordance with N pieces of input ports and a shared buffer 104 installed in accordance with N pieces of output ports are provided and this shared buffer 104 can receive simultaneously N pieces of packets from the input buffers 101-1 to 101-N, and a shared buffer control part 105 for controlling the shared buffer 104 multi-addresses a packet store state of the shared buffer 104 to input buffer control parts 102-1 to 102-N, and each input buffer control part 102-1 to 102-N controls so as to output the packet from the input buffers 101-1 to 101-N if a free space of the shared buffer 104 is an N-packet portion or above.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switching system, and more particularly to a packet switching system which handles multimedia and obtains high performance.

[0002]

2. Description of the Related Art Conventional packet switching methods are classified into a shared buffer type (H. Kuwahara
et. al .: "A Shared Buffer Memory Switch for an ATM
Exchange ", Proc.ICC'89, pp.122-125 (1984)), Output buffer type (H.Suzuki, et.al.:"Output-Buffer Switch Arch
itecture for Asynchronous Mode, "Int.J.Digital andA
nalog Cabled Systems, Vol.2, pp.269-276 (1989)), cross point buffer type (Y. Kato et. al .: "A Developme
nt of a High Speed ATM Switching LSIC ", ICC'90, pp.3
10.3.1-310.3.5 (1990)), input buffer type (M.Akata et.
al.:"A Scheduling Content-Addressable Memory for
ATM Space-Division Switch Control ", ISSCC'91, pp.244
-245 (1991)) and input / output buffer type exchange method (Yukih
iro Doi et. al .: "A Very High-Speed ATM Switch with
Input and Output Buffers ", ISS'92, pp.231-235 (199
2))

In the shared buffer type exchange system, the sharing effect of the buffer is large and the total required buffer capacity is the smallest compared to other systems, but the access speed to the buffer is high (input port speed x number of input ports). X2), and it is difficult to mount a large capacity high speed buffer.

In the output buffer type exchange system, it is easy to handle traffic such as multicast, and the access speed to the output buffer is about half that of the shared buffer, but there is no sharing effect of the buffer and the required buffer is available. Since the capacity is several times more than that of the shared buffer type method, it is difficult to implement such a high speed large capacity buffer.

In the cross-point buffer type exchange system, the access speed to the buffer is small (input port speed × 2), but the buffer corresponding to one output port is divided into N (N is the number of input ports). Therefore, the required capacity of the buffer becomes enormous due to the characteristics such as uneven traffic.

In the input buffer type switching system, the access speed to the buffer is the same as that in the cross point buffer type switching system, but it is necessary to perform complicated scheduling between input ports at high speed in order to obtain high throughput. There is.

In the input / output buffer type exchange system, the access speed to the buffer is several times that of the input buffer type exchange system, and it is necessary to perform scheduling between input ports. In particular, scheduling becomes complicated for traffic such as multicast, and the capacity of the output buffer on the output side is as large as that of the output buffer type exchange system.

[0008]

The conventional packet switching systems described above can be implemented by the present technology because the required buffer capacity is small for random traffic. However, for traffic with a strong burst characteristic, a large-capacity and high-speed buffer is indispensable to obtain high throughput, and there is a problem that it is difficult to implement with the current technology.

Further, in the input buffer system using the low speed buffer, there is a problem that complicated scheduling between input ports is required.

An object of the present invention is to improve the disadvantage that it is difficult to mount a large-capacity high-speed buffer of the conventional system as a switching system for handling multimedia, especially traffic having a strong burst property, and mount a large-capacity low-speed buffer. By providing a small amount of shared buffers, it is possible to provide a high-performance packet switching system for independently performing low-speed scheduling at each input port.

[0011]

A packet switching system according to a first aspect of the present invention has an input buffer installed corresponding to a plurality of input ports and a shared buffer installed corresponding to a plurality of output ports. However, the shared buffer is N at the same time.
In the packet switching system capable of receiving (N is the number of input ports) packets from the plurality of input buffers, the input buffers provided to the packets input from the plurality of input ports corresponding to the plurality of input ports. When the packet is output from the input buffer, if the free space of the shared buffer is N packets or more, it is determined that the packet can be output from the input buffer, and one of the plurality of output packets can be selected. When the selected packet is input to the shared buffer and the packet is output from the shared buffer, one is selected from a plurality of packets that can be output to the corresponding output port based on the output port information of the packet, and this selected packet is selected. Output packets from the shared buffer to the corresponding output port. It is characterized in that.

In the packet switching system of the second invention, in the packet switching system of the first invention, if the free space of the shared buffer is N packets or more, a multicast communication packet can be output from a plurality of input buffers. If the free space of the shared buffer is p (N <p) packets or more, one-to-one communication packet can be output from the plurality of input buffers.

According to a third aspect of the packet switching system of the present invention, in the first or second packet switching system, the packets of the priority class traffic are preferentially input to the shared buffer from a plurality of input buffers, and the packets are transferred from the shared buffer. When outputting, the packet of the priority class traffic is output preferentially.

The packet switching system of the fourth invention is the packet switching system of the third invention, wherein the maximum capacity of the shared buffer that can be occupied by the non-priority class traffic packet is M, and the non-priority class traffic packet is occupied. It is characterized in that the packet of the non-priority class traffic cannot be output from a plurality of input buffers when the amount of the shared buffer is larger than (MN).

The packet switching system of the fifth invention is the packet switching system of the fourth invention, wherein the amount of the shared buffer occupied by the packets of the non-priority class traffic is (M-
N) or less, i (i = 1) in the shared buffer
~ N) The number of stored packets going to the Nth output port is m
If ((M−N)> m ≧ 0) or less, j (j = 1 to 1)
When the stored number of packets going to the N, j ≠ i) th output port is larger than m, the packet going to the i-th output port is preferentially sent from the input buffer to the packet going to the j-th output port. It is characterized by outputting.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

In the embodiment, it is assumed that both priority class traffic, which is processed in preference to other traffic in the exchange processing, and non-priority class traffic, which is not processed, are handled.
Priority class traffic is constant bit rate traffic such as voice and video.
c, hereinafter abbreviated as CBR), and variable bit rate traffic (hereinafter referred to as VBR) such as data as non-priority class traffic.

Further, in this embodiment, the VBR includes a variable bit rate multicast traffic (Variable bit rate mult) which is a normal one-to-one communication VBR and a broadcast communication.
icast traffic, hereinafter abbreviated as VBRM) will be described below.

FIG. 1 is a block diagram showing an embodiment of the packet switching system of the present invention.

As shown in FIG. 1, the packet switching system of this embodiment is an N × N packet switching system composed of N input ports and N output ports. Random-in random-out input buffers 101-1 to 101-N for accumulating input packets arriving from -1 to 100-N, and the input buffers 101-1 to 101-N based on packet selection information described later. Input buffer control unit 102 for controlling by
-1 to 102-N and packets arriving from each input buffer are time-division-multiplexed on the input highway and stored in the random-in-random-out memory, and the output highway multiplexing information output from the memory is output to N pieces. Port 110-
A shared buffer 104 that separates and sends 1 to 110-N;
The input buffer 101 is controlled based on the packet storage information of the shared buffer 104 while controlling the shared buffer 104.
-1 to 101-N creates packet selection information for selecting a packet to be output, and each input buffer control unit 102-
1 to 102-N and a shared buffer control unit 105 that broadcasts to each of the units.

Since the time division multiplexing and demultiplexing in the shared buffer 104 is a known technique, a description of this technique will be omitted hereinafter, and the shared buffer 104 responds to the high speed writing of the incoming N packets and the request of the output port. The memory will be described as a random-in random-out memory capable of high-speed reading of N packets, and the shared buffer control unit 105 will be described as the one for performing the control.

FIG. 2 shows N input buffer control units 102-
Input buffer controller 1 as a typical example of 1 to 102-N
It is a block diagram which shows an example of 02-1.

The input buffer control unit 102-1 of FIG. 2 has an idle address management queue 206, which is a first-in first-out memory that manages and stores the idle address of the input buffer 101-1 (the address of the buffer that does not store packets). A CBR address management queue 2 which is a first-in first-out memory that manages and stores the address (of the input buffer 101-1) in which the CBR-related packet is stored.
02 and a VBRM address management queue 2 which is a first-in first-out memory that manages and stores the address (of the input buffer 101-1) in which the VBRM-related packet is stored.
03, and a VBR that is a first-in first-out memory that manages and stores the address (of the input buffer 101-1) at which the VBR-related packet for one-to-one communication output to the output port i (i = 1 to N) is stored. The output i address management queue 204-i and the idle address supplied from the idle address management queue 206 according to the arrival of the input packet are supplied as write addresses to the input buffer 101-1 via the line 103-1-2. This input packet is stored in the input buffer 101-1 and the packet characteristics (CBR, VBRM, VBRM) of this input packet are stored.
Input buffer 101-1 in which the packet is stored based on R) and output port information (output port number)
Is distributed to the corresponding address management queue (if the input packet is a packet output to the output port 1 by the VBR of 1: 1 communication, the address storing it is supplied to the VBR output 1 address management queue 204-1) The distribution unit 201 and the reference numerals 202, 20 based on the packet selection information broadcast from the shared buffer 104.
3 and 204-1 to 204-N, the address of the packet to be output is selected from the address management queue and is supplied as a read address to the input buffer 101-1 via the line 103-1-3 to output the packet. In addition, the selection unit 205 supplies the read address that has become an empty address to the idle address management queue 206.

FIG. 3 is a block diagram showing an example of the shared buffer control unit 105.

The shared buffer control unit 105 in FIG. 3 outputs the idle address of the shared buffer 104 to the idle address management queue 303 which is a first-in first-out memory for management storage, and the output port i (i = 1 to N). Address where packet is stored (shared buffer 104
Output i-address management queue 302, which is a first-in first-out memory that separately stores and stores CBR and VBR
-I and the idle address supplied from the idle address management queue 303 in response to the arrival of the input packet are supplied as write addresses to the shared buffer 104 via the line 106-2 and the input packet is transmitted to the shared buffer 1
No. 04, and the distribution unit 301 that distributes the address of the shared buffer 104 storing the packet to the corresponding output address management queue based on the packet characteristics of the input packet and the output port information, and based on the priority order. The address of the packet to be output is selected from the output address management queues of reference numerals 302-1 to 302-N and is supplied as a read address to the shared buffer 104 via the line 106-3 to output the packet and also to an empty address. The selection unit 304 that supplies the read address that has become unusable to the idle address management queue 303, and the packet that creates the selection information that indicates the selection instruction of the packet that will be supplied to the shared buffer 104 next based on the packet storage information of the shared buffer 104. Selection information creation unit 30
And 8 are included.

This selection information, that is, the selection instruction, minimizes the capacity of the shared buffer that requires high-speed access, supplements it with the amount of input buffer that enables low-speed access and large capacity, and also between input ports. The high-speed scheduling is eliminated, and the input ports are set to perform low-speed scheduling independently of each other, and the multicast is set so that it can easily handle heavy bursty traffic.

For that purpose, first, the output to the shared buffer 104 is to give priority to the CBR which is the priority class traffic, and in order to ensure this priority control,
The maximum occupancy of the shared buffer 104 of the non-priority class traffic VBR is M (VBRM occupancy and V for one-to-one communication).
The BR occupancy is the maximum of the added amount). Here, the priority means that both the CBR and the VBR are input to the shared buffer 104 when the amount of the VBR including the VBRM occupying the shared buffer 104 is equal to or less than a certain value (a value different from M as described later). Is accepted, but the V containing the VBRM divinated on the shared buffer 104
When the amount of BR exceeds a certain value, the input to the shared buffer 104 of VBR is rejected, but even in that case, the input to the shared buffer 104 of CBR is accepted.

In consideration of the residence time of the VBRM in the shared buffer 104, the amount of the shared buffer 104 that the VBRM can occupy is controlled so that k packets can be stored more than the VBR of the one-to-one communication.

Further, V output to a specific output port
In order that only the BR packet does not occupy the shared buffer 104, one threshold value m is set for each occupied amount of the VBR packet including the VBRM that goes to each output port in the shared buffer 104. The VBR packet for one-to-one communication output to the port is controlled to be output to the shared buffer 104 with priority over the VBR packet for one-to-one communication output to the output port exceeding m. V including the VBRM output to each output port
1 to 1 output to each output port when the BR packet occupancy in the shared buffer 104 exceeds m.
The VBR packets for communication are controlled so that they are treated equally.

Next, the packet selection criteria in the packet selection information creating section 308 will be described.

The first priority is the CBR packet. Therefore, if the free space of the shared buffer 104 is X,
If the vacant space X is the number of ports N or more (X ≧ N),
The shared buffer 104 allows the CBR packet to be accepted,
If the number of ports is less than N (X <N), it is not accepted, and C
Keep BR packets in the input buffer.

By doing so, the shared buffer 104 is always available when the free space X is greater than or equal to the number N of ports.
It becomes possible to simultaneously input N CBR packets to the input port, the high-speed scheduling between the input ports is eliminated, and the scheduling can be independently performed at the input ports.

The second priority is VBRM packets. Therefore, when the occupancy of the sum of the VBRM packet currently occupying the shared buffer 104 and the VBR packet of the one-to-one communication is Y, the empty space X is the number N of ports or more (X ≧ N), If the free space (MY) left in the non-priority class traffic VBR is equal to or larger than the number of ports N (MY ≧ N), the shared buffer 104 can accept the VBRM packet, and otherwise it cannot accept it. , And retain the VBRM packet in the input buffer.

By doing so, if the empty space X is the number of ports N or more and the empty space (MY) left in the non-priority class traffic VBR is the number of ports N or more, the shared buffer is always available. N Vs to 104
BRM packets can be input at the same time, high-speed scheduling between input ports is eliminated, and scheduling can be performed independently at each input port.

Since the maximum occupancy of the VBR packet for one-to-one communication is smaller than that of the VBRM packet by k packets, the total occupancy of the VBRM packet currently occupying the shared buffer 104 and the VBR packet for one-to-one communication is calculated. When Y is set, the empty space X is equal to or larger than the number N of ports (X ≧
N), and if the empty space (MYK) left in the VBR packet including the VBRM is greater than or equal to the number of ports N (MYK≥N), the shared buffer 104 is a VBR for one-to-one communication. The packet can be accepted, and otherwise the VBR packet for one-to-one communication is retained in the input buffer.

By doing so, the empty space X is greater than or equal to the number of ports N (X ≧ N), and the empty space left in the VBR packet including VBRM (MY−Y−
If k) is greater than or equal to the number of ports N (MY−k ≧ N), it is always possible to simultaneously input N VBR packets for one-to-one communication to the shared buffer 104, and high-speed scheduling between input ports is not possible. Now, scheduling can be done independently for each input port.

Further, regarding the VBR packet for one-to-one communication, the shared buffer 104 for the VBR packet including the VBRM output to the output port i even in the acceptable state.
The current occupancy (m (i)) in the fixed value m (0 ≦ m <
(M-Y-k)) In the following cases, the VBR packet output to the output port that exceeds the fixed value m is given priority for output, and if not, it is not given priority.

As a result, only the VBR packet for one-to-one communication output to the specific output port is shared by the shared buffer 10.
4 can be controlled not to occupy.

When there are a plurality of acceptable packets and when there are a plurality of packets to be prioritized, they are processed in a predetermined order.

CBR, VBRM and VB for one-to-one communication
A state variable indicating whether the R packet can be accepted by the shared buffer 104 (having a value of 1 when the packet is acceptable and 0 when it is unacceptable) is BP _C , BP _VM , and BP _V , respectively.
And a state variable (having a value of 1 when giving priority and 0 when not giving priority) indicating whether or not to preferentially output the VBR packet of the one-to-one communication output to the output port i is set to FP.
A flow chart for determining these state variables when (i) is shown in FIG.

Since the above control effectively uses the high-speed and small-capacity shared buffer, when there is a lot of free space in the shared buffer, any traffic is accepted, but when the free space in the shared buffer is gradually decreasing. , VBR input for 1: 1 communication is restricted first, then V
The BRM is controlled so as to limit the input of the CBR at the end. However, when input is possible, it is controlled so that N packets can be simultaneously input.

When creating the packet selection information, the packet selection information creation unit 308 obtains the empty space X of the shared buffer 104 from the number of idle addresses of the shared buffer 104, and the difference between the input and output of the CBR shared buffer 104. From this, the number of CBR packets stored in the shared buffer 104 is calculated, and conversely, the amount Y of VBR packets including VBRM stored in the shared buffer 104 is known, and m (i) is the common buffer control unit 105.
Of the output i address management queue 302-i from the number of addresses in the VBR address management queue, and according to the flowchart of FIG.
P _C , BP _VM , BP _V and FP (1) to FP (N) are obtained and broadcast to the input buffer control units 102-1 to 102-N.

Next, the operation of this embodiment will be described with reference to FIGS.

The packet input from the input port 100-1 is the input buffer 101 indicated by the idle address supplied from the idle address management queue 206 of the input buffer control unit 102-1 via the distribution unit 201.
At the same time as being stored in the corresponding location of −1, the distribution unit 201 refers to the storage address of the packet based on the characteristics of the input packet and the output port information thereof, by reference numeral 202,
203 and 204-1 to 204-N are stored in the corresponding address management queues.

Selection unit 2 of input buffer control unit 102-1
05 determines which packet should be output in the next time slot based on the packet selection information broadcast from the packet selection information creation unit 308 of the shared buffer control unit 105. That is, the selecting unit 205 compares the characteristics of the packet pointed to by the address at the head of each address management queue and its output port information with the packet selection information that has been broadcast, and determines the address of the packet that can be output. One of them is selected and read out in a predetermined order, and in the next time slot, a packet is output from the position of the input buffer 101-1 pointed to by the selected address to the shared buffer 104 and this address is output. It is stored in the idle address management queue 206 as an idle address.

The shared buffer 104 has N packets per packet time.
Since the number of packets can be received at the same time and the available space is N or more, the packet read operation at each input port can be performed independently of the operation at other input ports.

In the embodiment, the priority order of outputting the packets is such that the CBR packet has the highest priority, followed by the VBRM packet and the VBR packet which goes to the output port having a small occupation amount in the shared buffer 104.

The packet output from the input buffer 101-1 is stored in the shared buffer 104 corresponding to the idle address supplied from the idle address management queue 303 of the shared buffer control unit 105 via the distribution unit 301. At the same time, the distribution unit 301 determines the storage address of the packet based on the characteristics of the input packet and the output port information thereof with reference numerals 302-1 to 302-3.
Store in the corresponding output address management queue in 02-N.

When a packet is output from the shared buffer 104, the selection unit 304 preferentially selects an address in the CBR address management queue and outputs the packet from the location of the shared buffer 104 pointed to by the selected address. The address is output to the port and stored in the idle address management queue 303 as an idle address.

As described above, in the N × N packet switching system of this embodiment, when the free space in the shared buffer is less than N packets, the output from the input buffer to the shared buffer is suppressed. By controlling, high-speed scheduling between input ports can be eliminated and independent low-speed scheduling can be performed on each input port. Also, a shared buffer that requires high-speed access can have a small capacity and a large capacity is required. By using an input buffer that can be accessed at low speed, it can be easily realized as compared with the conventional method, and high throughput can be obtained even for traffic having strong burstiness.

In the present embodiment, the VBR packet for one-to-one communication is not classified into specific classes according to the use or the like, but a specific measure is provided for this VBR packet. A variety of service qualities can be satisfied by providing an address management queue for each class in the control unit and setting an empty state of the shared buffer corresponding to each class.

[0052]

As described above, in the packet switching system of the present invention, when the free space in the shared buffer is less than N packets, the output from the input buffer to the shared buffer is controlled to be suppressed. This eliminates high-speed scheduling between input ports,
Independent low-speed scheduling can be performed at each input port, and the shared buffer that requires high-speed access can have a small capacity, while the large capacity requires a low-speed access to provide a good input buffer. This has the effects that the feasibility can be significantly improved compared to the system and that high throughput can be obtained even for traffic that is strong in burstiness.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a packet switching system of the present invention.

FIG. 2 is a block diagram of an input buffer control unit.

FIG. 3 is a block diagram of a shared buffer control unit.

FIG. 4 is a flowchart showing a process of creating packet selection information.

[Explanation of symbols]

100-1 to 100-N input port 101-1 to 101-N input buffer 102-1 to 102-N input buffer control unit 104 shared buffer 105 shared buffer control unit 110-1 to 110-N output port 201, 301 distribution Part 202 CBR address management queue 203 VBRM address management queue 204-i (i = 1 to N) VBR output i address management queue 205, 304 selection part 206, 303 idle address management queue 302-i (i = 1 to N) output i-address management queue 308 Packet selection information creation unit

Claims (5)

[Claims] 1. An input buffer installed corresponding to a plurality of input ports and a shared buffer installed corresponding to a plurality of output ports, the shared buffer being N at the same time (N is the number of input ports). In the packet switching system capable of receiving a number of packets from the plurality of input buffers, the packets input from the plurality of input ports are input to the input buffers installed corresponding to the plurality of input ports, and the input buffers are input. When a packet is output from the input buffer, if the empty space of the shared buffer is equal to or more than N packets, it is possible to output the packet from the input buffer, and one of the plurality of outputtable packets is selected and the selected packet is output. When the packet is input to the shared buffer and the packet is output from the shared buffer, the packet output port is A packet switching system characterized by selecting one from a plurality of packets that can be output to the corresponding output port based on the packet information and outputting the selected packet from the shared buffer to the corresponding output port. 2. The shared buffer according to claim 1, wherein if the empty space of the shared buffer is N packets or more, a multicast communication packet can be output from a plurality of input buffers, and the empty space of the shared buffer is p (N <p) packets. A packet switching system characterized in that one-to-one communication packets can be output from the plurality of input buffers if the number of minutes or more. 3. The packet of priority class traffic according to claim 1 or 2, when packets of priority class traffic are input from a plurality of input buffers to the shared buffer with priority, and when packets are output from the shared buffer. A packet switching method characterized by being output preferentially. 4. The maximum capacity of a shared buffer that a packet of non-priority class traffic can occupy is M, and the amount of the shared buffer occupied by the packet of non-priority class traffic is larger than (M−N). The packet switching system is characterized in that the packet of the non-priority class traffic cannot be output from a plurality of input buffers. 5. The amount of shared buffer occupied by a packet of non-priority class traffic according to claim 4,
N) or less, i (i = 1) in the shared buffer
~ N) The number of stored packets going to the Nth output port is m
If ((M−N)> m ≧ 0) or less, j (j = 1 to 1)
When the stored number of packets going to the N, j ≠ i) th output port is larger than m, the packet going to the i-th output port is preferentially sent from the input buffer to the packet going to the j-th output port. A packet switching method characterized by outputting.