JPH07106509A - Multilayer structure semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to fully respond to finer intervals of semiconductor element wiring and to form an electrically conductive path in a high-density array shape by realizing three-dimensional high-density mounting of diversified semiconductor elements by laminating thin type semiconductor devices housing semiconductor elements in recessed portions and also by multi-layer conductor circuits by inserting conductor circuits to the electrically conductive paths. CONSTITUTION:This is a multilayer structure semiconductor device T laminated on an external substrate 1 with two or more semiconductor devices H mounting a semiconductor element S in a recessed portion 5 placed on an insulation substrate 3, and semiconductor elements of each semiconductor device and terminals of the external substrate are respectively made conductive through one or more of electrically conductive paths D1, D2, D3 and D4 provided inside the insulation substrate 3. Moreover, the tip of the conductive path of the semiconductor device is made as a bump electrode, the electrical connection are made more reliable between the semiconductor and the conductive path, between semiconductor devices and between semiconductor device and external substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layer structure, and more specifically, it can three-dimensionally and densely mount a semiconductor device in which two or more semiconductor devices each having a semiconductor device are stacked on an external substrate. The present invention relates to a multilayer structure semiconductor device.

[0002]

2. Description of the Related Art In recent years, with the development of electronic equipment, devices and equipment that use a large amount of semiconductor devices are required to be mounted with high density of semiconductor elements on a substrate having a constant area in accordance with the reduction in size, thickness and weight. A multi-chip module has been attracting attention as one suitable for its application. However, as long as semiconductor elements and chip components are two-dimensionally mounted on a substrate having a constant area as in the conventional case, the mountable amount is also limited, and a limit is seen due to the progress of higher density.

[0003]

In order to avoid such problems and realize higher density mounting, for example, a structure in which components are mounted on both surfaces of a circuit board has been proposed. Eventually, the problem of the area cannot be avoided, and since the components are mounted on both sides, there are many problems such as poor workability when mounting the components. Attempts have also been made to increase the packaging density by stacking semiconductor elements themselves three-dimensionally. According to this semiconductor device, the mounting area per unit area is remarkably improved, but the number of parts that can be stacked is limited, and the stacking work is troublesome.

An object of the present invention is to solve the above conventional problems and to provide a semiconductor device having a multi-layer structure in which semiconductor elements can be three-dimensionally mounted at high density. Another object of the present invention is to provide a multi-layer structure semiconductor device which can cope with a fine pitch of semiconductor element wiring.

[0005]

In order to achieve the above-mentioned object, a multi-layer structure semiconductor device of the present invention has two or more semiconductor devices each having a semiconductor element mounted on a recess provided in an insulating base material on an external substrate. A multilayer structure semiconductor device formed by stacking,
It is characterized in that the semiconductor element of each semiconductor device and the terminal of the external substrate are electrically connected to each other via an electric conduction path provided in the insulating base material.

In the following description, "conductor circuit" indicates a broad concept including not only wiring patterns but also electrodes, leads and the like. The term "terminal" includes the concepts of electrodes, pads, lands, and the like.

Further, the "recess" is not particularly limited in shape and size as long as it can accommodate and mount a semiconductor element, and at least one recess is formed and circuit wiring is provided. It may be formed so as to be exposed.

[0008]

According to the semiconductor device of the present invention, two or more semiconductor devices each having a semiconductor element mounted in a recess provided in an insulating base material are laminated on an external substrate to make the semiconductor device thin, and a wide variety of devices are available. The semiconductor elements of the above can be mounted three-dimensionally. Further, the electrical connection between the semiconductor element mounted on each semiconductor device and the terminal of the external substrate is sequentially performed through the electrical conduction path provided in the insulating base material of the semiconductor device which is a lower layer of the semiconductor device. Reliable and space-saving.

In the laminated semiconductor device, the number of electrical conduction paths increases as it goes to the lower layer. However, if the electrical conduction paths are electrically connected by a conductor circuit provided in the insulating base material. The electric conduction path can be freely formed according to the formation of the conductor circuit. Therefore, the electrical conduction paths can be formed close to the insulating base material and can be formed at a high density, and it is possible to sufficiently cope with the fine pitch of the semiconductor element wiring.

[0010]

The present invention will be described in more detail below with reference to the drawings showing the embodiments. The present invention is not limited to these examples. FIG. 1 is a partially cutaway sectional view showing an embodiment of a multi-layered semiconductor device of the present invention. In the figure, T is a multi-layered semiconductor device (a four-layered structure in this example). It is laminated in layers. Each semiconductor device H is
It has an electrical conduction path D1 for conducting the semiconductor element mounted in the recess to the lower semiconductor device or the external substrate 1.
In addition, each of the semiconductor devices H (2), (3), and (4) other than the uppermost semiconductor device H (1) has an electrical conduction path formed in a semiconductor device located in an upper layer thereof. It has one or more of electrical conduction paths D2, D3, and D4 that are electrically connected to terminals of a semiconductor device or an external substrate located in a lower layer.

The electrical conduction path D1 is provided in the insulating base material 3 and electrically connects the semiconductor element mounted in the recess to the lower semiconductor device or the terminal of the external substrate.
The electrical conduction paths D2, D3, D4 are respectively connected to the electrical conduction paths formed in the upper layer and electrically connected to the electrical conduction path of the semiconductor device in the lower layer or the terminal of the external substrate.

The electrical conduction paths D1, D2, D3 and D4 are
As shown in FIG. 1, it is preferable that all are electrically connected to the insulating base material by conductor circuits 2, 2a ... Taking the semiconductor device H (1) as an example, a conductive path 6 that extends in the thickness direction from the conductor circuit 2 embedded in the insulating base material 3 toward the recess of the insulating base material and is exposed at the recess bottom surface 5a. , A conductive path 7 extending in the thickness direction toward the surface of the insulating base material opposite to the recess forming side and exposed on the surface 3b opposite to the recess forming side 3a.
1 is formed. It should be noted that any of the conductor circuits is not necessarily embedded in the insulating base material, and may be on the surface of the insulating base material.

Metal protrusions (hereinafter referred to as bump electrodes), which are contact portions protruding outward from the surface of the insulating base material, are formed at both ends of the electrical conduction path D1. The bump electrode is at a position where it contacts the terminal 20 of the semiconductor element,
Further, they are respectively formed at positions where they abut on the electrical conduction path D2 of the semiconductor device H (2) located in the lower layer. It goes without saying that any end portion of the electrical conduction paths D2, D3, D4 may be similarly used as a bump electrode.

At this time, it is preferable that the electrical conduction path that is electrically connected to the bump electrode is recessed from the surface of the insulating base material in a shape that fits into the bump electrode (for example, an aspect in which the conductor circuit is exposed). Is preferable). Thus, by positioning the bump electrodes for external connection of the semiconductor devices to be stacked in the recessed portions, the positioning connection becomes simple.

When a solder layer is provided on the surface of the bump electrode, the terminal of the semiconductor element connected to the bump electrode, the conductor circuit (planar electrode), the terminal of the external substrate, etc.,
This is preferable because the electrical connection becomes more reliable and the connection reliability is improved.

In the above embodiment, the electrical conduction path D1
Although bump electrodes were formed on both tips of
As shown in the partial cross-sectional view of FIG. 3, the terminal portion of the semiconductor element can be a bump electrode and the tip of the electrical conduction path of the semiconductor device can be a planar electrode.

Taking the semiconductor device H (2) as an example,
Electrically conductive path including a conductor circuit 2a embedded in the insulating base material 3 and a conductive path 7a extending from the conductive circuit in the thickness direction of the insulating base material and exposed at the surface 3b opposite to the recess forming side. D
2 is formed. Conduction path 7 of the electrical conduction path D2
A bump electrode, which is a contact portion protruding outward from the surface of the insulating base material, is formed at the tip of a. The bump electrode is formed at a position in contact with the electrical conduction path D3 of the lower semiconductor device H (3).

In the present invention, the conductor circuit is not limited to one layer when forming the electrical conduction path, and the conductor circuit may be provided between the conductor circuits depending on the number of pins, the layout of the wiring, or the arrangement of the conduction path in the vertical direction. A multi-layer structure in which they are connected by conductive paths can be used. With this configuration, the electrical conduction paths can be freely formed in an arbitrary shape, and the electrical conduction paths can be arranged close to each other to be formed in a high-density array.

In the four-layered semiconductor device T,
The semiconductor element S1 mounted on the semiconductor device H (1) includes the electrical conduction path D1 of the semiconductor device H (1) and the semiconductor device H (1).
Through the electrical conduction path D2 of (2), the electrical conduction path D3 of the semiconductor device H (3), and the electrical conduction path D4 of the semiconductor device H (4), to the terminal portion 11 of the external substrate 1. It is conducted. Similarly, the semiconductor elements S2, S3, S4 are electrically connected to the terminal portions of the external substrate.

As is clear from the above-described embodiments, in the semiconductor device having a multi-layer structure of the present invention, the electrical conduction paths increase in the lower layers of the stacked semiconductor devices.

The material of the above-mentioned insulating base material may be any material as long as it has electrical insulation properties and also has a proper flexibility, for example, polyester resin, epoxy resin, urethane resin. , Polystyrene resin,
Any thermosetting resin or thermoplastic resin such as polyethylene resin, polyamide resin, polyimide resin, ABS resin, polycarbonate resin, silicone resin, or fluorine resin can be used. Further, it is also possible to use those obtained by impregnating these resins with glass cloth or the like. Among these resins, it is preferable to use a polyimide resin from the viewpoint of heat resistance and mechanical strength. In addition, especially when high signal transmission speed is required such as for large computer applications, it is effective to use a low dielectric constant fluorine-containing polyimide resin or fluorine-based resin for all or part of the insulating base material. Target. In the present invention, a layer or film made of the above materials is used as a substrate.

The recess for mounting the semiconductor element is similar to the mounted semiconductor element and is set to be slightly larger than the semiconductor element. Further, the depth is preferably set so that the semiconductor element is not exposed above the surface of the insulator. With this recessed shape, the semiconductor element can be housed in the recessed portion, and the semiconductor device can be thinned.
In addition, a wide variety of semiconductor elements can be mounted.
When the thickness of the semiconductor element is thicker than the depth of the recess and the element protrudes above the surface of the insulator, the height of the bump electrode for external connection is set to the insulation for forming the semiconductor element and another semiconductor device. It should be set so that it does not come into contact with the body.

The material for forming the conductor circuit, the conductive path and the bump electrode is not particularly limited as long as it has conductivity, and known metal materials can be used. For example, gold, silver, copper, platinum. , Lead, tin, nickel, cobalt,
Examples include single metals such as indium, rhodium, chromium, tungsten, and ruthenium, or various alloys containing these as components, such as solder, nickel-tin, and gold-cobalt.

In the present invention, as shown in the sectional view of FIG. 2, the recesses 5 can be formed at a plurality of positions on the same plane side of the insulating base material 3. With this configuration, the packaging density of semiconductor elements can be further improved.

Further, in the present invention, as shown in the sectional view of FIG. 3, the recess 5 can be formed in two steps. With this configuration, the semiconductor element is not face-down connected to the electrical conduction path, but the semiconductor element is die-bonded to the bottom surface of the recess, and the lead portion exposed at the raised portion of the recess is wire-bonded. You can connect. This two-step recess structure has an advantage that the conventional semiconductor mounting technology can be used as it is.

Further, in the above-mentioned two-step recess structure, as shown in FIG. 4, connection can be made by using TAB beam leads instead of wire bonds, and workability and productivity for mounting semiconductor elements can be improved. become able to.

The above semiconductor device is manufactured, for example, by the following method. First, an insulating base material such as thermosetting polyimide or thermoplastic polyimide is laminated on a conductor such as copper foil. Next, the conductor portion of the laminated flexible substrate is etched into a predetermined pattern by a known method to form a conductor circuit. Next, a hole reaching the conductor circuit is formed in the portion where the conductive path is provided from the side of the insulating base material. As a method for forming the holes, chemical etching, ablation by laser light, or photosensitive polyimide is appropriately used.

Subsequently, the hole is filled with a metal substance, and a conductive path for connection is formed at the tip as a flat electrode or a bump electrode. Copper, silver, gold,
Metals such as tin, lead, nickel, cobalt, indium,
Alternatively, various alloys containing these as components are used. Examples of the filling method of the metal substance include an electrolytic plating method and a printing method of a metal paste, but the electrolytic plating method of filling the hole portion with the metal substance by using the conductive layer exposed at the bottom of the hole as a cathode to fill the minute hole This is preferable from the viewpoints of metal filling property and formability of bumps of uniform height. Also,
As a method of forming only the bump portion, a well-known so-called transfer bump forming method can be used to easily obtain a highly uniform bump.

Of the individual printed circuit boards thus formed, the portions corresponding to the recesses for mounting the semiconductor are preliminarily formed by a method such as punching press or laser processing into a shape in which the predetermined portion faces the semiconductor element. An opening is formed in. The individual printed boards thus formed are thermocompression-bonded and laminated using a known method such as a hot press to form a board for mounting a semiconductor element. In this step, the conductor circuits inside the insulating base material are connected to each other via the bump electrodes.

In the above manufacturing example, the semiconductor connecting bump electrodes and the external connecting bump electrodes are formed at the same time when the individual printed boards are formed. However, these bump electrodes may be formed after the individual printed boards are laminated. . According to this method, it is possible to suppress damage to the bump electrodes exposed to the outside when the individual printed circuit boards are laminated.

The recess for mounting the semiconductor element can also be formed by half-etching the insulating base material after stacking the printed boards. In this case, as the half-etching method, either wet etching or dry etching can be used. However, considering the ease of controlling the etching depth, dry etching with an ultraviolet laser such as an excimer laser is used. It is preferable to use.

6 and 7 are schematic process diagrams showing a specific manufacturing method of the above-mentioned semiconductor device. The method shown in FIG. 6 is to form the element mounting recess after stacking the printed boards. On the other hand, in the method shown in FIG. 7, an insulative base material punched into the shape of a semiconductor element in advance is laminated to form an element mounting recess.

As shown in FIG. 8, each semiconductor device in which a semiconductor element is mounted in the recess of the semiconductor device manufactured as described above and then the above-mentioned predetermined electrical conduction path is formed is shown in FIG.
The multi-layer structure semiconductor device of the present invention is manufactured by sequentially stacking on an external substrate (not shown) and connecting to the external substrate using a known method such as reflow.

In the present invention, as shown in the sectional view of FIG.
It is possible to form at least one or more through holes that penetrate the insulating base material on the bottom surface of the recess of the semiconductor device in the thickness direction and communicate the outside with the inside of the recess. With this structure, the circulation of air in the semiconductor device is facilitated, and the heat dissipation is improved. Further, the presence of such a through hole can prevent the insulating resin layer of the semiconductor element mounting portion from changing in dimension due to moisture absorption and the like, and thus can reduce distortion due to the dimension change.

Further, in the present invention, as shown in the sectional view of FIG. 10, the periphery of the semiconductor element mounted in the recess can be sealed with a sealing resin. The resin used for this encapsulation is not particularly limited as long as it is a resin generally used for encapsulating semiconductor elements such as epoxy resin, silicone resin, and fluororesin. As a sealing method, potting, casting, transfer molding or the like is used. When the through holes are formed in the insulating resin layer of the recesses, voids and the like do not occur in the above sealing, and good sealing is possible. In particular, when a resin having a low viscosity is used, the resin is filled into the voids of the recesses through the through holes due to the capillary phenomenon, so that the sealing reliability is increased.

Further, as shown in the sectional view of FIG. 11, for example, the periphery of the semiconductor element is sealed with a flexible insulating resin such as silicone resin or fluororesin, and the outside is sealed with an epoxy resin or the like. You can also do it. With this configuration, the stress applied to the semiconductor element is buffered,
The adverse effect of the stress is reduced. Further, when polyimide is used as the insulating base material, it has excellent adhesiveness with the epoxy resin, so that intrusion of water from the interface between the epoxy resin and the polyimide resin is prevented, and the sealing reliability is significantly improved.

FIG. 12 is a partial cross-sectional view showing an example in which an adhesive resin layer made of a thermoplastic resin or a thermosetting resin is provided to completely adhere the interfaces between the stacked semiconductor devices to each other. By doing so, the connection reliability of the electrode portion can be improved, and by integrating each semiconductor device, the shock resistance of the semiconductor device can be improved and the reliability can be increased. The above-mentioned thermoplastic resin or thermosetting resin is not particularly limited, and any one commonly used as an adhesive can be used. Particularly when heat resistance and reliability are required, it is preferable to use thermoplastic polyimide.

As a method for bringing the above semiconductor devices into close contact with a resin, for example, an adhesive resin layer is provided on the substrate by means of coating or the like, or an adhesive insulating sheet is sandwiched between the substrates, and this is subjected to a hot press or the like. It may be laminated. On this occasion,
It is necessary to contact the bump electrode and the conductor circuit. However, if the mode illustrated below is adopted, the contact is not necessary. That is, as shown in FIG. 13 (a), by using conductive particles such as metal particles dispersed in the adhesive insulating resin layer to conduct electricity only in the pressure bonding direction (thickness direction), a so-called anisotropic conductive adhesive sheet is used. It was what I had. In addition, FIG.
(B) uses an adhesive insulating resin layer in which a columnar conductive material is embedded in the thickness direction of the sheet. These connection methods may be used for any connection between semiconductor mounting boards or printed boards forming the same.

In the multi-layered semiconductor device of the present invention, a heat dissipation structure can be installed by connecting to a heat exchange device such as a heat sink provided on the outer periphery. 14
[Fig. 3] is a sectional view showing this example. A through hole is formed in the bottom surface of the recess of each semiconductor device, and the hole is filled with a high thermal conductive material. Further, a high thermal conductive material layer is also formed on a portion other than the connecting bump electrodes between the semiconductor devices in a range not contacting the bump electrodes. Further, the heat conduction path formed upward from the high thermal conductivity material layer is connected to the heat sink arranged at the uppermost portion. The heat conduction path is formed in an insulating base material of a semiconductor device by filling a through hole penetrating in the thickness direction while avoiding the recess forming portion and the electrical conduction path with a high heat conductivity material. By forming such a heat dissipation structure, it becomes possible to cope with a large output semiconductor element that generates a large amount of heat.

As the high thermal conductive material used here,
Similar to the electrode portion, a metal substance that can be plated is more preferable, and in consideration of heat conduction, copper or an alloy thereof is particularly preferable.

[0041]

As described above, according to the multi-layer structure semiconductor device of the present invention, each semiconductor device is provided with the concave portion in the insulating base material, and various semiconductor elements are mounted in the concave portion. Even though it is thin. Moreover, since the semiconductor element of each semiconductor device and the terminal of the external substrate are connected to each other through the electrical conduction path provided in the insulating base material, space saving is achieved, and the semiconductor element is three-dimensionally manufactured. Can be mounted at high density. Further, since the semiconductor element can be easily mounted by simply dropping it into the recess, positioning when mounting the semiconductor element becomes easy.

Further, as the lower layer is formed, a larger number of electrical conduction paths are formed in the semiconductor device.
At that time, it is also possible to form a high-density array by biting a conductor circuit in the electrical conduction path or by forming the conductor circuit in multiple layers. Therefore, without increasing the mounting area, it is possible to cope with a large number of pins, which increases the degree of freedom in the design of the connecting electrodes on the board, and it is possible to cope with the fine pitch of semiconductor element wiring. Is.

In the semiconductor device, if the tip of the electrical conduction path is formed as a bump electrode, the electrical connection between the semiconductor element and the semiconductor device or between the semiconductor devices or between the semiconductor device and the external substrate is more reliable. Done

[Brief description of drawings]

FIG. 1 is a partially cutaway sectional view showing a semiconductor device having a four-layer structure according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a semiconductor device having a plurality of recesses formed therein.

FIG. 3 is a partial cross-sectional view showing a semiconductor device having a two-step recess formed therein.

FIG. 4 is a partial cross-sectional view showing an example in which semiconductor elements mounted in two-step recesses are connected using TAB beam leads.

FIG. 5 is a cross-sectional view showing an example in which a terminal portion of a semiconductor element is a bump electrode.

FIG. 6 is a schematic process diagram showing a specific method for manufacturing a semiconductor device.

FIG. 7 is a schematic process diagram showing another specific method for manufacturing a semiconductor device.

FIG. 8 is a schematic process diagram showing a method for manufacturing a multi-layer structure semiconductor device of the present invention.

FIG. 9 is a cross-sectional view showing a semiconductor device in which a through hole is formed in an insulating base material of a recess.

FIG. 10 is a cross-sectional view showing an example in which a semiconductor element mounted in a recess is resin-sealed.

FIG. 11 is a cross-sectional view showing an example in which the periphery of a semiconductor element is sealed with a flexible insulating resin, and the outside is sealed with an epoxy resin.

FIG. 12 is a cross-sectional view showing an example in which an interface between individual semiconductor devices is adhered with a resin.

FIG. 13 is a partial cross-sectional view showing a method of bringing the semiconductor devices into close contact with each other by resin. 13 (a) is a method using an anisotropic conductive adhesive sheet in which conductive particles are dispersed in an adhesive insulating resin layer, and 13 (b) is a columnar conductive material embedded in the thickness direction of the sheet. The method of using the adhesive insulating resin layer will be described below.

FIG. 14 is a cross-sectional view showing an example in which a heat dissipation device is formed on the outer periphery of a multi-layer structure semiconductor device to form a heat dissipation structure.

[Explanation of symbols]

 1 External Substrate 2, 2a Conductor Circuit 3 Insulating Substrate 3a One Side 3b Opposite Side 5 Semiconductor Element Mounting Recess 5a Recess Bottom 6,7 Conducting Path 11 External Board Terminal 20 Semiconductor Element Terminal D1, D2, D3 , D4 Electrical conduction paths H (1), H (2), H (3), H (4) Semiconductor device S1, S2, S3, S4 Semiconductor element T Multi-layer structure semiconductor device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 25/10 25/11

Claims (8)

[Claims] 1. A multi-layered semiconductor device, comprising: a semiconductor device having a semiconductor element mounted in a recess provided in an insulating base material; and a semiconductor device having two or more layers stacked on an external substrate, the semiconductor device being provided in the insulating base material. A semiconductor device having a multi-layer structure in which a semiconductor element of each semiconductor device and a terminal of an external substrate are electrically connected via an electric conduction path. 2. The multi-layer structure semiconductor device according to claim 1, wherein the electrical conduction path has a conductor circuit provided on the insulating base material. 3. The multi-layered semiconductor device according to claim 1, wherein the electrical conduction path is formed as a protruding electrode protruding outward from the surface of the insulating base material. 4. The multilayer structure semiconductor device according to claim 2, wherein the conductor circuit is embedded in an insulating base material. 5. The multilayer structure semiconductor device according to claim 1, wherein the semiconductor device has at least one through hole penetrating the bottom surface of the recess of the insulating base material in the thickness direction. 6. The semiconductor device has a plurality of heat conduction paths that penetrate the insulating base material in the thickness direction while avoiding the recesses and the electrical conduction paths, and the heat conduction paths are provided in the outer peripheral portion. The multi-layered semiconductor device according to claim 1, wherein the multi-layered semiconductor device is connected to the device. 7. The multi-layer structure semiconductor device according to claim 1, wherein the semiconductor element is sealed in a recess of the semiconductor device with an insulating resin. 8. The multi-layer structure semiconductor device according to claim 1, wherein the interfaces between the semiconductor devices are adhered by an adhesive resin layer.