JPH07104928B2 - Image processing device - Google Patents

Description

The present invention relates to an image processing apparatus for processing an input image signal according to a pulse signal having a predetermined pattern.

[Prior Art] Conventionally, for example, a dither method or a density pattern method using a threshold matrix is well known as a method of binarizing an image including a halftone image tone. However, especially when the halftone image is binarized by these methods, there is a drawback that moire fringes are generated due to the beat of the periodic structure of the halftone dot and the threshold matrix, and the image quality is remarkably deteriorated. Further, not only the halftone dot image but also the line image such as a character has a drawback that the edge portion becomes jagged.

[Problems to be Solved by the Invention] The present invention has been made in view of the drawbacks of the above-described conventional examples, and its purpose is to obtain a reproduced image output of high quality, and a further object is, for example, a halftone image. Another object of the present invention is to propose an image processing device that faithfully reproduces an image of an original including at least one of a character image and a halftone image.

[Means for Solving the Problems] According to the configuration of the present invention for achieving the above object, an input means for inputting a digital image signal represented by a plurality of bits for each pixel, and a digital input by the input means are provided. Identification means for identifying the characteristics of the image represented by the image signal; and a first pattern signal generated by comparing the digital image signal for each pixel input by the input means with a first pattern signal.
Pulse width modulation signal generating means for selectively outputting the second pulse width modulation signal generated by comparing the pulse width modulation signal and the second pattern signal according to the discrimination result by the discrimination means. An image processing apparatus having, wherein the first pattern signal has a predetermined number of pixels of the digital image signal input by the input means as one cycle,
It is a pattern signal having an extreme value inside the one cycle,
The second pattern signal is a pattern signal having a period different from that of the first pattern signal.

Embodiments Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

<Principle> As an embodiment of the present invention, for example, the image processing apparatus of the embodiment shown in FIG. 1 adjusts the image tone by detecting whether the input image signal 1a corresponds to, for example, an edge portion of an image. The recognition circuit 13 for recognition, a SELECT signal 19 whose value changes according to the recognition result of the recognition circuit 13, and a pattern pulse 42 having a predetermined pattern, which is a pulse having a frequency according to the value of the SELECT signal 19. Timing signal generation circuit 7, which generates
It comprises a pulse pattern generation circuit 3 and a binarization processing unit (D / A converter 2, comparator 4 etc.) for binarization by PWM (pulse width modulation).

Under the above configuration, the output of the identification circuit 13 is the SELECT signal 19
Changes correspond to changes in the image tone of the input image signal.
For each change, the timing signal generating circuit 7 and the pattern pulse generating circuit 3 cause the pattern pulse 42 (screen)
Is generated by changing the cycle, and the cycle is a cycle according to the image tone identified by the identifying circuit 13. Therefore, the screen processing is performed with a short-period pattern pulse when the image tone requires fine screening, and with a long period screening when rough screening is sufficient.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

<Structure of Embodiment> FIG. 1 is a schematic view of an image processing apparatus according to this embodiment. In the figure, 1 is a video data output unit, which performs A / D conversion of image data from a CCD sensor or a video camera (not shown), and outputs a predetermined bit (6 bits in this example) of digital image data 1a having density information. Output. This digital image data 1a may be temporarily stored in a memory (not shown), or may be input from an external device by communication or the like. The image data 1a from the digital data output unit 1 is 6-bit image data as shown in the figure and is input to the buffer memory 11 in the next stage. The buffer memory 11 is used by the identification circuit 13 to take out a desired pixel in the image data for performing the image tone identification. The discrimination circuit 13 discriminates the image tone (which means the characteristic or property of the image),
The SELECT signal 19 corresponding to the image tone is output. SELECT signal
19 is input to the timing signal generating circuit 7 to change the frequency of the screen clock 12. The screen clock 12 is input to the pulse pattern generation circuit 3. The screening process in this embodiment means the pattern pulse 42 having a predetermined shape in synchronization with the screen clock 12, the image data 43 analogized by the D / A converter 2 and the pulse by the comparison method. It is binarized by width modulation. At this time, the frequency of the screen clock 12 determines the coarse density of the "screen" to be applied to the image data 43.

<Operation of Buffer Memory> The buffer memory 11 is composed of four line memories 11a to 11d as shown in FIG.
For 1a, one line is selected by the selector 15a and writing is performed to the selected line memory. On the other hand, the image signal already written is read by the selector 15b from the line memory which is not written, and is output as the image signals 16a, 16b and 16c. Also, writing to such line memory
11a, 11b, 11c, 11d are sequentially performed, and finally the output image signal 16a
16c output image data of continuous 3 lines.
Further, by preparing four line memories, writing and reading can be performed simultaneously.

<Image Tone Recognition> The output signal from the line memory enters the discrimination circuit 13 at the next stage shown in FIG. The function of the discriminating circuit 13 is image tone recognition for detecting an edge of an image by the Laplacian filter operation shown in FIG. The hardware circuit of this Laplacian filter is shown in FIGS. 4 (a) and 4 (b). That is, the image signals 16a, 16b, 16c of each line are output from the five taps 17a to 17e through the delay circuits 20a to 20d for one pixel clock. A matrix element other than "0" in the filter shown in FIG. 3 corresponds to each tap. The output of each tap, that is, the portion (17a, 17a, corresponding to the coefficient "-1" in FIG. 4 (b).
17b, 17d, 17e) are all added by the adder 52. or,
The part (17c) of the coefficient “4” is multiplied by 4 by the multiplier 50.
Then, both are subtracted by the adder 18, and the target Laplacian
Get the output 18a. This Laplacian output 18a should be called the amount of edge of the image, that is, the amount representing the "degree" of the edge.
And a SELECT signal 19 is obtained. At this time, the identification circuit
13 is an output. The SELECT signal 19 is: a binary output in which the output is "1" when the image edge amount> k and the output is "0" when the image edge amount≤k. However, the parameter "k" at this time
Can be appropriately determined by the reference data 22. In this way, the identification circuit 13 recognizes the image tone of the area formed by the eight image data around the image data of the tap 17c and outputs the recognition result.
It is output as the SELECT signal 19. Of course, if the step of image tone recognition is made finer, for example, if the parameter "k" is set to a plurality of values, the output SELECT signal 19 is also made a few bits long, and more detailed image tone recognition can be performed.

<Pulse for Screen> The SELECT signal 19 is input to the timing signal generating circuit 7, and the image clock 11 and the screen clock 12 are obtained from the timing signal generating circuit 7. Here, the timing signal generating circuit 7 will be described in detail.

FIG. 5 is a block diagram of an example of the timing signal generating circuit 7. The inputs are the master clock 40, the SELECT signal 19 and the horizontal synchronizing signal 41, and the outputs are the pixel clock 11 and the screen clock 12. The pixel clock 11 is generated from the counter 46 in synchronization with the horizontal synchronization signal 41 generated for each line from the horizontal synchronization signal (HSYNC) generation circuit 5. still,
The horizontal synchronizing signal may be generated internally or may be given from the outside. Further, since this embodiment is applied to a laser beam printer, the horizontal synchronizing signal corresponds to a well-known beam detect (BD) signal.

The master clock 40 is counted down by the counter 46 to become the pixel clock 11. The degree of the countdown is determined according to how much "fluctuation" that occurs for each line of the screen clock 12 is suppressed as described later, but is 1/4 in this embodiment. That is, one pixel clock 11 is generated for four master clocks 40. The pixel clock 11 is used for the transfer clock of the image data and the latch timing of the D / A converter 2. "1
The / 3 "divider circuit 31 further counts down the pixel clock 11. That is, the clock 51 obtained from the" 1/3 "divider circuit 31.
Will be three times coarser than the pixel clock 11. The selector 30 selects the pixel clock 11 or the clock 51 which is three times rougher than the pixel clock 11 according to the SELECT signal 19 of the identification circuit 13. The one selected by the selector 30 becomes the screen clock 12. As described above, the SELECT signal 19 has a value of "1" for the edge portion of the image and a value of "0" for the non-edge portion. Therefore, the selected one of the screen clocks 12 is the edge portion of the image → the pixel edge of the image 11 and the non-edge portion of the image → the clock 51 divided by 1/3. The screen clock 12 is converted into a pattern pulse 42 having a predetermined shape by the pattern pulse generation circuit 3. In the case of this embodiment, it is a triangular wave. This pattern pulse is input to the comparator 4 for binarizing image data by PWM (pulse width modulation).

<Binarization processing by PWM> When explaining the PWM operation, in order to simplify the explanation,
It is assumed that the screen clock 12 selected by the timing circuit 7 is the clock 51 which is further divided from the pixel clock 11 by 1/3.

The image data corresponding to the center pixel of the image-tone recognized area is the output of the tap 17c. This output is delayed by one pixel by the delay circuit 14 and synchronized with the pattern pulse 42. Then, it is further converted into an analog quantity by the D / A converter 2, and the individual picture elements are sequentially input to one terminal of a comparison circuit (comparator) 4. The comparator 4 compares the analog-converted image signal 43 with the level of the pattern pulse 42 of, for example, a triangular wave, and outputs a pulse width-modulated PWM signal 45. And this PWM signal
45 is input to, for example, a modulation circuit (for example, laser driver 32 in FIG. 7) for modulating the laser beam. And the laser beam is turned on / off according to the pulse width,
A halftone image is formed on the recording medium (also the photosensitive drum 38).

FIG. 6 is a diagram for explaining signal waveforms of respective parts of the apparatus shown in FIG. Referring to FIG. 6, the master clock 40 is the output of the oscillator 6, and the BD signal is the horizontal synchronizing signal described above. Also, as described above, the pixel clock 11
Is the master clock 40 of the oscillator 6 counted down by the timing signal generating circuit 7. That is, the pixel clock 11 is a signal obtained by synchronizing with the horizontal synchronizing signal by the timing signal generating circuit 7 and counting down the master clock 40 to a quarter cycle. Screen clock 12
Is obtained by further counting down the pixel clock 11 obtained by the timing signal generation circuit 7 in the timing signal generation circuit 7 to one-third period, that is, once for every three pixel clocks 11. It has a cycle. The screen clock 12 is a synchronizing signal for generating the pattern pulse 42 of the triangular wave, and is input to the pattern signal generator 3. The digital data 44 is digital image data (code data), which is an image signal output from the video data output unit 1. The analog video signal 43 indicates the image data D / A converted by the D / A converter 2,
As can be seen from the figure, each pixel data of analog level is output in synchronization with the pixel clock 11. As shown in the figure, the higher the analog level, the higher the density.

The triangular pattern pulse 42 output from the pattern signal generator 3 is generated in synchronization with the screen clock 12 as shown by the solid line of "input to comparator" in FIG. The broken line in the figure is the image data that is analogized by the D / A converter 2, and is compared with the triangular pattern pulse 42 from the pattern signal generator 3 by the comparator 4, and as shown in the PWM signal 45, the image data Is pulse width modulated binary data.

As described above, in the binarization processing in this embodiment, after the digital image data is once converted into the analog image data, it is possible to perform almost continuous pulse width modulation by comparing it with the pattern pulse 42 having a predetermined period, and high gradation is obtained. The image output of is obtained. Further, according to the present embodiment, the master clock 40 having a frequency higher than the frequency of the synchronizing signal for generating the pattern pulse 42 (triangular wave in the present embodiment) (12 times the frequency of the triangular wave in the present embodiment) is used. Since the screen clock 12 synchronized with the horizontal synchronizing signal 41 is formed by using, the "fluctuation" of the pattern pulse 42 generated from the pattern signal generating circuit 3 (for example, the deviation between the pattern signals of the first line and the second line). ) Is 1/12 of the pattern pulse period in this embodiment. Therefore, since the grayscale information is pulse-width modulated almost steplessly by using the pattern signal with less "fluctuation", a high-quality reproduced image can be obtained.

The pulse-width-modulated video output generated as described above obtains 64-level analog output if the D / A converter 2 has an input of 6 bits, so that 64-level pulse-width modulated output is obtained.

In the above description of the PWM, the clock that determines the comparison rate in the comparator 4 is the 1/3 frequency divided clock 51, but when the selector 30 selects the pixel clock 11, the clock to the comparator 4 shown in FIG. The signal waveform of the triangular wave in the "input" portion is a triangular wave having one pixel clock 11 as one cycle. However, the triangular pattern pulse
Even if the cycle of 42 is changed, the comparison and the like in the comparator 4 at the subsequent stage are exactly the same. Therefore, as the output waveform of the final PWM signal, the following waveform is obtained according to the quality of the read image.

Edge part of image: Pulse width modulation output by pattern pulse 42 synchronized with one pixel clock 11 Non-edge part of image: Pulse width modulation output by pattern pulse 42 synchronized with three pixel clock 11 Therefore, it corresponds to the edge part An image output with a fine line number screen is obtained for the image area to be processed, and an output with a coarse line number screen is obtained for the non-edge portion.

FIG. 7 shows an example in which the signal processing of this embodiment is applied to a laser beam printer. The aforementioned PWM signal 39 is the laser driver 3
2 is modulated, and the semiconductor laser 33 is pulse-width modulated to emit light. The light beam emitted from the semiconductor laser 33 is a collimator lens.
The light is collimated by 34, deflected by the rotary polygon mirror 36, and scanned on the photosensitive drum 38 by the fθ lens 37.
The image of light formed on the photosensitive drum forms an electrostatic latent image, and the image is output by a normal copying machine process.

<Effect of Embodiment> The following can be said as a result of the image processing of the embodiment described above.

The edge portion of the character / line drawing is detected as an edge signal (SELECT signal "1") by the identification circuit 13 of this embodiment. With respect to the halftone image, since the input sensor for reading the document can sufficiently identify the halftone dot, it is detected as an edge signal by the discrimination circuit 13 of the present embodiment. At this time, for example, the output image output on the printer becomes a fine image. On the other hand, inside a thick character or in a portion close to a continuous tone such as a photograph, since it is a non-edge signal, the output is obtained by applying a coarse screen.

Here, for example, the resolution of a printer or the like that outputs a visible image is 400 dot per inchi (hereinafter abbreviated as 400 dpi).
, 400 line p for fine image output
A line screen of er inch (400 lpi) is suitable for rough image output, and output of 400/3 = 133 lpi is suitable. As a result, the SELECT signal = "1" for all parts for small characters, and the result is output at 400 lpi. For thick characters, only the edge part of the SELECT signal 19 = "1". Therefore, the outer edge of the character is processed at 400 lpi and the inner part of the character is processed at 133 lpi. Therefore, the problem that the characters, line drawings, etc. described above are cut off is solved.

Next, in the case of a halftone dot original, since the SELECT signal 19 = "1",
It will be output at 400 lpi, and the beat (moire) phenomenon due to the halftone dot original and the output dither will disappear. The reason is that moire occurs at the difference frequency (the number of lines) between the two, but since the number of output lines is high, the difference frequency also becomes large and becomes inconspicuous.

In the screening process in the above embodiment, the fine image is composed of the pixel clocks 11 and the rough image is composed of the three pixel clocks. For example, the original purpose is met for the time being.

Further, it goes without saying that a Laplacian filter using all 9 pixels shown in FIG. 8 may be used, and further, for example, a 5 × 5 matrix other than the 3 × 3 matrix may be used. Furthermore, the pattern pulse 42 is not limited to the triangular wave, but may be a sine wave, a sawtooth wave, or the like.

[Effect of the Invention] As described above, according to the present invention, the pulse width modulation signal generation means has the pattern signal of the optimum cycle according to the "feature of the image of the input digital image signal" identified by the identification means. Since the pulse width modulation signal by is output selectively,
Optimal image formation can be performed according to the image tone (indicating the characteristics or properties of the image).

Further, the “pattern signal” is a pattern such as “having an extreme value inside one cycle”, and therefore the pulse width of the signal after pulse width modulation is not from the beginning of one cycle of this pattern signal. , It starts to grow from its "extreme" that is "inside one cycle". Therefore, the spatial frequency of the image formed using such a pattern signal becomes constant, and substantially continuous pulse width modulation is possible, so that it is possible to obtain the effect of reducing beats such as the moire phenomenon. it can. Further, it is possible to achieve gradation in one pixel period, which cannot be achieved by dither processing.

Further, since one cycle of the pattern signal is set as the period of the predetermined number of pixels of the digital image signal, if the period of a plurality of pixels is set, for example, the pulse width modulation signal is generated in a concentrated manner around the extreme position of the pattern signal. Therefore, it is possible to reproduce an image having excellent gradation.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the embodiment, FIG. 2 is a diagram showing a configuration of a buffer memory, FIG. 3 is a diagram showing a matrix configuration of a Laplacian filter for image tone recognition, and FIGS. 4 (a) and 4 (b). ) Is a block circuit diagram constituting an identification circuit, FIG. 5 is an internal view of a timing signal generating circuit, FIG. 6 is a timing chart explaining the operation of pulse width modulation, and FIG. 7 is a case of a laser beam printer as an example. 3 is a diagram for explaining the output of the binary image of FIG. FIG. 8 is a matrix configuration diagram of another Laplacian filter. In the figure, 1 ... Video data output section, 2 ... D / A converter, 3 ...
Pattern signal generator, 4, 21 ... Comparator, 5 ... Horizontal sync signal generation circuit, 6 ... Oscillator (master clock generation circuit), 7 ... Timing signal generation circuit, 8b ...
Smoothing circuit, 9,15a, 15b …… Selector, 11 …… Buffer memory, 11a to 11d …… Line memory, 13 …… Identification circuit,
20a to 20f ... 1 pixel delay circuit, 21a to 21d, 22a, 22b, 25,
40,41 …… Adder, 24a, 24b …… Absolute value circuit, 42 …… Division
ROM, 32 ... Laser driver, 33 ... Semiconductor laser, 34
…… Collimator lens, 36 …… Rotating polygon mirror, 37 …… fθ
Lens, 38 ... Photosensitive drum, 50 ... Smoothed image data,
51 …… Binarization processing unit, 52 …… Master clock, 53 …… Analog image data, 54 …… Screen clock, 55 ……
It is a BD signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 1/40 A

Claims (1)

[Claims] 1. Input means for inputting a digital image signal represented by a plurality of bits for each pixel; identification means for identifying characteristics of an image represented by the digital image signal input by the input means; A first image signal generated by comparing a digital image signal for each pixel input by the means with a first pattern signal;
Pulse width modulation signal generating means for selectively outputting the second pulse width modulation signal generated by comparing the pulse width modulation signal and the second pattern signal according to the discrimination result by the discrimination means. An image processing apparatus having, wherein the first pattern signal has a predetermined number of pixels of the digital image signal input by the input means as one cycle,
It is a pattern signal having an extreme value inside the one cycle,
The image processing apparatus, wherein the second pattern signal is a pattern signal having a period different from that of the first pattern signal.