JPH07104828B2 - Data transfer buffer circuit - Google Patents

Description

DETAILED DESCRIPTION [Overview] In a data transfer buffer circuit used for data exchange, a circuit that prepares a plurality of buffers corresponding to a data transfer source and outputs a buffer full signal of each buffer,
By providing a circuit that selects a buffer according to the state of each buffer and a transfer source and a circuit that sends out the data read from the selected buffer, each of a plurality of data transfer sources transfers to a plurality of data transfer destinations. When transferring data, the amount of buffer required is reduced and the control of data transfer is simplified.

[Industrial application field]

The present invention relates to a data transfer buffer circuit used in a multiprocessor system in which, for example, a plurality of processors carry out processing while exchanging data with each other to accomplish one job, and it is particularly efficient and simple. The present invention relates to a data transfer buffer circuit capable of realizing a network system for exchanging data under various controls.

[Conventional technology]

An architecture for accelerating processing by arranging a large number of processors, connecting them with a communication network, dividing one job into each processor, and exchanging data with each other using the communication network while proceeding in parallel. Is being considered.

In such a system, a device that exchanges data between processors at high speed and easily with a minimum amount of material is required. However, conventionally, there is no suitable device for such data exchange, and data exchange is performed by means such as switching with a switch or reading / writing to a common memory.

[Problems to be solved by the invention]

FIG. 6 is a diagram for explaining the problem of the present invention. In FIG. 6, 70 is a switch, 71 is a data transfer source, 72 is a data transfer source, 73 is an input buffer, and 74 is an output buffer.

When performing data transfer from a plurality of data transfer sources 71 to a plurality of data transfer destinations 72, for example, as shown in FIG. 6A, the data transfer source 71 and the data transfer source 72 are connected via the switch 70. In the directly connected configuration, if the data transfer destinations 72 conflict, it is necessary to have one of the data transfers, and it is necessary to control its own data transfer timing depending on the transfer request of another processor. .

In order to simplify this control, for example, as shown in FIG. 6 (b), an input buffer 73 and an output buffer 74 having sufficient capacity are placed before and after the switch 70 to prevent contention of the data transfer destination 72. It is possible to store the data to be transferred when it happens.

However, the method shown in FIG. 6 (b) requires a large amount of buffers, and in particular, when the circuits for exchanging data are connected in multiple stages, there is a problem that the buffers are wasted. .

The present invention aims to solve the above problems, and with a small number of buffers,
Moreover, it is an object of the present invention to provide a data transfer buffer circuit that enables a data transfer source to transfer data without being aware of competition with other data transfer sources.

[Means for solving problems]

 FIG. 1 shows a basic configuration example of the present invention.

In FIG. 1, 20 is a PISO (parallel serial out) buffer, 30 is a buffer, 31 is a selector, 40 is a selection determiner, 41-0 to 41 to 3, 41-X is a register, 42 is a multiplexer circuit, Reference numeral 43 represents a buffer full signal output circuit. Also, DI
0 to DI3 are input signals containing data, DO is output signal, F0 to F3 are buffer full signals, N0 to N3 are residual data amount signals, R0 to R3 are read signals, D0 to D3 are read from each buffer Data and SEL represent selection signals.

In the following description, the case where the number of data transfer destinations is 4 and the number of data transfer destinations is 4 will be described as an example.

The PISO buffer 20 corresponds to the data transfer buffer circuit of the present invention.

Each buffer 30 is provided corresponding to the data transfer source.
The input signals DI0 to DI3 to the respective buffers 30 are roughly n pieces of data including parity bits and one data valid signal. Data is independently fetched into each buffer 30 in accordance with the data valid signal. Buffer 30
Is composed of, for example, a FIFO memory, and when each buffer 30 becomes full (or the data amount exceeds a certain threshold value), a buffer full signal is output via the buffer full signal output circuit 43.

The selector 31 is a circuit that preferentially selects the buffer 30 in which the most data is accumulated, generates a data valid signal from the transfer destination address or the like shown in the data, and outputs the data. That is, the selection determiner 40 uses the buffers 30
One of the buffers 30 is selected by the data residual amount signals N0 to N3 from the buffer and the buffer full signal from the transfer destination, and the data read signals R0 to R3 for the buffer 30 are output.
It also outputs the selection signal SEL to the multiplexer circuit 42. Based on this selection signal SEL, the multiplexer circuit 4
The data selected by 2 is output via the register 41-X. A data valid signal indicating a data transfer destination is added to this output, and the output signal DO is composed of n data and four data valid signals corresponding to the transfer destination.

This PISO buffer 20 has a structure that can be connected to other PISO buffers having the same structure in multiple stages.
Is an input signal DIi (i = 0 to 3) to another PISO buffer
It can be used for.

[Action]

The buffer 30 is provided corresponding to the data transfer source, and the data from the data transfer source is stored independently of the transfer source, so that the data transfer destination is the other data transfer destination. It is possible to send data while being aware of the buffer full signal regardless of the original state.

One of the buffers 30 is selected by the selection determiner 40 according to the remaining data state of each buffer 30 and the state of the transfer destination, and the data read from it is selected by the multiplexer circuit 42 and automatically output. Therefore, the buffer 30 can be utilized without waste in space and time.

At the data generation source or the data transfer destination that relays the data, the data is automatically sent to the desired transfer destination simply by sending the data to the buffer 30, so control is extremely simple.

〔Example〕

2 is an example of the format of communication data used in an embodiment of the present invention, FIG. 3 is an example of the internal configuration of the buffer shown in FIG. 1, and FIG. 4 is an example of the internal configuration of the selection deciding device shown in FIG. ，
FIG. 5 shows an example of an application system of the present invention.

The format of communication data in the communication system in which the present invention is used is, for example, as shown in FIG.

One data transfer unit is generally of variable length, and the data width W is the amount of data that can be moved on the network in one clock. This data width W is called a data word. A group of data is distinguished by the data delimiter information SD at the beginning of each data word. For example, if the data delimiter information SD is 1 bit, only the end of the data is "1" (END)
The data delimiter is recognized by setting "1" and setting other values to "0". However, when the data transfer unit has a fixed length, the data delimiter information SD is unnecessary. For example,
The first data word has address information of the data transfer destination.

The registers 41-0 to 41-3 shown in FIG. 1 initially latch data including the transfer destination address, which is the first word of the data shown in FIG.

The internal structure of the buffer 30 shown in FIG. 1 is as shown in FIG. 3, for example. In FIG. 3, 50 is a memory cell array, 51 is a write address register, 52 is a read address register, 53 is a subtracter, and 54 and 55 are AND circuits. CLK represents a clock.

The write data to the memory cell array 50 is written to the address indicated by the write address register 51. The write address register 51 is counted up by the write signal Wi generated by the data valid signal.

Reading from the memory cell array 50 is performed from the address indicated by the read address register 52. The read address register 52 is counted up by the read signal Ri generated by the selection determiner 40 shown in FIG.

The subtractor 53 calculates the difference between the value of the write address register 51 and the value of the read address register 52. This difference is notified to the selection determiner 40 as the data residual amount signal Ni.
This signal may be the actual number of remaining data, but for example, only the upper j bits of the address are used for the operation.
The number of signal lines can be reduced by compressing the information, teaching the amount of data sampled to the power of j, and adding one representing the sky. For example, the buffer depth
When 2K words are used, 11 bits are required to represent the remaining number. If j = 2, "00" is 0 to 0.5K words, "01".
0.5K to 1K words for "10" 1K to 1.5K words, "11" for 1.5K
Up to 2K words, one for empty and one for full, if necessary, can be configured with four buffers.

Further, the buffer full signal Fi can be generated from the output of the subtractor 53.

The selection determiner 40 shown in FIG. 1 is, for example, as shown in FIG. 4. In FIG. 4, 60 is a buffer selection determining circuit and 61 is an address decoder.

The address decoder 61 includes registers 41-0 to 41-0 shown in FIG.
The transfer destination address on 41-3 is decoded and a signal indicating the transfer destination is output. The buffer selection decision circuit 60 receives the buffer full signal of the transfer destination and holds the data to the transfer destination which is not currently full 30 shown in FIG.
Is recognized from the output of the address decoder 61, and the buffer having the largest data residual amount is recognized from the signals N0 to N3 to determine which buffer 30 data is to be transferred. The determination result is notified to each buffer 30 as read signals R0 to R3. Further, the signal SEL for selecting the buffer 30 is output.

The multiplexer circuit 42 shown in FIG. 1 receives the selection signal SEL from the selection determiner 40 and selects one of D0 to D3.
Register 41-X latches that value. This data is output together with four data valid signals generated from the address decoding result. This data valid signal designates the buffer to fetch this data among the four transfer destination buffers. That is, in the present embodiment, four data valid signals are assigned to each of the four PISO buffers 20 shown in FIG. The data valid signal of the book is one of the input signals DI0 to DI3 in each PISO buffer 20.

In this selection status, the data delimiter information is selected by the selection determiner 40.
Is locked until it is detected from the data being transferred (the data selected from the registers 41-0 to 41-3). When the lock is released, the registers 41-0 to 41-0 again.
In 41-3, the data including the data transfer destination, which is the first word of the data, is latched, and the state returns to the initial state.
Although the circuit for detecting the data delimiter information is omitted in FIG. 4, it can be constituted by a simple logic circuit without needing to explain.

Position information of the PISO buffer 20 including the PISO buffer 20 on the communication network is preset in the selection determiner 40. As a result, the transfer destination address is set to the register 41-0.
.. 41-3, the address decoder 61 can determine to which of the four destination buffers the data should be sent.

The expression regarding the transfer destination address may or may not be unique. For example, if there are 64 processors and the transfer destination is represented by 6 bits, the transfer destination is unique and one of four data valid signals is used.
Only books are valid.

For example, the transfer destination is expressed in 12 bits, and each bit of the 6-bit address is expressed in 2 bits, and "00" = 0, "01" =
If multiple destinations are expressed at once such as 1, “10” = 1or0, “11” = 1or0, among the four data valid signals, multiple lines are valid at the same time and simultaneous transfer to multiple buffers is possible. It will be possible. In this case, for example, the transfer destination of "000000001001" is the 6-bit address "000001" and "000011".
The data valid signal for the two transfer destinations is validated. It should be noted that such an address expression can be modified in various ways.

FIG. 5 shows an example of a multiprocessor system using the PISO buffer according to the present invention. In Fig. 5, P
0 to P15 are processors, 20-i are PISO buffers, OP is an output port, and IP is an input port.

In this example, 16 processors are divided into groups of 4 and connected hierarchically via the PISO buffer.

The processors P0 to P3, P4 to P7, P8 to P11, and P12 to P15 are each in the first hierarchy group. Processor P0-P1
The whole of 5 is a group of the second hierarchy. The output port OP and the input port IP are connected to a host device or another external device.

For example, when sending data from the processor P0 to the processor P3, the processor P0 selects the PIS out of the four data valid signals.
Send data by validating only the data valid signal corresponding to the O buffer 20-3. In PISO buffer 20-3,
The input from the processor P0 is the input signal DI0 shown in FIG.
If it is assigned to the terminal of, the data is fetched in the buffer (0) 30 shown in FIG. And the selector
The data is transferred to the processor P3 via 31.

Data transfer from processor P4 to processor P11 is PISO
Buffer 20-X1, PISO buffer 20-18, PISO buffer 20-
Done via 11.

〔The invention's effect〕

As described above, according to the present invention, data exchange between a plurality of data transfer sources and a plurality of data transfer destinations can be performed with a small number of buffers and with simple control. It is especially useful for systems that require data communication between a large number of processors.

[Brief description of drawings]

FIG. 1 is a basic configuration example of the present invention, FIG. 2 is a format example of communication data used in an embodiment of the present invention, FIG. 3 is an internal configuration example of the buffer shown in FIG. 1, and FIG. FIG. 5 shows an example of the internal structure of the selection determiner shown in FIG. 1, FIG. 5 shows an example of an application system of the present invention, and FIG. In the figure, 20 is a PISO buffer, 30 is a buffer, 31 is a selector, 40 is a selection determiner, 41-0 to 41-3, 41-X are registers, 42 is a multiplexer circuit, 43 is a buffer full signal output circuit, DI0 ~ D
I3 is an input signal, DO is an output signal, F0 to F3 are buffer full signals, N0 to N3 are data residual amount signals, R0 to R3 are read signals, SEL
Represents a selection signal.

Claims (1)

[Claims] 1. A data transfer buffer circuit for exchanging data, each of which is supplied independently from a plurality of data transfer sources to a designated data transfer destination, the data transfer buffer circuit comprising: ， The output is provided so as to correspond to the input of the data transfer destination including the other data transfer buffer circuit having the same structure, and it is configured to be connectable in multiple stages, and each is supplied from the predetermined data transfer source. A plurality of sets of input terminals corresponding to the number of connectable data transfer sources for inputting at least a data input signal and a data valid signal indicating the validity of the data, and one or more connected data transfer destinations To a data output signal and a number corresponding to the number of data transfer destinations indicating the data transfer destinations that should receive this data among the transfer destinations of the connected data. Data supplied from the corresponding data transfer source when the data valid signal is valid, corresponding to one set of output terminals that outputs at least the data valid signal and each of the plurality of sets of input terminals A plurality of buffers (30) for independently receiving and storing data, and a buffer full signal output circuit (43) for outputting a buffer full signal when the amount of data stored in the buffer (30) exceeds a predetermined amount , One of the buffers (30) is selected according to the data remaining state of the buffer (30) and the state of the transfer destination, and a data read signal for the buffer (30) is generated, and the selected data is output to the output destination. In response, a data valid signal indicating that the data is valid only to the data transfer destination that should receive this data among the connected data transfer destinations is output. And a selective transmission circuit (42) for selectively transmitting the data read from the buffer (30) selected by the selection determiner (40). A data transfer buffer circuit.