JPH0697781B2 - Video signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical detail information signal derived from the output of, for example, a comb filter used in a television receiver to separate the luminance and chrominance components of a color television signal. The present invention relates to a device for processing non-linearly. More particularly, this invention relates to apparatus for coring and pairing vertical detail signals.

<Background of the Invention> In the color television projection system used in Japan and the United States, the luminance component and chrominance component of the color television projection signal have a luminance component which is an integral multiple of the horizontal scanning frequency of 1/2 of the horizontal scanning frequency. The chrominance components are arranged in an interpolated relationship with each other in the video signal spectrum such that the chrominance components are located at odd numbers. Luminance and chrominance components are often separated from each other in a color television signal by a comb filter, as shown, for example, in US Pat. No. 4,096,516 to DHPritchard.

The comb-filtered luminance signal appearing at the comb filter's luminance output undergoes combing over its entire band. The comb processing over the high frequency band is shared with the chrominance signal component and has the desired effect of removing the chrominance signal component. It is not necessary to extend this comb filtering to the low frequency band portion to obtain the desired effect of removing the chrominance signal component,
When the comb filtering process is extended to the low frequency band portion, it acts to remove the luminance signal component. The components in the low frequency end of such a removed band represent vertical detail luminance information. It is desirable that the luminance component of the displayed image retains such vertical detail information in order to prevent loss of vertical resolution.

One configuration for storing vertical detail information is a low pass filter connected to the output of a comb filter where the comb filtered chrominance components appear. The upper cutoff frequency of this filter is below the band occupied by the chrominance signal components. The filter supplies a signal below the chrominance band from the chrominance output of the comb filter to a combiner circuit, where the selectively supplied signal is the comb filtered luminance output signal from the comb filter. Is added. This comb-filtered signal is a comb-filtered high-frequency component (occupying a frequency band above the cutoff frequency of the filter) from which the chrominance signal components have been removed, and a non-comb-filtered (ie, flat-fractionated) component in which all luminance signal components are stored. The low frequency part is included.

It is often desirable to minimize the detrimental effects of both noise and interference, including common channel interference on the replayed video, without unduly reducing the detail of the replayed video. This is done by a process commonly referred to as signal coring (coring) to remove runout of small amplitude signals (including noise). More specifically, signal coring acts to remove the core near the mean axis of a signal by means of a conversion circuit having a transfer characteristic with a dead zone for signal amplitude fluctuations close to the axis. Signal coring is a well-known signal processing function that is often used for noise reduction purposes and is described in SMPTE Journal, March 1978, pp. 134-140, "Television."
Digital Tech for reducing noise (Digital Tech
Niques for Reducing Television Noise) ”in a paper by J. Rossi.

It may also be desirable to selectively reduce the magnitude of large video signal amplitude excursions by a process often referred to as signal pairing. Signal pairing acts to prevent blooming of the reproduced video signal and to prevent distortion or obscuring of image details. U.S. Pat. No. 4,295,160 to WALagoni describes a vertical detail signal processor having a non-linear transfer characteristic that correlates small signal amplitude excursions and pairs large signal amplitude excursions. ing. This is accomplished by a circuit that includes a feedback network with a diode switching impedance coupled from the output of the amplifier receiving the vertical detail input signal to the input. The conduction state of the diode is controlled by the magnitude of the vertical detail signal supplied to the amplifier, thereby selectively varying the magnitude of the feedback impedance with respect to the amplitude range of a given detail signal.

It has been found desirable to incorporate the vertical detail signal processor in the same integrated circuit as the comb filter, especially the charge coupled device (CCD) comb filter using MOS semiconductor technology. The vertical detail signal is taken from the output of the filter. In addition, it has been found desirable to provide a detail signal processor for a switching device such as a diode, which has a predictable non-linear transfer relationship that does not depend on the sometimes unpredictable threshold switching levels.

SUMMARY OF THE INVENTION The non-linear vertical detail signal processing apparatus described herein in accordance with a preferred embodiment of the present invention includes a plurality of cascaded amplification stages forming a vertical detail amplification path. The selected amplitude portion of the non-linearly processed vertical detail output signal from the amplifier is combined with the linear version of the input vertical detail signal.
The synthesized vertical detail signal is (a) corrugated for small amplitude excursions within the first amplitude range to remove this small amplitude, and (b) for medium amplitude excursions within the second amplitude range. The runout is transformed with a given amplitude greater than 0, (c)
Large amplitude swings within the third amplitude range are characteristic of being paired or damped.

Also shown is a vertical detail signal processor having improved operating characteristics which is another feature of the present invention. The processing device disclosed herein includes first and second keyed sample and hold networks, each of which is sampled of a vertical detail signal at the input of an associated amplifier in the detail signal amplification path. Supply the format. These sampling circuits operate at different times, and the second sampling network operates in the sampling state when the first sampling network is in the inactive state and the holding state. The sample and hold network can reduce the transient effects of the switching signal that occur in connection with the switching signal that times the operation of the comb filter during operation of the detail signal processor. The sample and hold circuit also has the effect of reducing the possibility of distortion of the non-linear transfer function of the processor, especially in the presence of high amplitude, high frequency vertical detail signal components.

<Detailed Description> In FIG. 1, the vertical detail signal extracted from the output of the comb filter as shown in FIG. 6 passes through the capacitor 10 and is input to the input terminal T1 of the non-linear vertical detail signal processing circuit by alternating current (AC).
Be combined. The vertical detail signal processing circuit consists of NMOS transistors configured as an integrated circuit on a common semiconductor substrate with a comb filter configuration.

The input inverting buffer amplifier 12 includes a plurality of cascaded inverting amplifiers 14, 15, 1 that show the same signal gain for vertical detail signals.
Supply to the main signal amplification path including 6 and 17. Connected between amplifiers 14 and 15 is a sample and hold circuit consisting of a keyed enhancement type NMOS switching device 20 and a charge storage capacitance device 22. Switch
20 is a source input electrode coupled to the output of amplifier 14;
It has a drain output electrode coupled to the capacitance element 22 and a gate electrode to which the keying signal 1 for controlling the conduction state of the switch 20 is supplied. Similarly, a keyed NMOS sample and hold circuit consisting of a keyed switch 24 and a storage capacitance element 26 responsive to the keying signal 2 is coupled between the output of amplifier 16 and the input of amplifier 17. The keying signals 1 and 2 represented by the waveforms in the figure have a frequency of 10.7 MHz, which corresponds to a frequency which is three times the subcarrier component of the chrominance component of the television signal of the NTSC television system. The phase relationship between the switching signals 1 and 2 is different in that the signals 1 and 2 sample (S) and hold (H) the signals at different points in time, and the switch 24 includes the preceding sample and hold network. It is activated for sampling at a time (S of 2) corresponding to the hold period (H of 1) for 20, 22. Accordingly, the sampling circuitry 24,26 resamples the signal samples provided by the preceding sampling circuitry 20,22. Series resistor elements coupled between amplifiers 15 and 16 are interconnected NMs arranged as shown.
It consists of OS devices 28 and 29. This resistive element is connected to amplifier 14
To provide the desired signal gain in the main signal path from the input to the output of amplifier 17.

The following description will be given with reference to FIG. 1, but the signal transfer characteristics are as shown in FIG.

The vertical detail signal (S1 ') from the output of the amplifier 12 is supplied to the signal addition point A via the delay compensation network 30 and the resistance element 32. In the resistive element 32, the gate electrodes are connected to each other,
A drain-source conductive path is formed by depletion mode NMOS devices 33, 34 connected in series. The delayed vertical detail signal transmitted to the connection point A via the resistive element 32 exhibits the linear transfer characteristic as shown in FIG. 2 for the signal S1.

The amplified vertical detail signal S2 'from amplifier 15 is generated by a voltage divider network formed by series resistance elements 42, 43 each consisting of NMOS devices 44, 45 and 46, 47 connected in series. The amplitude is converted. Associated with the voltage divider network is an inverter 48 having its input and output terminals connected together to generate a reference potential from a power supply voltage (not shown) supplied to device 47 at its low impedance output. Resistance elements 42, 43
The converted vertical detail signal appearing at the connection points of the two is sampled by a network including an NMOS switch 50 and a charge storage capacitance element 52 responsive to the keying signal 2. The sampled amplitude-converted vertical detail signal is supplied to the connection point A via an inverter 53 and a resistive element 55 composed of NMOS devices 56 and 57 connected in series. The converted vertical detail signal S2 supplied to the connection point A by the resistive element 55 exhibits a non-linear transfer characteristic as shown as S2 in FIG.

Further amplified vertical detail signal S from the output of amplifier 17.
3'represents NMOS devices 63, 64 and 65, 6 respectively as shown.
The amplitude is converted by a voltage divider network formed by the series resistive elements 60 and 62 of 6. The reference potential for this voltage divider is obtained from the low impedance output of the inverter 68 whose input and output terminals are connected together. The converted vertical detail signal appearing at the junction of resistive elements 60 and 62 is supplied to junction A via a resistive element 70 consisting of NMOS devices 71 and 72 connected in series. The converted vertical detail signal S3 transmitted by the resistive element 70 to the connection point A exhibits a non-linear transfer characteristic as shown as S3 in FIG.

The combined transfer characteristics of the signals S1, S2 and S3 show the combined output transfer characteristics at the connection point A as shown by the alternate long and short dash line in FIG. The vertical detail signal from node A is transmitted to the vertical detail signal output terminal T2 via a device 75 and an NMOS amplification stage including an output NMOS voltage follower device 78. The load circuit for the voltage follower device is constituted by a utilization circuit coupled to terminal T2.

The combined output transfer characteristic for the vertical detail signal at connection point A has three operating ranges for the three predetermined ranges of vertical detail signal amplitude levels. In FIG. 2, these regions are shown as regions I, II and III.

Region I contains small vertical detail signal amplitudes between 0 and +5 IRE units and between 0 and -5 IRE units. For such small signal amplitudes, the output vertical detail signal is coring, ie processed with substantially zero signal gain,
Undesired noise components are removed. Coring is done by the signal cancellation effect of the transfer characteristic for signals S1, S2 and S3 over region I. In the region I and above, the transfer characteristic for the signal S3 shows the amplitude limiting effect provided by the amplifier 17 of FIG. 1 operating in the amplitude limiting mode. Therefore, the amplifier 17 operates as a limiting amplifier.

Region II is between +5 and +40 IRE units and -5 and -40 IRE
It includes a medium amplitude vertical detail signal to and from the unit. For such a medium signal amplitude, the output vertical detail signal is 0
As described above, the processing is performed with a signal gain of 1, for example. However, in this region the vertical detail signal is amplified with a greater gain, for example a gain of 2 or 3, to provide an amplitude enhancement or peaking of the vertical detail signal in region II depending on the requirements of the particular device. Such amplitude peaking is undesirable for small signals in region I. This is because the peaking signal in region I contains unwanted amplified noise components. The response of the output signal amplitude over region II is determined primarily by the linear portion of the transfer characteristic associated with signals S1 and S2, and in part by the characteristic provided by the transfer characteristic associated with signal S3 in region II. To be done. The amplifier 15 acts as a limiting amplifier like the amplifier 17, and for regions II and above, i.e. 40 IRE units and above, the transfer characteristic of the signal S2 is that the amplitude limiting provided by the amplifier 15 operating in the amplitude limiting mode. Show the effect. The magnitude of the signal gain given to the vertical detail signal in region II is
Adjusted to suit by adjusting the signal processing parameters for the processing of the signal S2.

Region III contains large amplitude vertical detail signals with absolute values greater than +40 and -40 IRE units. The amplitude of such a large vertical detail signal is processed with a signal gain below 0, or a negative signal gain, to provide attenuation or pairing of the signal amplitudes in Region III. Attenuating such large vertical detail signals is desirable to prevent blooming of the replayed video image, thereby preventing distortion or obscuring of image details. In region III, amplifier 15 operates in amplitude limited mode with amplifiers 16 and 17.

Thus, in the vertical detail signal processing device, each output is connected to the connection point A.
It can be seen that it consists of three signal channels that are combined in. The first signal channel associated with signal S1 'constitutes a linear signal processing channel from the output of amplifier 12 to node A. The second signal channel associated with signal S2 'exhibits linear and non-linear regions (ie, amplitude limiting regions), from the output of amplifier 12 including amplifier 15, voltage dividers 42, 43 and inverter 53 to node A. It constitutes a signal path. This signal channel shows linear regions for the small-amplitude signal and the medium-amplitude signal in the regions I and II, respectively, and responds to the large-amplitude signal by the operation of the amplifier 15 in the amplitude-limiting mode, thereby increasing the large-amplitude in the region III. 3 shows a restricted area for the signal of. The third signal channel associated with signal S3 'also exhibits linear and non-linear (limited) regions and includes amplifier 17 and amplifier 12 including voltage dividers 60,62.
And a signal path from the output of to the connection point A. This signal channel shows a linear region for small amplitude signals in region I, and for medium and large amplitude signals in regions II and III, an amplifier responsive to these medium and large amplitude signals. The limit region is shown by the operation in 17 amplitude limit modes. The voltage amplifiers 42, 43 and the inverter 53 in the second channel and the third
The voltage dividers 60, 62 in the channels of FIG. 2 are of suitable large size so that the desired output signal is obtained at node A when the signals from the second and third channels are combined with the signal from the first channel. And a signal with polarity is applied to the connection point A.

As will be explained with reference to FIG. 4, the sampling circuits 50, 52 as well as the two sampling networks including the delay circuit 30.
When the processed vertical detail signals S1, S2, S3 are combined at the connection point A, these processed vertical detail signals S1, S2, S3
It operates as a signal transition delay equalization element for surely equalizing the signal transition delays indicated by S2 and S3. In particular, the signals S1, S2, S3 appearing at the connection point A are each subjected to two sampling operations with matched delays. Other features of the sampling networks 20, 22 and 24, 26 are described below.

Balance control voltage circuit 80 provides a variable DC balance control voltage to amplifiers 15 and 17 to balance or center the combined output transfer characteristic at node A with respect to vertical detail signal amplitude excursions. This adjustment is important in providing symmetric coring response in Region I, especially when low-level noise rejection is severe.

The non-linear vertical detail signal processor described above is capable of providing predictable combined output transfer characteristics over the entire band of vertical detail signals from DC to about 1 MHz, and is also a MOS charge coupled device with vertical detail signals derived. It has the advantage that it can be built on the same integrated circuit as the (CCD) comb filter. The predictability of transfer characteristics can be improved by using an amplifier having the same configuration and operating characteristics that can be easily realized on an integrated circuit. In addition to having the same gain, amplifiers 15, 16 and 17 preferably exhibit the same absolute peak-to-peak limiting amplitude level in amplitude limiting mode. Furthermore, the transfer characteristics, especially in the amplitude limited region, are primarily a function of the predictable gain of the amplifier and are substantially unaffected by the offset associated with the switching threshold and the amplifier switching threshold difference. Also, the signal conversion provided by the voltage divider resistive elements 42, 43 and 60, 62 is a function of the resistance ratio that can be accurately determined in the integrated circuit.

The sampling networks 20, 22 and 24, 26 have an effect on the signal distortion due to the switching transients associated with the timing signals used to time the charge transfer operation of the CCD comb filter from which the vertical detail signal is extracted. Acts to greatly reduce. These switching transients are, for the most part, inevitable and are guided by the ground line and a common integrated circuit board shared by the vertical detail signal processing circuit and the comb filter. In particular, the sampling networks 20, 22 and 24, 26 are amplifiers.
Prevents 15, 16 and 17 from exhibiting a saturation limit condition in response to such switching transients. Therefore, the sampling key signals 1 and 2 are
It is timed so that it occurs synchronously with the timing signal.

Generally, in devices that include timing periods where it is desired that switching transients from other signal sources be substantially absent, the sampling periods of 1 and 2 are the periods during which the signal sampling process corresponds to such timing periods. Well timed to be done. However, in some devices, there are no timing periods that are substantially free of such switching transients. In such a case, the synchronous sampling with signals 1 and 2 is a substantially constant switching transient sample from cycle to cycle, and thus, for example, a feedback circuit, as will be described below.
Produce a switching transient sample that represents a DC offset component that can be compensated by an all-negative feedback loop of the form 85, in each case without such synchronous sampling,
If the switching transient is large relative to the magnitude of the vertical detail signal to be amplified, the amplifier limits in response to the switching transient rather than in response to the vertical detail signal, thereby reducing the vertical detail signal. This would reduce the usable dynamic range of the amplifier.
This causes distortion associated with the signal transfer characteristics of the vertical detail signal processor, as well as distortion of the output vertical detail signal available from the amplifier.

The processing of the sampled data signal by the sampling networks 20, 22 and 24, 26 causes the amplifier through
The effects of signal amplitude distortion due to rate (maximum rate of change in the linear operating range) limits can be significantly reduced.
Such amplitude distortion tends to be generated by linear (ie, non-sampled signal) signal processing of high amplitude high frequency signals. In the device shown here, amplifier 17 is particularly prone to exhibit slew rate limited amplitude distortion. This is a relatively large amplitude where the signal is processed by amplifier 17,
That is, it is because it has been amplified in advance. Slew rate limited amplitude distortion significantly distorts the transfer function of the output signal and is particularly undesirable with respect to the desired coring response in region I.

For linear, non-sampled data signals undergoing amplification, slew rate limited distortion is represented by distortion of the rate of change of signal amplitude over a given period of time, and the form of amplitude swing of the output signal is the input signal. It does not follow the form of amplitude fluctuation of. In processing the sampled data signal provided by using the sampling circuitry 20, 22 and 24, 26, accurate signal amplitude sampling is performed during the sampling period. Obtained during each sampling period,
These amplitude samples that are held during the associated hold period are present at each time the signal is sampled,
It accurately represents the amplitude of the signal associated with a change in amplitude that is substantially free of distortion due to slew rate limiting effects.

The feedback network 85, as will be described in detail with reference to FIG.
Includes a differential comparator with the signal input provided at terminal T3. To the terminal T3, an output signal in a sampled form is supplied from an amplifier 17 through a sampling network composed of a keyed sampling switch 88 and a storage capacitance element 89 and an inverting amplifier 90. The reference voltage supplied to the reference input of the comparator via terminal T4 is taken from the low impedance reference voltage terminal of inverter 68 via NMOS coupling device 94. The output terminal T5 of the comparator is coupled to the input of the buffer 12 via a feedback path including a resistive element consisting of NMOS devices 96, 98 connected in series as shown in FIG. The output signal of the comparator is a filter / capacitor coupled to the return path.
Integrated by 99. The feedback network operates to stabilize the DC gain of the signal path containing amplifiers 14-17. This helps maintain the accuracy of the given coring characteristics for small vertical detail signals in region I.

The components of the feedback network 85 of FIG. 1 are shown in FIG. The NMOS devices 100 and 102 have their source electrodes connected to each other to form a differential comparator, a signal is supplied from a terminal T3 to the gate electrode of the device 100, and a reference voltage is supplied from a terminal T4 to the gate of the device 102. Supplied to the electrodes. The NMOS device 103 in the drain output circuit of the comparator device 100 provides the load impedance for the device 100. The output signal of the comparator is generated in the drain circuit of the device 100 and supplied to the feedback path via the terminal T5. The current sources for the comparator devices 100, 102 are in parallel NM in cooperation with the feedback reference current source 108 including the device 110.
It is configured by the OS devices 105 and 106. NMOS device 112
And the capacitance element 113 constitutes a loop stabilization filter for the feedback loop associated with the reference current source device 110 having the device 115 as a load impedance. The current conducted by the device 110 is also conducted by the current source devices 105, 106. NMOS device 116
Acts as a resistor to reduce the voltage gain of the feedback reference current source network 108, further ensuring the stability of the loop of the network 108.

The feedback circuit including network 85 exhibits two modes of operation. The circuit including the devices 100, 102 is particularly suitable in the absence of an input vertical detail signal and in the presence of a very small (coring region) input signal that is not large enough for the amplifiers 17 and 90 to perform limiting operation. It operates as a differential comparator to stabilize the DC gain of the signal amplification path.

The devices 100 and 102 of the comparator have the output through the terminal T3.
An amplifier 90 connected to acts as a fast current switch in the presence of a large amplitude signal indicative of amplitude limiting. In this example, the devices 100 and 102 symmetrically charge and discharge the integral capacitor 99 (FIG. 1) in the return path in response to a limited signal swing swing provided by amplifier 90 to terminal T3. Therefore, the output current is supplied via the terminal T5. In the current switching mode of operation, the charge developed across the integrating capacitor 99 remains substantially unchanged, thereby maintaining the bias level and DC gain set in the signal path for small signal conditions substantially unchanged. To be done. In this regard, it has been found that the vertical detail signal derived from the comb filtered chrominance output of a CCD comb filter exhibits a typical symmetrical amplitude characteristic of 50% duty cycle.

The feedback circuit, which includes network 85, also includes any DC that appears in the main vertical detail signal amplification path as a result of the sampling process.
Helps compensate for the offset.

FIG. 4 shows details of the delay compensation circuit of FIG. The input signal is provided to an input coupling circuit that includes NMOS devices 120 and 121, and is sampled by a circuit that includes a keyed sampling switch 125 and a storage capacitance element 126. The sampled signal is a voltage follower device 128 and a combiner circuit 1
It is transmitted to the second sampling circuits 135 and 136 via 30 and 131, and is coupled to the output from the sampling circuits 135 and 136 via the voltage follower device 138.

FIG. 5 shows the circuit configuration of the inverter (ie, amplifier) used in FIG. The input signal is a parallel connected signal inverting NMOS device 140, 141, 142 having a plurality of NMOS devices 143 to 146 connected in series as a common load network.
Is commonly supplied to the gate electrodes of. The output signal generated across the common load network is provided to the output via the voltage follower device 150.

FIG. 6 shows the construction of a non-linear vertical detail signal processor 160 corresponding to the apparatus of FIG. 1 and is associated with a CCD comb filter device such as that used in a color television receiver. The vertical detail processor 160 and the CCD comb filter are both constructed on the same integrated circuit within the dotted box.

The video signal containing the luminance and chrominance components from signal source 170 is passed through capacitor 172 and terminal T6 to the long line inputs 175, 176 of CCD comb filter device 173.
And the short line input of the same type filter device 177, 1
Supplied to 78 and. The video signal is inverted by inverter 180 before being applied to input 178. For the configuration and operation of the CCD comb filter device, refer to
Chard's U.S. Pat. No. 4,096,516, Carne
s) U.S. Pat. No. 4,217,605, issued May 28, 1982, entitled "CCD Charge Subtraction Arran.
Génété ”)
r) in U.S. Patent Application No. 383,302.

The signal combining node "+" of the comb filter combines the signals (charge packets) delayed by 1H, that is, one horizontal line period, to generate a comb filtered luminance signal on the comb filter 190. This is done by the additive charge combining process at the "+" node. The signal combining junctions "-" of the comb filter are inverted from each other and
The signals delayed by 1H are combined and a comb filtered chrominance signal is generated at the output of the comb filter 192 by a charge subtractive combining process. The comb filtered luminance and chrominance signals are sampled by sample and hold circuits 194 and 195, respectively, and the sampled shapes of the comb filtered luminance and chrominance signals appear at terminals T7 and T8, respectively. Comb filter
Timing signals for 173, sampling circuits 194, 195 and vertical detail processing circuit 160 are provided by signal source 198. The timing signal from the signal source 198 is generated in response to a timing reference signal, eg, a 10.7 MHz signal corresponding to a chrominance subcarrier reference signal frequency of 3.58 MHz (NTSC standard) multiplied by the frequency.

The comb filtered chrominance signal taken from terminal T8 is filtered by bandpass filter 200 to provide the chrominance signal in the chrominance frequency spectrum to the chrominance signal processing circuit. Filter 200 is NTSC as an example
It shows a frequency response of 3.58MHz ± 0.5MHz for chrominance signals. The signal generated at terminal T8 is also supplied to vertical detail signal processing circuit 160 via low pass (eg, 0 to 1 MHz) vertical detail filter 202 and terminal T1. Filter 202
Extracts from the comb filtered chrominance signal the low frequency luma signal vertical detail information that is lost from the comb filtered luminance signal. After processing by processing circuit 160, the non-linearly processed vertical detail signal appears at terminal T2, as described with respect to FIG.

The comb-filtered luminance signal taken out from terminal T7 is low-pass filtered by a filter 205 having a frequency response of 0 to 4 MHz corresponding to the luminance signal frequency spectrum. The signal combining network 208 includes a low pass (0-1 MHz) filter that removes the filtered luminance signal from the filter 205 and the harmonics generated by the non-linear signal processing.
A non-linearly processed (ie coring, peaking, pairing) vertical detail signal from 210 and a linear vertical detail signal component from the output of vertical detail filter 202 are provided. The latter signal is provided to the compositing network 208 in an amount sufficient to preserve the normal low level vertical resolution in the luminance component of the displayed video. In particular, the latter signal magnitude corresponds to the magnitude required to reproduce the small amplitude excursions of the vertical detail signal with respect to the luminance signal (ie the amplitude excursions of region I), and thus the final reconstruction. The resulting luminance signal exhibits an essentially flat amplitude response for small amplitude detail signals.
Thus, the output luminance signal provided to the luminance signal processing circuit from the synthesis network 208 relates to the non-linearly processed vertical detail component exhibiting peaking and pairing for medium and large amplitude swings, respectively, and the small amplitude swing. It has a reproduced flat amplitude characteristic.

[Brief description of drawings]

1 is a diagram showing a vertical detail signal processing device according to the principles of the present invention, part of which is in the form of a block, and the other part is in the form of a circuit diagram. FIG. 2 is obtained by the device of FIG. FIG. 3 shows the signal transfer characteristics, FIG. 3, FIG. 4 and FIG. 5 show the circuit of each part of the apparatus of FIG. 1 in detail, and FIG. 6 shows the separated luminance component and chrominance of the color television signal. FIG. 2 is a diagram showing the relationship between the comb filter for supplying components and the apparatus of FIG. 1. 10 ... Capacitor (input video signal source), 12 ... Amplifier (first signal channel), 30 ... Delay circuit (first signal channel), 32 ... Resistive element (first signal channel), 15 ... Amplifier (second signal channel), 28, 29 ... Resistive element (second signal channel), 42, 43 ... Resistive element (second signal channel), 17 ... Amplifier (second signal channel) 2 signal channels), 60, 62 ... Resistive element (second signal channel), A ... Synthetic video signal generating means.

Claims (2)

[Claims] 1. A signal source of an input video signal, a first signal channel for linearly transmitting the video signal, a first linear amplification region and a first limiting region with respect to the amplitude of the input video signal. Including a first limiting amplifier having
A second signal amplifier channel for transmitting the video signal; and a second limiting amplifier having a second linear amplification region and a second limiting region with respect to the amplitude of the input video signal.
A third signal channel for transmitting the video signal, the second linear amplification region and the second confinement region being the first linear amplification region and the first linear amplification region of the second signal channel. Different from the restricted area,
And the second limiting amplifier is arranged in cascade,
The second limiting amplifier is responsive to the output signal from the first limiting amplifier and further combines the output video signals of the first signal channel, the second signal channel and the third signal channel. , Within the same frequency range, small amplitudes within the first amplitude range of the input video signal are processed with a first gain substantially equal to zero, and within the first amplitude range of the input video signal are smaller than the first amplitude range. Amplitudes within the second amplitude range are processed with a second gain greater than the first gain and a third of the input video signal greater than the second amplitude range.
A video signal processing device having means for producing a synthesized video signal exhibiting such a characteristic that the amplitude within the amplitude range of is attenuated. 2. A signal source of an input video signal, a first signal channel for linearly transmitting the video signal, a first linear amplification region and a first limiting region with respect to the amplitude of the input video signal. Including a first limiting amplifier having
For transmitting a video signal including a second signal channel for transmitting the video signal and a second limiting amplifier having a second linear amplification region and a second limiting region with respect to the amplitude of the input video signal. And the second linear amplification region and the second restriction region are different from the first linear amplification region and the first restriction region of the second signal channel, respectively. , Combining the respective output video signals of the first signal channel, the second signal channel, and the third signal channel to obtain a small amplitude within the first amplitude range of the input video signal within the same frequency range. A second gain that is processed with a first gain substantially equal to zero and that has an amplitude in the second amplitude range of the input video signal that is greater than the first amplitude range is greater than the first gain. Treated with obtained, a third large the input video signal than the second amplitude range
Has a means for producing a synthesized video signal exhibiting a characteristic such that amplitudes within the amplitude range of the signal are attenuated, the second signal channel being a first keyed sample and hold coupled to the signal source. A first keyed sample and hold circuit for presenting a sampling state for obtaining an amplitude sample of the video signal during a first period and a hold state during a subsequent second period; Limiting amplifier is responsive to the output signal of the first keyed sample and hold circuit and the third signal channel is coupled to the output of the first limiting amplifier to a second keyed sample and hold circuit. The second keyed sample and hold circuit exhibits a hold state during a first period and an output signal from the first limiting amplifier during a second period. Exhibited sampling state for sampling, the second limiting amplifier responsive to the output signal from the second sample and hold circuit, a video signal processing apparatus.