JPH0695701B2 - Modulator / demodulator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a modulation / demodulation device (hereinafter referred to as a modem), and in particular, enables efficient terminal connection with a communication terminal device (hereinafter referred to as DTE). The present invention relates to an economical modem having a parallel data transfer function.

[Conventional technology]

As a conventional technique relating to a modem connected to a DTE, for example, “Nikkei Electronics, August 25, 1986”, No. 22
A technique described as "1200-bit / sec modem CMOS LSI having a built-in interface with a microprocessor and a telephone line" is known from page 7 to page 237.

A conventional modem will be described below with reference to the drawings.

FIG. 15 is a block diagram showing the configuration of a conventional modem, and FIG. 16 is a block diagram showing the usage of a conventional modem. 15 and 16, 1 is a modem,
2 is control means, 3 is modulation means, 4 is demodulation means, and 10 is DT
E and 11 are microcomputers (hereinafter referred to as MPU), and 12 is a serial interface circuit (hereinafter referred to as S-I / F).

As shown in FIG. 15, a modem 1 according to the prior art comprises a control means 2, a modulation means 3 and a demodulation means 4, a microcomputer bus interface (hereinafter referred to as MPU-1 / F) and serial data. Interface (hereinafter V.24-I / F
And analog interface (hereinafter AI-F)
It is configured to enable parallel data transfer and serial data transfer. FIG. 16 shows the overall configuration when the modem thus configured is used by being connected to the DTE 10. That is, the DTE10 is composed of the MPU11 and S-1 / F12, and the DTE10 and the modem 1 are MP
U-I / F and V.24-I / F are connected to each other.

In such a configuration, when data is serially transferred between the DTE 10 and the modem 1, the MPU 11 sends the transmission speed and training format to the modem 1 through the MPU-I / F before starting the operation of the modem 1. It controls the actual data transfer to be performed serially via V.24-I / F.

When data is transferred between the DTE10 and the modem 1 in an ordinary manner, the V.24I / F is not used and the MPU-I / F interrupt function (INT pin in Fig. 15) is used. Synchronize, MPU11
Performs data transfer in parallel by the software.
The A-I / F of the modem 1 is an interface with the communication line.

[Problems to be solved by the invention]

In the conventional technology, an interrupt terminal for parallel data transfer at the time of serial data transfer, a terminal for serial data transfer at the time of parallel data transfer is not used, the utilization efficiency of the terminal is poor, for example,
When a modem as shown in Fig. 15 is formed on a single chip semiconductor, the chip may be an IC chip with many terminals, or a large package with many terminals must be used. Therefore, it has a problem that it is not economical. In addition, the above-mentioned conventional technique, in parallel data transfer,
Since the software processing by MPU is used, when the modem speed is high, there is a problem that the processing throughput as a DTE terminal is reduced.

SUMMARY OF THE INVENTION It is an object of the invention to solve the above-mentioned problems of the prior art and to provide a modem having efficient hardware and software means.

[Means for solving problems]

According to the present invention, in addition to the control means, the modulation means, the demodulation means, the AI / F, and the MPU-I / F, the purpose is to provide a serial data interface and a parallel data reference timing interface (hereinafter referred to as V.24). -I / F / P-I / F-T), serial / parallel conversion means connected to MPU-I / F and modulation / demodulation means, and means for controlling the combined use of the interface in the modem. It is achieved by providing. Further, in the case of the half-duplex high speed modem, a means for additionally using the serial / parallel conversion means originally provided in the modem unit of the modem as the serial / parallel conversion means for parallel data transfer with the DTE. It is achieved by providing.

Of course, if economically permitted, the half-duplex modem may have the same configuration as the full-duplex modem.

[Action]

The serial-parallel conversion circuit receives the parallel data output from the DTE in parallel from the modem's original microcomputer bus, converts it to serial data, and inputs this to the modem's original modulator, and vice versa. , Receives the received data from the demodulator as a serial signal, and supplies this as parallel data to the DTE from the microcomputer bus. At this time, the transfer timing of this parallel data is input / output from the terminal for serial data transfer which the modem originally has. Therefore, it becomes possible to use one terminal for both the terminal for serial data transfer and the timing signal terminal for parallel data transfer of the modem. Also,
In the case of a half-duplex high speed modem, the serial / parallel conversion means originally possessed by the modem unit of the modem can be used also as the data transfer means with the DTE. Further, in the present invention, the data transfer request signal can be controlled by the data transfer preparation completion signal.

〔Example〕

An embodiment of a modem according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram functionally expressing one embodiment of the present invention, FIG. 2 is a block diagram showing an outline of one embodiment of the present invention, and FIG. 3 is a SP-I / F of FIG. FIG. 4 is a block diagram showing the details, FIG. 4 is a timing chart for explaining the operation at the time of serial data transfer in FIG. 3, FIG. 5 is a block diagram showing the configuration at the time of transmission operation in FIG. 3, and FIG.
FIG. 7 is a timing chart for explaining the transmission operation in FIG. 7, FIG. 7 is a block diagram showing the configuration at the time of reception operation in FIG. 3, and FIG. 8 is a timing chart for explaining the reception operation in FIG. In FIGS. 1 and 2, 5 and 6 are serial-parallel conversion means, 7 to 9 are switching switches, 20 is a digital signal processing processor (hereinafter referred to as DSP), 30 is an analog signal processing processor (hereinafter referred to as ASP), 40. Is a sample timer, 50 is a serial-parallel interface (SP-
I / F) and other symbols are the same as those in FIGS. 15 and 16.

One embodiment of the modem according to the present invention is, as shown in FIG. 1, a control means 2, a modulation means 3, a demodulation means 4 and an A-I / F for controlling the connection between a communication line, MPU-I / F and V.24-I / F / P-I / F-T connecting between DTE and MPU-I / F
And serial / parallel conversion means connected to the modulation / demodulation means 3 and 4
5, 6 and the changeover switches 7 to 9 for sharing the interface V.24-I / F / P-I / F-T.
In order to perform the above-described functions of the one embodiment of the present invention, the modem 1 of the one embodiment of the present invention, as shown in FIG.
Supports serial data transfer and parallel data transfer function between DTE and 0, ASP30 that performs signal conversion between digital signal and analog signal, sample timer 40 that generates processing timing signal of analog signal in ASP30 To do. Composed of SP-I / F50 and most of modem functions such as modulation, demodulation and sequence control
It is realized by the program.

When the modem 1 shown in FIG. 2 performs a transmission operation, a DTE (not shown) gives an operating condition to the modem 1 via the MPU-I / F prior to transmission, and if the modem 1 starts the operation,
Input data in series or in parallel via SP-I / F50. The DSP 20 modulates the data from the DTE and gives the processing result to the ASP 30. The ASP 30 transmits data to the communication line via the A-I / F based on the transmission timing signal Tst generated by the sample timer 40.

In the case of the reception operation of the modem 1, the modem 1 starts the operation after receiving the operation condition from the DTE as in the case of the transmission operation. In this case, the ASP 30 receives the data from the A / I / F by the reception timing signal Rst issued by the sample timer 40, converts the received analog signal into a digital signal, and then transfers the digital signal to the DSP 20. DSP20 is
After demodulating this digital signal, it is transferred to the DTE in series or in parallel via the SP-I / F50.

When the modem 1 performs the full-duplex operation, the above-mentioned transmission and reception operations are executed in parallel.

Fig. 3 shows the detailed configuration of the SP-I / F50 in Fig. 2. The SP-I / F50 is a serial-to-parallel conversion circuit (hereinafter referred to as S / P) 51, 52 and a parallel-to-serial conversion. Circuit (hereinafter referred to as P / S)
53,54, variable frequency division counter (hereinafter referred to as CT) 55,56,
1/8 division counter (hereinafter referred to as 1/8 CT) 57,58 and 2
Minute division counter (hereinafter referred to as 1 / 2CT) 59, 60, latches 61 to 63, and 1-bit shift register (hereinafter referred to as SR)
64, 65, an AND circuit (hereinafter referred to as AND) 66, 67, an inverting circuit (hereinafter referred to as INV) 68, and a switching switch (hereinafter referred to as SW) 70 to 73 are connected as shown in the figure. .
SW70 to 73 in FIG. 3 are shown as a state during parallel data transfer, and when the contacts are reversed, the serial data transfer mode is set.

In the serial data transfer mode, a signal as shown in FIG. 4 is applied to each input / output terminal of the modem 1 shown in FIG.
First, the DTE on the transmission side gives a transmission request signal () to the modem 1 via the MPU-I / F. When the modem 1 receives this, it sends a training signal and then a transmission enable signal ▲
Output ▼ to notify the DTE that transmission data can be input. The transmission timing signal TXT is generated by the CT55, sent to the DTE via the switch 71, and given to the SR64 via the SP51 and INV68, so the transmission data that changes at the falling edge of the transmission timing signal TXT. If TXD is input from DTE, transmission data TXD will be S / P
It is input to 51 and converted into parallel data. The DSP 20 counts the number of parallel bits by the program, and when it reaches a fixed number, reads the contents of the S / P 51 via the DSP-BUS to obtain the transmission data required for modulation.
This parallel data is modulated by DSP20, ASP30, A-
Via the I / F, an analog signal shown as a modulated wave in FIG. 4 is sent to the transmission line and received by the modem of the receiving side system.

The modem 1 shown in FIG. 2 and FIG. 3 uses the A-I / F to
If an analog signal is received, the received data is given to the DSP 20 and demodulated via the ASP 30, but first, the DSP 20
Received signal detection signal notifying that the modulated wave is received ▲
▼ is output to the DTE via the MPU-I / F, and the training signal from the DTE is received. When the DSP 20 finishes the training, it receives the carrier detection signal via the latch 62.
▼ is output and the demodulated received data is sent to DSP-B
It is sent to DTE in series via US, P / S54, SR65, and SW73.
The reception timing signal RXT for this operation is generated by the CT 56, distributed to the internal circuit, and also output to the DTE via the SW 72.

When data is transferred in parallel between the DTE and the modem,
Each SW71-73 shown in FIG. 3 is in the position of the figure. And
In the transmission operation in this case, the circuit in the modem 1 is connected as shown in FIG. 5 and operates at the timing shown in FIG. The reference numerals in FIG. 5 are the same as those in FIG.

Before the transmission, the MTE-I / F gives the modem 1 an operating condition that should be given to the latch 62 shown in FIG.
A training signal is transmitted by turning on a transmission request signal (not shown). After receiving the transmission request signal ▲ ▼ and the training signal from the DTE, the modem 1 sends out the transmission enable signal CTS to the DTE in the same manner as in the case described above and starts the operation. In the modem 1, the DTE of this transmission enable signal ▲ ▼
Is reset, the reset of 1 / 8CT57 and 1 / 2CT59 is released, and first, 1 / 8CT57 counts the transmission timing signal TXT. When 1/8 CT57 counts 8 TXTs, 1/2 CT59 operates,
Its output is the parallel data transfer request signal DR-T, and DT
Sent to E. DTE is the parallel data transmission request signal DR-
When T is received, the reference display signal ▲ ▼ for accessing the write latch 61 of the transmission data and the modem 1
The read / write timing signal R / of the MPU is given to the modem 1 to write 8-bit transmission data in parallel to the latch 61 from the MPU-I / F. The parallel data transfer request signal DR-T is reset by the fall of the reference display signal () or the L level. When the 1/8 CT57 counts eight more transmission timing signals TXT, a carry-out signal CO is output, and at the same time the DTE is requested to transfer the next 8-bit data, the latch 61 sends the previous transmission data to the P / S53. Transferred. Since the transmission timing signal TXT is supplied to the P / S53, S / P51 and SR64, the transmission data in the P / S53 is
According to the transmission timing signal TXT, it is serially supplied to the S / P 51 and again converted into parallel data and transferred to the DSP 20 for modulation. In this way, the reason for converting the transmission data from parallel to serial at P / S53 and then converting it to parallel data again at S / P51 is that the MPU-I / F between the DTE and the modem 1 has an average width of 8 bits. This is because the number of bits required for each modulation by the high-speed modem is 1,2,3,4 bits, which varies depending on the speed and the modulation method of the modem, whereas the example is data transfer processing. Sixth
In the figure, TXD 'indicates the contents of the input side register in the S / P 51. Then, as shown in FIG. 6, the modem 1 requests parallel data transfer to the DTE by the first carry-out signal CO from the 1/8 CT57, and the second carry-out signal CO requests the P / S53 and S / S53. Serial data transfer is started between / P51, and data is input to S / P51 which DSP20 can fetch. The DSP 20 has a function of predetermining the timing of outputting the transmission enable signal ▲ ▼ in accordance with the timing of ending the training.

When the modem 1 transmits data via the transmission line and transfers this received data in parallel to the DTE, the SP-I / F50 is connected as shown in FIG. 7 and at the timing shown in FIG. Operates accordingly. The reference numerals in FIG. 7 are the same as those in FIG.

When the modem 1 receives the analog signal, the DSP 20 notifies the DTE of the reception of the modulated wave, as described with reference to FIG. The DTE gives operating conditions to the modem 1 via the MPU-I / F such as outputting the reception mode (PR) by parallel data transfer to the latch 62 shown in FIG.
Receiving state. The modem 1 receives the actual signal via the A-I / F, and after finishing the training, starts data transfer to the DTE. First, the DSP 20 turns on the reception carrier detection signal ▲ ▼ and simultaneously writes the reception data of a plurality of bits to the P / S 54 via the DSP-BUS. Since the reception timing signal RXT is supplied to the P / S54, S / P52, and SR65 that connects them, the reception data set in the P / S54 is once converted to serial data RXD and sent to the S / P52. And again converted into parallel data here. Since 1 / 8CT58 and 1 / 2CT60 start counting the reception timing signal RXT at the same time when the reception carrier detection signal ▲ ▼ turns ON, if 8 bits of reception data RXD is accumulated in S / P52,
1/8 CT58 outputs the carry-out signal CO. The carry-out signal CO transfers the 8-bit received data in the S / P 52 to the latch 63 and simultaneously drives 1 / 2CT60 to output the data transfer request signal DR-R to the DTE. When the DTE detects this data transfer request signal DR-R, it accesses the latch 63 through the MPU-I / F and reads the contents in parallel, as in the case of the transmission operation. Data transfer request signal
The DR-R is reset by the fall of the reference display signal {circle over (5)} or the L level for accessing the read latch 63 of the received data.

According to the embodiment of the present invention described above, the terminal used for serial data transfer between the modem and the DTE is also used as the terminal for the timing signal at the time of parallel data transfer, thus improving the utilization efficiency of the terminal. At the same time, just by switching to the parallel data transfer mode before starting the operation of the modem, the DSP can perform parallel transfer with software processing that is almost the same as in the case of normal serial data transfer, and a small internal A modem with well-balanced hardware and software can be realized only by adding a circuit and a switching means.

FIG. 9 is a block diagram showing the structure of the SP-I / F according to another embodiment of the present invention. This block diagram is an SP-I / F applied to a half-duplex high-speed modem. 75-76 in the figure
Is a switching switch, and other symbols are the same as those in FIG.

In general, a high-speed modem adopts a system in which its modulation is discrete and a plurality of data are modulated per signal point, and a plurality of bits are transmitted in parallel, and a serial / parallel conversion means is provided. The embodiment of the present invention shown in FIG. 9 takes advantage of the fact that in such a modem, the serial-parallel converting means on the receiving side is not used at the time of transmission and the serial-parallel converting means on the transmitting side is not used at the time of reception. The serial / parallel conversion means that the modem originally has for transmitting / receiving data to / from the transmission line can also be used as the serial / parallel conversion means for interfacing with the DTE. In other respects, the same as in the case of FIG. Is composed of. In addition, since the terminal and the internal configuration can be switched between the serial data transfer and the parallel data transfer based on the switching signal P and the transmission / reception switching signal PT, the usage efficiency of the terminal can be further improved and the circuit configuration can be economical. Can be one.

FIG. 10 is a block diagram showing the configuration of the SP-I / F applied to a half-duplex high speed modem, which is still another embodiment of the present invention. In FIG. 10, 80 and 81 are parallel in-out shift registers, 82 is a bit counter, 83 is 1 / 8CT, and 84 is 1
/ 2CT, 85 and 86 are AND circuits, and 87 to 89 are switching switches.
Also in the case of this embodiment, the structure is the same as that of FIG. 3 except that it is half-duplexed, and it is possible to effectively use the terminals and the internal circuit, which is economical. is there.

FIG. 11 is a block diagram showing still another embodiment of the present invention. The embodiment shown in FIG. 11 is different from the embodiment shown in FIG. 3 in that an edge detection circuit 90 and an OR circuit 91 are added, but in other respects it is constructed similarly to the case shown in FIG. ing. The operation of this embodiment will be described below with reference to the time chart of FIG.

When the training is completed, the modem 1 sends a data transfer enable signal ▲ ▼ from the latch 62 to the DTE. The data transfer enable signal is also given to the edge detection circuit 90 in the modem 1 and its falling edge. To be detected. Edge detection circuit
This detection signal Y of 90 drives 1 / 2CT59, whereby the parallel data transmission request signal DR-T is sent to the DTE. DTE
When the parallel data is transmitted in response to the parallel data transmission request signal DR-T, the parallel data is transmitted by the reference display signal ▲ ▼ for accessing the write latch of the transmission data as in the case described with reference to FIG. The transfer request signal DR-T is reset. And data transfer enable signal ▲ ▼
1/8 CT57 sets the transmission timing signal TXT to 8 after enabling
When counting the number, the 1/8 CT57 outputs a carry-out signal CO and requests the next data transfer.

According to this embodiment, as compared with the embodiments described with reference to FIGS. 5 and 6, the timing at which the DTE transfers data can be advanced, and the processing start timing inside the DSP 20 can be advanced. There is a merit.

FIG. 13 is a block diagram showing still another embodiment of the present invention, which is a circuit diagram in which the timing of the first DMA request and the serial transfer in the parallel transfer mode are improved.
In FIG. 13, 100 is an 8-bit latch, 101 is a P / S, and 102.
Is 1/8 CT, 103 and 104 are flip-flops, 105 to 107 are IN
V and 108 are NOR circuits, 109 is an OR circuit, and 110 and 111 are AND circuits. The operation of this embodiment will be described below with reference to the time chart shown in FIG.

In this embodiment, in executing the signal processing, the modem controls the data transfer enable signal ▲ ▼ to fall and send to the DTE two symbol intervals before the timing when data is actually needed. . Then, the fall of the data transfer enable signal is performed after the fall of the baud timing signal SBT. In this way, when the data transfer enable signal ▲ ▼ is at the "H" level, the output of the flip-flop 104 is at the "H" level. Therefore, when the data transfer enable signal ▲ ▼ falls, The output rises, whereby the DMA data transfer request signal DRQ is sent to the DTE. The DTE receives the fact that the DMA data transfer request signal DRQ has reached the “H” level,
Using the signal as a timing signal, the transmission data is transferred to the 8-bit latch 100 in parallel and written. With this write timing signal ▲ ▼, the flip-flop
103 is reset and DMA data transfer request signal DRQ is "1".
It is a level. At this time, since the 1/8 CT102 is connected to the Q output of the flip-flop 104, it is in the reset state and does not operate. When the next baud timing signal ▲ ▼ rises to "H" level, the output of the AND circuit 110 becomes "H" level, and the output of the NOR circuit 108 stays at "L" level while the baud timing signal ▲ ▼ is at "H" level. "Because it is a level, the contents of the latch 100 are transferred to the P / S 101.
When this baud timing signal ∇ falls and becomes "L" level, the flip-flop Q output changes to "H" level and the output changes to L level. Therefore, the 1 / 8C102 becomes operable, and the AND circuits 110 and 111 enable the data transmission enable signal ▲ ▼ and the baud timing signal ▲.
The restart of the DMA data transfer request signal DRQ by ▼ does not occur thereafter, and the data transfer from the latch 100 to the P / S 101 does not occur.

Such an embodiment of the present invention has the effect that the data transfer from the first P / S 101 can be synchronized with the timing of the baud timing signal (). That is, in this embodiment, the operation of the flip flip 104 causes the DMA
The effect is that the initial start of transfer and the baud timing of the modem can be synchronized.

〔The invention's effect〕

As described above, according to the present invention, it becomes possible to use both the terminal for serial data transfer and the terminal for timing signal for parallel data transfer in the conventional modem, thereby improving the utilization rate of the terminal. It is possible to realize an economical circuit configuration, and since serial / parallel conversion means of a conventional modem is used for parallelizing data, an economical circuit configuration can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram functionally expressing one embodiment of the present invention, FIG. 2 is a block diagram showing an outline of one embodiment of the present invention, and FIG. 3 is a SP-I / F of FIG. FIG. 4 is a block diagram showing the details, FIG. 4 is a timing chart for explaining the operation at the time of serial data transfer in FIG. 3, FIG. 5 is a block diagram showing the constitution at the time of the transmitting operation in FIG. 3, and FIG.
FIG. 7 is a timing chart for explaining the transmission operation in FIG. 7, FIG. 7 is a block diagram showing the configuration at the time of reception operation in FIG. 3, and FIG. 8 is a timing chart for explaining the reception operation in FIG. 7, FIGS. FIG. 11, FIG. 11 and FIG. 13 are block diagrams showing the structure of another embodiment of the present invention, FIG. 12 and FIG.
FIG. 14 is a timing chart for explaining the operation of FIGS. 11 and 13, respectively. FIG. 15 is a block diagram showing the structure of a modem according to the prior art, and FIG. 16 is a description of how to use the modem of FIG. It is a block diagram. 1 ... modem, 2 ... control means, 3 ... modulation means, 4 ...
... Demodulation means, 5, 6 ... serial-parallel conversion means, 7-9 ... switching switches, 10 ... communication terminal equipment (DTE), 11 ... microcomputer (MPU), 12 ... serial interface (SI) /
F), 20 ... Digital signal processing processor (DSP), 30
…… Analog signal processing processor (ASP), 40 …… Sample timer, 50 …… Serial-parallel interface (SP-I /
F).

Claims (5)

[Claims] 1. A modulation / demodulation device comprising a modulation means, a demodulation means, a control means, an analog signal interface connected to a transmission line, and a microcomputer bus interface and a serial data interface connected to a communication terminal device. In the above, the microcomputer bus interface, the modulation means, and the serial-parallel conversion means connected to the demodulation means are provided,
A modulator / demodulator characterized in that a terminal for a reference timing signal of the serial-parallel conversion means through a microcomputer bus interface is also used as a terminal of the serial data interface. 2. A modulator / demodulator according to claim 1, wherein one terminal is shared by the serial data timing signal and the parallel data timing signal. 3. A serial-parallel conversion circuit provided inside the modulation means and the demodulation means, and a serial-parallel conversion means connected to the microcomputer bus interface, the modulation means, and the demodulation means. The modulation / demodulation device according to claim 1. 4. A modulator / demodulator according to claim 1, wherein the timing of data transfer start for parallel data transfer and serial data transfer is instructed using the same timing signal. 5. A modulator / demodulator according to claim 1, wherein the parallel bit number counter is provided only in the serial / parallel conversion means on the side of the microcomputer bus interface.