JPH0691469B2 - Decoder circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a decoder circuit that decodes a plurality of input signals and outputs the results.

[Conventional technology]

Semiconductor products, especially microcomputers, decode instruction codes, decode internal microprograms,
In many cases, a plurality of decoder circuits are built in the chip to perform address decoding of internal hardware.

A conventional decoder circuit will be described below with reference to FIG.

FIG. 3 shows a conventional decoder circuit, and the decoder circuit 110 is
Input signal lines 101 to 103 for inputting signals to be decoded and inverters 151 to 153 for inverting the values of the input signal lines 101 to 103
And the NAND gates 300, 310 ... 370 that output the output signals based on the signals input to the input signal lines 101 to 103, and the inverters 400,410 ... for making the values of the NAND gates 300,310 ... 370 positive logic. 470, output signal lines 500/510 for controlling the controlled object, 570, and power supply lines for each circuit (hereinafter Vdd
600).

Next, the actual operation of the decoder circuit 110
A case will be described in which the input signal lines 101 to 103 to are 011.

If the input signal lines 101 to 103 are '011', the inverter
The output value of 151-153 is '100'. Therefore, of the NAND gates 300, 310, ... 370, only the output of the NAND gate 330 becomes "0", and the other NAND gates 300, 310, 320, 340.
The output of 350/360/370 is "1". Therefore, of the output signal lines 500, 510, ... 570, only the output signal line 530 has the logical value "1", and the other output signal lines 500, 510, 52.
0, 540/550/560/570 will be "0". Output signal line 530
Is a control signal for controlling other hardware.

The decoder circuit operates in the same manner even when the input signals 101 to 103 take other values, and is in a one-to-one relationship with eight possible input signal lines 101 to 103 from “000” to “111”. As a result, the output signal lines 500, 510, ... 570 have a logical value of "1".

Next, the connection between the input signal line 101 and the NAND gate 370 is shown in A of the figure.
Due to factors such as disconnection, failure, or connection mistakes at
A case where the Vdd line 600 is connected will be described.

In the NAND gate 370, one of the input signal lines is connected to Vdd, so the value of the input signal lines 101 to 103 is '11.
The output value of the NAND gate 370 becomes "0" and the output signal line 570 becomes "1" when the input signal lines 101 to 103 are also "011" except when it becomes "1".

Therefore, for the input signal lines 101 to 103, the output signal lines 500 and 510
...... 570 does not have a one-to-one relationship. That is, when the input signal lines 101 to 103 are “011”, the output signal lines 530 and 570 are “1” at the same time.

In this case, the output that is originally correct as the output of the decoder circuit 110 is that the output signal line 530 is “1” and the output signal line 530 is “1”, so that the control target controlled by the output signal line 530 is , Works fine.

However, since the output signal line 570 is also "1", the control target controlled by the output signal line 570 also operates, and the originally intended operation normally operates, but causes a malfunction in other parts. For example, when the decoder circuit is an address decoder or the like, the register originally addressed by the output signal line 530 is accessed, but the register addressed by the output signal line 570 is simultaneously accessed. Occurs.

In order to find such a failure, it is necessary to check all the parts other than the part to be operated by the circuit simulation or the function check such as the test pattern, and it is extremely difficult to perform the simulation or the test pattern with a finite number of patterns. It is a malfunction that is hard to find.

[Problems to be solved by the invention]

A conventional decoder circuit finds a failure by circuit check simulation or test pattern even if a failure occurs in the input signal and the output signal is output by decoding a value other than the original value to be decoded in addition to the original decoding. There is a problem that it is difficult to do.

An object of the present invention is to provide a decoder circuit that can easily realize fault detection by having a signal indicating that an abnormality has been detected when the output value of the decoder becomes two or more "1".

[Means for solving problems]

A decoder circuit of the present invention includes a decoder circuit that has a plurality of output signals and outputs a single output signal in response to an input signal; a plurality of transistors that conduct a gradon level by the output of the decoder circuit; A reference circuit having impedance lower than that of a single transistor among the plurality of transistors being in a conducting state and having a higher impedance than that of a plurality of transistors being in a conducting state, and parallel connection of the plurality of transistors and the reference circuit A sense amplifier that performs impedance comparison, compares the impedance of a circuit in which the plurality of transistors are connected in parallel with the reference circuit, and outputs a comparison signal to detect an abnormality in the output of the decoder. It is equipped with.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

First, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows an embodiment of the present invention in which a decoder circuit 100 is
Input signal lines 101 to 103 for inputting signals to be decoded and inverters 151 to 153 for inverting the values of the input signal lines 101 to 103
And the NAND gates 300, 310 ... 370 that output the output signals based on the signals input to the input signal lines 101 to 103, and the inverters 400,410 ... for making the values of the NAND gates 300,310 ... 370 positive logic. … 470 and inverter 400 ・ 410 …… 470
N-channel transistor (hereinafter referred to as NCH-TR) 405/415 ... 475 that turns on when the output of the N1 becomes "1", test signal line 490 connected to 475, NCH-TR800 to 807, and NCH-TR800 to 80
A reference signal line 890 connected to 7 and a known current sense amplifier (hereinafter referred to as a sense amplifier) for detecting the current flowing in the test signal line 490 and the reference signal line 890 (see, for example, JP-A-60-70591). 700, an output signal line (hereinafter referred to as a detection signal) 900 of the sense amplifier 700, a power supply line (hereinafter referred to as a Vdd line) 600 of each circuit, and a ground line (hereinafter referred to as a Gnd line) 650.

Next, the hardware of each unit will be described.

The NAND gates 300 to 307 decode the values of the input signal lines 100 to 103, and only one NAND gate corresponding to the decoded value of the input signal lines 101 to 103 becomes “0”. Output signal line 500
・ 510 …… 570 outputs the inverted value of the output value of NAND gate 300 ・ 310 …… 370.

NCH-TR405 is ON if the output value of inverter 400 is "1".
The source input is connected to the Gnd line 650, and the drain terminal is connected to the test signal line 490. NCH-TR415 / 425
…… 475 is also the same. In the NCH-TR800, the source input terminal is connected to the Gnd line 650, the gate input is always “1”, and the drain output is connected to the reference signal line 890.

The NCH-TR800 is a transistor whose impedance is lower than the state in which any one transistor of NCH-TR405.425 ... 475 is turned on and whose impedance is higher than the state in which two or more transistors are turned on.

NCH-TRs 801 to 807 are N-channel transistors similar to the NCH-TR, the gate input is always in the off state at "0", and the drain output is connected to the reference signal line 890. The total sum of the capacities of the NCH-TR801 to 807 on the reference signal line 890 side is the same as that of the test signal line 490 so that the relationship related to the charging and discharging of the additional capacitance of the reference signal line 890 is the same as that of the test signal line 490. It has a value equal to the sum of the capacitances on the test signal line 490 side when any 7 transistors in the above are off.

The current sense amplifier 700 detects a difference between currents flowing in proportion to the impedances of the test signal line 490 and the reference signal line 890. If the reference signal line 890 has a lower impedance than the test signal line 490, the detection signal line 900 is detected. Is set to “0” and the test signal line 490 is the reference signal line 890
If the impedance is lower than that, the detection signal 900 is set to "1".

Next, the actual operation of the decoder circuit 100 will be described.

The decoder circuit 100 decodes the values of the input signal lines 100 to 103 and outputs the decoding result to the output signal lines 500, 510, ... 570.

Now, a case where "011" is input to the input signal lines 101 to 103 will be described. When '011' is input to the input signal lines 101 to 103, only the output value of the output signal line 530 becomes "1", and the output of the other output signal lines 500/510/520, 540/550/560/570 is It becomes "0". Also, the NCH-TR405 / 415 ... 475 connected to the test signal line 490 is turned on only by the NCH-TR435, and the other NCH-TR405 / 415/425, 445/455/465/475.
Is turned off. Therefore, the test signal line 490 is
Connect with Gnd line 650 via TR435, NCH-TR405 / 415/42
5, 445/455/465/475 has additional capacitance equivalent to the gate capacitance in the off state.

The reference signal line 890 is a transistor NCH-TR8 whose impedance is lower than when the NCH-TR435 is on.
It is connected to the Gnd line 650 via 00, and the test signal line
It has a capacity equivalent to the additional capacity of 490. Therefore, in the test signal line 490 and the reference signal line 890, the reference signal line 890 has a lower impedance, and the detection signal 900 output from the sense amplifier 700 is “0”.

Subsequently, the connection between the input signal line 101 and the NAND gate 370 is the first.
A case where the connection is made to the Vdd wire 600 due to a cause such as a disconnection, a failure, or a connection error in the portion A of the drawing will be described. In the NAND gate 370, one of the input signal lines is Vdd
The input signal lines 101-103 are '011' except when the values of the input signals 101-103 are '111' because they have been connected to the line.
Also at this time, the output value of the NAND gate 370 becomes "0". Therefore, when the input signals 101 to 103 are '011', the output signal 53
0 · 570 becomes “1” at the same time. At this time, NCH-TR435 / 475
Test signal line 490 is connected to NCH-TR43
It is connected to the Gnd line 650 through a parallel connection of 5 and 475.

That is, the impedance of the test signal line 490 is the above-mentioned NCH-
The impedance is lower than when one of the TR405, 415, and 475 is in the ON state. Therefore, the impedance of the test signal line 490 becomes lower than the impedance of the reference signal line 890, and the sense amplifier 700 sets the detection signal 900 to “1”.

By monitoring the detection signal 900, it is possible to realize a decoder circuit that can easily detect a failure of the input signal, disconnection, connection error, and the like.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 2 shows an embodiment of the present invention, in which the decoder circuit 200 is
N-channel transistors NCH-TR201-224 for decoding for decoding the input signal lines 104-103, precharge transistors PCH-TR251-258, N-channel transistors NCH-TR261-268 for discharging,
Input signal lines 101 to 103 for inputting signals to be decoded and inverters 151 to 153 for inverting the values of the input signal lines 101 to 103
And inverter 400/410 …… 470 and the gate input is “1”
NCH-TR405 ・ 415 …… 475 which turns on when it becomes, output signal lines 500 ・ 510 …… 570 controlling the controlled object, and NCH-TR405
・ 415 …… Test signal line 490 connected to 475 and NCH-TR80
0 to 807, reference signal line 890 connected to NCH-TR800 to 870, test signal line 490, and reference signal line 890
A current sense amplifier (hereinafter referred to as a sense amplifier) 700 for detecting a current flowing through the output line, an output signal line detection signal line 900 of the sense amplifier 700, a clock signal C1, and a Vdd line 600.

Next, the hardware of each part will be described. The input signal lines 101 to 103, which have already been described in the first embodiment, and the inverter
151-153, inverter 400/410 …… 470, NCH-TR40
5 ・ 415 …… 475 and output signal line 500 ・ 510 …… 570 and NCH
A description of -TR 800 to 807, test signal line 490, reference signal line 890, sense amplifier 700, and output signal line 900 will be omitted.

The signal lines input to the inverters 400-470 are PCH-TR251-
It is precharged by 258 for the period of C1 and its logical value becomes "1". Next, during the period of ▲ ▼, discharge operation is performed by NCH-TR260 to 268, and input signal lines 101 to 103
NCH-TR201 to 224 are turned on or off according to the value of N and all N on the signal line input to the inverter 400 ・ 410 …… 470
Only the signal line for which CH-TR is in the ON state becomes "0", and the inverter output becomes "1". If the input signal lines 101 to 103 to the decoder circuit 200 are '011', the clock ▲
Output signal line 500/510 after discharge by ▼
The output signal line 530 is the only logical value "1" in the value of 570, and the other output signal lines 500/510/520/540 ... 570
Becomes "0".

Here, when NCH-TR222 does not exist, or NC
If the H-TR222 is always on, the input signal of the inverter 470 is 0 when the value of the input signal lines 101 to 103 is 0.
Both 11 'and' 111 'are discharged during the clock ▲ ▼ period, so the output signal line 570 becomes “1”.

In the following, by a method similar to that described in the first embodiment, the decoder circuit failure is detected by comparing the impedances of the test signal line 490 and the reference signal line 890, and the detection signal line 900 is set to "1" when abnormal. To

By monitoring the detection signal 900, it is possible to realize a decoder circuit that can easily detect a failure of the input signal, disconnection, connection error, and the like.

〔The invention's effect〕

As described above, add a test signal line in which NCH-TR is connected in parallel to the output signal of the decoder, a reference signal line for detecting normal operation, and a circuit for performing abnormality determination by current sensing of both. As a result, it becomes possible to easily detect the input failure of the decoder circuit, and it is possible to further improve the testability of the LSI including the decoder circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the present invention, and FIG.
The figure is a circuit diagram showing a configuration of a decoder circuit according to a conventional technique. 100/200 …… decoder circuit, 101 ・ 102 ・ 103 …… input signal line, 500 ・ 510 …… 570 …… output signal line, 600 …… Vdd
Wire, 650 …… Gnd wire, 700 …… Current sense amplifier, 900 ……
Detection signal line.

Claims (1)

[Claims] 1. A decoder circuit having a plurality of output signals, which outputs a single output signal in response to an input signal, a plurality of transistors for energizing a ground level by the output of the decoder circuit, and a plurality of the transistors. Of the reference circuit having a lower impedance than when a single transistor is in a conducting state and having a higher impedance than when a plurality of transistors are in a conducting state, a parallel connection of the plurality of transistors, and an impedance of the reference circuit Having a sense amplifier for comparison,
A decoder circuit, wherein the impedance of a circuit in which the plurality of transistors are connected in parallel is compared with the impedance of the reference circuit, and an abnormality in the output of the decoder is detected by outputting a comparison signal.