JPH0691438B2 - Period control pulse generator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a cycle control pulse generation circuit capable of controlling the average cycle and instantaneous cycle of an output pulse with extremely high accuracy.

“Prior Art” With the development of electronic devices, many electronic components are being configured with digital circuits. In various digital circuits, a cycle control pulse generating circuit that can control the cycle of an output pulse with high accuracy is extremely important.

A conventional cycle control pulse generating circuit as shown in FIG. 3 is used.

In the figure, reference numeral 1 is a reference oscillator, which generates a stable rectangular wave having a frequency f ₀ = 1 / τ as a reference signal. Reference numeral 2 is a clock circuit, which counts up by 1 each time the reference signal rises and outputs a count value n. 3 is a comparison circuit,
The count value n in the clock circuit 2 is compared with the cycle cumulative value tk output from the timing generation circuit 9. And
When the former falls within a predetermined error range with respect to the latter, a timing pulse is output to the output terminal 8. The timing generation circuit 9 is composed of a latch circuit 4, an adder 5, and a period latch circuit 6.

The operation of this cycle control pulse generating circuit will be described below.
When the target average period of the timing pulse is T, a digitized period value of the data T / τ = N + ΔT is input to the input terminal 7 and latched by the period latch circuit 6. Here, N indicates the integer part of the data T / τ, and ΔT indicates the decimal part. Then, the adder 5 adds the output data of the cycle latch circuit 6 and the cycle accumulated value tk output from the latch circuit 4 up to the present time. The output data of the adder 5 is latched in the latch circuit 4 for each timing pulse C output from the comparison circuit 3. In this way, the latch data of the latch circuit 4, that is, the cycle accumulated value tk is updated according to the following equation for each timing pulse.

tk ← tk + T / τ (1) On the other hand, in the comparison circuit 3, the count value n of the clock circuit 2 and the period cumulative value tk = mT / τ output from the latch circuit 4 (m is the value of T / τ up to the present time) The adder circuit) is compared, and when both match within a certain error range, the timing pulse C is output. In the actual circuit, the timing pulse C is output when the output value n of the clock circuit 2 matches the integer part of mT / τ. Then, the timing pulse is output every (mT / τ) × (period τ of the reference signal) (2) (m = 1, 2, ...), that is, in the vicinity of the time of an integral multiple of the target average period T. It Therefore, although there is one cycle of jitter of the reference signal, a value very close to the target average cycle T is obtained as the average cycle of the timing pulse.

"Problem to be Solved by the Invention" In the conventional cycle control pulse generating circuit described above, when a plurality of timing pulses are continuously output, the count value n of the clock circuit 2 and the cycle accumulation in the timing generating circuit 9 are accumulated. The value tk increases every time a timing pulse is output. Therefore, if it is necessary to continuously generate timing pulses for a long period of time, it is necessary to prepare an extremely large number of bits in the circuit in advance so that this can be allowed. There was a problem that the scale of the product would become extremely large.

The present invention has been made in view of the above circumstances, and a cycle control pulse generating circuit capable of continuously outputting a timing pulse and setting an average cycle thereof arbitrarily and with high precision has a large-scale circuit. The purpose is to realize without.

[Means for Solving the Problems] In order to solve the above problems, the first invention is such that a reference oscillator that generates a reference signal and frequency division number data are input, and the reference signal is divided according to the frequency division number data. A variable frequency divider that divides and outputs a timing pulse; a frequency divider latch circuit that latches input data when the timing pulse is input and outputs as the frequency division data; and a variable frequency divider from the variable frequency divider A period close to the target average period of the timing pulse, which is a period of a signal that can be output, is set as a reference period, and a constant value corresponding to a difference between the reference period and the target average period is set as a period error to be a period error cumulative value. An adder circuit for adding, and every time the timing pulse is input, the output data of the adder circuit is stored and output as a new cyclic error cumulative value, and the magnitude of the cyclic error cumulative value is increased. When the value exceeds a predetermined threshold value, a detection signal is output, and at the same time, a cyclic error cumulative value latch circuit that corrects and outputs the cyclic error cumulative value, and data corresponding to the reference cycle corresponding to the detection signal. And a frequency division number control circuit which supplies the data as input data to the frequency division number latch circuit.

A second aspect of the invention is different from the first aspect of the invention in that it corresponds to a multistage delay circuit that delays the output pulse of the variable frequency divider, and a cyclic error cumulative value output from the cyclic error cumulative value latch circuit. And a delay selection circuit for selecting one of the multistage outputs of the multistage delay circuit and transmitting the selected output signal as a timing pulse.

The relationship with the conventional circuit is that the average period of the timing pulse can be accurately controlled to any rational multiple of the period of the reference signal.

The point that the instantaneous period of the timing pulse can be changed arbitrarily with high accuracy.

While maintaining the advantages of the prior art, such as the reference signal frequency dividing means, instead of the clock circuit 2 and the comparison circuit 3 in the conventional circuit, the timing pulse 1
A point where a variable frequency divider with a sufficient number of bits to count the number of cycles is used.

In the conventional circuit, the cycle is accumulated in the timing generation circuit, whereas in the present invention, the accumulated value of the cycle error is held, and when the accumulated value exceeds a predetermined value, the variable frequency divider The point that the frequency is changed and the cumulative value is updated.

As described above, the circuit of the present invention is capable of continuously generating timing pulses because there is no risk of overflow in each part of the circuit during operation.

There are new advantages such as.

[Operation] According to the first invention, the reference signal output from the reference oscillator is divided by the variable frequency divider. Then, a timing pulse is output from the variable frequency divider. On the other hand, every time the timing pulse is generated, a constant value corresponding to the error between the target average cycle and the reference cycle is cumulatively added, and the cyclic error cumulative value stored in the cyclic error cumulative value latch circuit is updated. When the cyclic error cumulative value exceeds a predetermined threshold value, the cyclic error cumulative value of the cyclic error latch circuit is corrected and the detection signal is output. Then, the data corresponding to the reference period is changed according to the detection signal and supplied to the variable frequency divider, and the frequency division number of the variable frequency divider is switched. As a result, the average period of the timing pulse is very close to the target average period.

According to the second aspect of the invention, the timing pulse is output after being delayed by the delay amount corresponding to the cyclic error cumulative value at the output time point. Therefore, the deviation of the output time of the timing pulse from the ideal value, that is, the jitter is alleviated.

[Examples] Examples of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 is a configuration diagram of a cycle control pulse generating circuit according to a first embodiment of the present invention. In the figure, the reference oscillator 1
Generates a reference signal of frequency f ₀ = 1 / τ, as in FIG. 3 described above. This reference signal is input to the variable frequency divider 13. The variable frequency divider 13 includes a counter circuit 11 and a comparison circuit 12. Then, the pulse of the reference signal is counted by the counter circuit 11, and the count value and the frequency division number stored in the frequency division number latch circuit 14 are compared by the comparison circuit 12. Then, when the both match, a timing pulse is output from the comparison circuit 12 to the output terminal 21. further,
The counter circuit 11 is reset by the timing pulse, and counting is started again from "0". The variable frequency divider 13 is a general programmable frequency divider commercially available as an IC (for example, 74-16 of TTL74 series).
1) may be used. In this case, the carry pulse output from the frequency divider is used as the timing pulse.

Now, at the input terminal 20, the numerical value T / τ = N + ΔT (however,
(T is the target average period, N is the integer part of T / τ, ΔT is the decimal part)
The digital data corresponding to
Latched at 19. The integer part N of the output of the cycle latch circuit 19
Is input as a reference period to an adder circuit 15 provided as a frequency division number control circuit. On the other hand, the decimal part ΔT is input to the adder circuit 18 as a periodic error. Then, the adder circuit 18 adds the cyclic error ΔT and the fractional part ΣΔT of the cyclic error cumulative value in the cyclic error cumulative value latch circuit 17 and outputs it. The output data of the adder circuit 18 is the cyclic error cumulative value latch circuit every time the timing pulse C is generated.
Latched at 17, the cyclic error cumulative value is updated. In addition,
Here, when the result of addition by the adder circuit 18 is "1" or less, the addition result is latched as it is in the decimal part of the period error latch circuit 17, and when the addition result exceeds "1", the integer of the addition result is obtained. And the fractional part are latched in the integer part and the fractional part of the cycle error latch circuit 17, respectively.

Next, it is detected whether or not the cyclic error cumulative value exceeds a predetermined threshold value. In this embodiment, "1" is used as the threshold value. Therefore, whether or not the cyclic error cumulative value exceeds the threshold value "1" is determined from the output of the integer part of the cyclic error cumulative value latch circuit 17. And this latch circuit 17
The integer part of the output data of 1 is added to the reference period N output from the period latch circuit 19 by the adder circuit 15 and supplied to the frequency division latch circuit 14. Therefore, the frequency division number of the variable frequency divider 13 is set every time the cyclic error cumulative value exceeds the threshold value “1”.
Only the amount that exceeds that will be changed.

By the way, since the addition circuit 18 always adds decimals, the absolute value of the integer part of the addition result is "0" and "1".
I can only take it. Further, even if the sign of the period error ΔT is taken into consideration, the output of the adder circuit 15 is any one of N-1, N and N + 1. That is, this cycle control pulse generating circuit
At 10, when the cycle error is cumulatively added and its absolute value exceeds "1", N is changed to N ± 1 by the adder circuit 15 and is sent to the frequency division latch circuit 14 and then the cycle of the timing pulse. The frequency division number corresponding to is set. On the other hand, when the cyclic error is cumulatively added and its absolute value does not exceed "1", the integer part of the output of the cyclic error cumulative value latch circuit 17 becomes "0", and the output of the adding circuit 15 becomes N.

As a result of the control as described above, the timing pulses are continuously output without accumulating the cyclic error accumulated value infinitely. According to this circuit, the timing pulse is output each time the count value of the reference signal becomes N + the integer part of the numerical value mΔT (where m is the number of timing pulses generated up to the present time). This is a conventional circuit (3rd
In the figure), the count value n of the clock circuit 2 is the numerical value mT /
The timing pulse is output when it coincides with the integer part of τ (where m is the number of timing pulses generated up to the present time), and the principle is the same. The circuit of this embodiment is similar to the conventional circuit. As the average period of the timing pulse, a period very close to the target average period can be obtained.

As described above, in the present embodiment, even when infinitely continuous periodic pulses are generated, it is possible to prevent overflow of counts or accumulated values without increasing the circuit scale, and The average period of the timing pulse can be accurately set to any rational multiple of the period of the reference signal. Further, even during the continuous operation, the average period and the instantaneous phase of the generated timing pulse can be instantly changed by changing the digital data corresponding to the target average period of the timing pulse.

[Second Embodiment] In the above-described first embodiment, the timing pulse is output at a time every cycle τ of the reference signal. Therefore, the timing pulse is output with a jitter of ± τ / 2 with respect to the ideal output time. As a method of reducing this jitter, it is conceivable to reduce the period τ. However, in this way, the frequency f _{0 of the} reference oscillator 1 =
1 / τ becomes high, and higher performance hardware is required. Therefore, FIG. 2 shows a period control pulse generating circuit equipped with a device for generating a periodic pulse with less jitter without increasing the frequency f ₀ of the reference oscillator 1.

In the figure, 10 is a circuit having the same configuration as the period control pulse generating circuit in the first embodiment (FIG. 1). A multistage delay circuit 22 and a delay selection circuit 23 are inserted between the circuit 10 and the output terminal 21. The number of delay stages (the number of output terminals) of the multi-stage delay circuit 22 is D, and τ is set for each stage.
Only / D delays τ time. The delay selection circuit 23 selects any one delay output of the multi-stage delay circuit 22 corresponding to the cyclic error cumulative value in the cyclic error cumulative latch circuit 17, and outputs it to the output terminal 21.

From the variable frequency divider 13 in the circuit 10, a timing pulse is generated at the time of (integer part of numerical value (mT / τ) × τ). Therefore, the time of the decimal part of the numerical value (mT / τ) × τ becomes an error, which appears as jitter. In order to remove this jitter, it is sufficient to delay by the time of the decimal value of (mT / τ) × τ. Here, since the fractional part of the cyclic error accumulated value corresponds to the error, the delay selection circuit 23 outputs the delay output having the delay amount having the most equal value with the data of this fractional part.
Select with. By doing so, it becomes possible to correct the jitter in the range of ± (τ × 2D). As described above, according to the present invention, the amount of jitter can be reduced to 1 / D without increasing the frequency of the reference signal.

[Advantages of the Invention] As described above, in the cycle control pulse generation circuit according to the present invention, the timing of the generated pulse is adjusted, and the average cycle of the output pulse is adjusted with extremely high accuracy without increasing the frequency of the reference oscillator. It is possible to control the frequency of the oscillator to an arbitrary rational number and continuously generate pulses without increasing the circuit scale.

Further, during continuous operation, the input phase can be changed to an arbitrary value to instantaneously shift the output phase or change the average frequency.

Further, by providing a multi-stage delay circuit before the output terminal and adjusting the delay time thereof, the jitter of the output pulse can be reduced.

Since the advantages described above are obtained, the present invention replaces the voltage-controlled oscillator used in various synchronizing circuits in digital communication and the digital oscillator by adding / removing pulses, and has an extremely stable oscillation frequency and frequency / phase. Can be used as an oscillator that can be freely and instantaneously controlled.

[Brief description of drawings]

FIG. 1 is a block diagram of a cycle control pulse generator circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram of a cycle control pulse generator circuit according to a second embodiment of the present invention, and FIG. FIG. 3 is a configuration diagram of the cycle control pulse generating circuit of FIG. 1 ... Reference oscillator, 11 ... Counter circuit, 12 ... Comparison circuit, 14 ... Division number latch circuit, 15 ... Adding circuit (division number control circuit), 17 ... Period error accumulated value latch circuit, 18 ……
Adder circuit, 22 ... Multistage delay circuit, 23 ... Delay selection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-23220 (JP, A) JP-A-52-58311 (JP, A) JP-A-58-182924 (JP, A) Actual development Sho-61- 197731 (JP, U)

Claims (2)

[Claims] 1. A reference oscillator for generating a reference signal, a variable frequency divider for inputting frequency division number data, dividing the reference signal according to the frequency division number data, and outputting a timing pulse, and the timing pulse. When the input frequency is input, the input data is latched, and a frequency division number latch circuit that outputs the frequency division number data as the frequency division number data, and a cycle of a signal that can be output from the variable frequency divider that is a target average cycle of the timing pulse An adder circuit that adds a constant value corresponding to the difference between the reference period and the target average period to the period error accumulated value as a period error, when a timing period is input, The output data of the adder circuit is stored and output as a new cyclic error cumulative value, and when the magnitude of the cyclic error cumulative value exceeds a predetermined threshold value, the detection signal is output at the same time. And a cyclic error cumulative value latch circuit that corrects and outputs the cyclic error cumulative value, and data that corresponds to the reference cycle corresponding to the detection signal is changed and supplied as input data to the frequency division number latch circuit. A frequency control pulse generation circuit, comprising: 2. A multistage delay circuit for delaying an output pulse of the variable frequency divider, and a multistage output of the multistage delay circuit corresponding to a cyclic error cumulative value output from the cyclic error cumulative value latch circuit. 2. The cycle control pulse generation circuit according to claim 1, further comprising a delay selection circuit that selects one of the selected output signals and sends the selected output signal as a timing pulse.