JPH0690713B2 - Memory IC simulator - Google Patents

Description

The present invention relates to a memory IC simulator.

[Common technology]

With the recent progress in VLSI technology and the increasing density and scale of integrated circuits, the need for logic simulators is increasing to shorten the development period.

In the initial logic simulation, we simulated only logic circuits using basic logic elements such as AND gates, OR gates, and flip-flops, but simulations of memories with complicated internal states are being put to practical use. is there.

[Conventional technology]

As a conventional technique, for example, there is a memory IC simulator as disclosed in Japanese Patent Publication No. 59-191656.

A conventional memory IC simulator includes an address translation memory, a state memory, a detector, a write register, a master access device, and a read register.

Next, a conventional memory IC simulator will be described in detail with reference to the drawings.

FIG. 7 is a block diagram showing an example of a conventional memory IC simulator.

The memory IC simulator shown in FIG. 7 is an address converter.
71, state memory 72, detector 73, write register 74, read register 75, master access device 76, main memory of parent computer
Includes 77 and.

The address converter 71 inputs the IC number 701 and the address section 702 of the memory IC and outputs the DMA address 706. The state memory 72 inputs the control signal portion 703 of the memory IC, stores it in the memory location indicated by the IC number 701, and outputs the previously stored state 707. The detector 73 compares the previous state 707 with the input control signal portion 703, detects memory access,
The write access detection signal 708 or the read access detection signal 709 is issued. When receiving the write access detection signal 708, the write register 74 inputs and holds the write data 704 of the memory IC and outputs the write output data 710. The master access device 76 is a write access detection signal.
When 708 or read access detection signal 709 is input
A direct access 712 is made to the main memory 77 of the parent computer using the DMA address 706.

When the write access detection signal 708 is output, the write output data 710 is directly output to the access 712, and the main memory 77
Write to the location indicated by DMA address 706. When the read access detection signal is issued, the data is read from the main memory 77 and the read data 711 is issued.

When the read access detection signal 709 is issued to the read register 75, the read data 71 of the master access device 76 is read.
1 is input and held, and read output 705 is output to the memory IC.

[Problems to be solved by the invention]

In the conventional memory IC simulator described above, when the simulation target is a multi-port memory, when a plurality of ports read and write the same address at the same time, the read contents and the written contents differ depending on the order of the evaluated ports. However, there is a drawback that an accurate simulation of a multiport memory cannot be performed.

[Means for solving problems]

The memory IC simulation according to the present invention is performed on a plurality of memory ICs.
In the device for simulating, when the simulation target is a multi-port memory, the multi-port memory is specified when a plurality of ports forming the multi-port memory simultaneously access the memory cells forming the multi-port memory. A scheduler for determining the port number to be simulated, the port number, and the order of the simulated port from the control signal to obtain the memory address, data, control signal, and memory number, and the memory number and memory address when the control signal changes. A real address generator that obtains a real address defined for each memory of the main memory from the state transition memory that stores an internal state number for each memory; and when the memory performs a write operation and a read operation, Data that holds write data and read data A register, said internal state number,
A new internal state number is obtained from the control signal, stored in the state transition memory, the operation of the memory is determined, and when the operation is a write operation, the real address is used for the main memory of the data register. When a value is written and an operation is a read operation, the operation management device is configured to read a value from the main memory to the data register.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

1 is a scheduler, 2 is a real address generator, 3 is a data register, 4 is a state transition memory, 5 is an operation management device,
6 is the main memory.

The scheduler 1 inputs address input 101, control signal group 102, memory number 103, port number 104, input data 105, multiport memory detection signal 106, multiport memory simulation start signal 107, and memory number 110, address 111 and control. When the signal 117 is output and the write detection signal 114 is received from the operation management device 5, the data 112 is sent to the data register 3.
When the read detection signal 115 is received, the data 112 is received from the data register 3.

The real address generator 2 inputs the memory number 110 and the address 111, and outputs the real address 113. Data register 3
Upon receiving the write detection signal 114, the scheduler 1
When the read data 112 is input and held, the write data 116 is output, and the read detection signal 115 is received, the data 116 from the operation management device 5 is input and held, and the read data 112 is output. The state transition memory 4 outputs the previous internal state number 119, and stores the new internal state number 118 output by the operation management device 5 at the position indicated by the memory number 110.

When the operation management device 5 inputs the real address 113, the control signal line group 117, and the internal state number 119, the operation management device 5 determines the operation of the simulation target memory, outputs a new internal state 118 to the state transition memory 4, and outputs it to the main memory 6. Access 120. When the new internal state includes the write operation, the write operation detection signal 114 is output, the write data 116 is output to the access 120, and the main memory 6 is written to the position indicated by the real address 113. When the new internal state includes the read operation, the read operation detection signal 115 is output and the real address 1 of the main memory 6
Data is read from the position indicated by 13 and read data 116 is output to the data register 3.

FIG. 2 is a block diagram showing details of the scheduler shown in FIG. 21 is an encoder, 22 is a priority generation device, 23 is a stack management device, 24 is a stack, 25 is a decoder, and 26 is a bidirectional buffer.

The encoder 21 inputs the address input 101, the control signal group 102, the memory number 103, the port number 104 and the data 105, and outputs the composite data 201. The priority generator 22 inputs the memory number 103, the port number 104, and the priority number
It outputs 202. The stack management device 23 uses the composite data 201,
The priority number 202 is input, the stack 24 is accessed 203, and the composite data 201 is stored in the stack 24 in priority order. The stack 24 stores the composite data 201 in order of priority. When the decoder 25 receives the multiport memory simulation start signal 107, it accesses 204 to the stack 24, reads composite data in the order of priority, data 205, memory number 110, address.
The control signal group 111 and the control signal group 117 are output. The bidirectional buffer 26 receives the read operation detection signal 115 and outputs the read data 1
When 12 is input and held, read data 105 is output, and write operation detection signal 114 is input, write data 205 is input and held, and read data 112 is output.

FIG. 3 is a block diagram showing details of the real address generator shown in FIG. Reference numeral 31 is an address conversion memory, and 32 is an address register. . The address conversion memory 31 inputs the memory number 110 and the address and outputs the real address 301. The address register 32 inputs and holds the real address 301 and outputs the real address 113.

FIG. 4 is a block diagram showing details of the state transition memory shown in FIG. Reference numeral 41 is a memory, and 42 is an output register. The memory 41 reads the previous internal state number 301 from the storage location indicated by the memory number 110 and outputs it. The output register 42, into which the new internal state number output from the operation management device 5 is written, inputs and holds the internal state number 301 and outputs the previous internal state number 113.

FIG. 5 is a block diagram showing details of the operation management device shown in FIG. Reference numeral 51 is a control circuit, and 52 is an access control circuit. The control circuit 51 inputs the previous internal state number 119 and the control signal line group 117, and outputs a write operation detection signal 114, a read operation detection signal 115, and a new internal state number 118. The access control circuit inputs the write operation detection signal 114 and the read operation detection signal 115 and outputs the access 120 to the main memory.

FIG. 6 is a block diagram showing details of the data register shown in FIG. 61 is a bidirectional data buffer.
When the write operation detection signal 114 is input, the bidirectional buffer 61 inputs / holds the write data 112 and stores the data 1
Output 16 When the read operation detection signal 115 is input, the read data 116 is input and held, and the data 112 is output.

〔The invention's effect〕

When the simulation target is a multiport memory, the memory IC simulator of the present invention has an effect that it is possible to accurately simulate the operation of a plurality of multiport memories by using the main memory area for the memory of the simulation target. is there.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a scheduler 1 shown in FIG. 1, 3 is a block diagram showing a real address generator, and FIG. 4 is a state transition memory. 5 is a block diagram showing an operation management device, FIG. 6 is a block diagram showing a data register,
FIG. 7 is a block diagram showing a conventional example. 1 ... Scheduler, 2 ... Real address generator, 3 ...
Data register, 4 ... State transition memory, 5 ... Operation management device, 6 ... Main memory, 21 ... Encoder, 22 ... Priority generator, 23 ... Stack management device, 24 ... Stack, 25 ... Decoder, 26 ... Bidirectional buffer, 31
...... Address translation memory, 32 ...... Address register, 41
...... Memory, 42 ...... Output register, 51 ...... Control circuit, 52 ...... Access control circuit, 61 ...... Bidirectional buffer, 71 ...... Address converter, 72 ...... State memory, 73 ...... Detector, 74 ... write register, 75 ... read register, 76 ... master access device, 77 ... main memory of parent device.

Claims (1)

[Claims] 1. In a device for simulating a plurality of memory ICs, when a simulation target is a multi-port memory, a plurality of ports forming the multi-port memory simultaneously access memory cells forming the multi-port memory. A scheduler for obtaining a memory address, data, a control signal, and a memory number by deciding a port number for specifying the multiport memory and a sequence of ports to be simulated from a control signal, and a control signal when the control signal changes. A real address generator that obtains a real address defined in the main memory for each memory from the memory number and the memory address, a state transition memory that stores an internal state number for each memory, and a write operation for the memory. When performing a read operation, save the write data and read data. Data register, the internal state number, and a new internal state number from the control signal, stores the new internal state number in the state transition memory, determines the operation of the memory, and when the operation is a write operation, the main memory To the main memory, the operation management device reads the value from the data register to the main memory and writes the value to the data register using the real address. .