JPH0690222A - Receiver for spread spectrum communication - Google Patents

Abstract

PURPOSE:To provide a receiver for spread spectrum(SS) communication capable of shortening initial capture time, reducing tracking impossibility due to frequency fluctuation, and surely establishing synchronism. CONSTITUTION:An SS signal sent from a transmission side (base station) is converted to a signal of baseband zone, and after that, it is supplied to a correlation receiver 104. The correlation receiver 104 performs the delay detection of a PN code in chip unit, and calculates correlation with a PN differential system obtained by taking difference at every chip of the PN code, and outputs a data timing signal. The data timing signal is supplied to a PN generator 106, and the PN code can be generated at an obtained timing, and it is multiplied by the SS signal by a multiplier. A frequency control part 110 compares an inputted signal level with a prescribed threshold value level, and takes frequency synchronization by supplying a control signal to a VCO 100 so as to set the level at a value exceeding the threshold level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication receiver, and more particularly to improving synchronization establishment or synchronization tracking in a direct spread (DS) spread spectrum (SS) communication system.

[0002]

2. Description of the Related Art A spread spectrum communication system of direct spread (DS) system (hereinafter referred to as SS system) has advantages such as strong resistance to interference and less interference, and small capacity communication using a satellite line or automobile. Research is being conducted intensively as one of communication methods for mobile communication such as a telephone.

FIG. 19 shows a schematic configuration of this SS type transceiver. FIG. 19 (A) shows the transmitting side (satellite station or base station), and FIG. 19 (B) shows the receiving side (earth). Station or mobile station). On the transmission side, a pseudo noise signal (PN code) generator 4 generates a binary PN code, which is multiplied by an information signal and spread-modulated. Then, phase modulation of a predetermined carrier wave is performed, and the signal is transmitted from the antenna 5 as an SS signal. On the other hand, on the receiving side, the SS signal is received by the antenna 6 and supplied to the synchronizing circuit 7 to establish the synchronization of the code used by the PN code generator 4 on the transmitting side, and the same code is applied to the spread demodulator 8
Supply to. The spread demodulator 8 performs spread demodulation by multiplying the received SS signal by the code from the synchronizing circuit 7, and further the information demodulated by the information demodulator 9 is demodulated.

Here, in order to establish the synchronization in the synchronizing circuit 7, a phase matching point between the frequency synchronization for accurately tuning the frequency uncertain region and the transmitted PN code is searched. It is necessary to realize timing synchronization that suppresses the timing deviation within a predetermined range.

FIG. 20 shows a general circuit configuration for performing frequency synchronization and timing synchronization, which is shown in, for example, "Spread Spectrum Communication System" by Mitsuhiko Yokoyama (published in Science and Technology Publishing Company, 1988). ing. The frequency of the VCO 12 is fixed to a certain value and output according to a command from the frequency controller 11. On the other hand, the clock 14 of the PN code generator 15 is also set to a certain value according to a command from the clock controller 13. In this state, the sine wave from the VCO 12 and P
The signal from the N code generator is multiplied to generate a spread demodulation signal. Then, the SS signal received from the antenna 6 is multiplied by the spread modulation signal, and the band pass filter BPF is obtained.
16 are supplied. The component that has passed through the BPF 16 is squared by the squarer 17, then detected by the integrator 18, and the level thereof is compared with a predetermined threshold value by the search control logic circuit 19. If the level is equal to or higher than the threshold value, it is determined that the initial acquisition is completed, the search is stopped, and the tracking operation using the delay locked loop (DLL) is started. On the other hand, when the level is equal to or lower than the threshold value, the clock is advanced by a predetermined step (Δ / 2) and the level comparison is performed each time. This operation is performed for the time corresponding to one cycle of the PN code. If the initial acquisition is not completed by this operation, the frequency of the VCO 12 is further changed by a predetermined amount and the level comparison is performed. FIG. 21 schematically shows a search operation as shown in the same document as FIG. 20, in which the horizontal axis is the time axis showing the timing and the vertical axis is the frequency axis showing the frequency. The clock and the frequency are moved step by step until the level becomes equal to or higher than a predetermined threshold value, and the search is sequentially performed on (t, f). This operation is a synchronous cell whose level is above the threshold value (shaded area in the figure)
Will be performed until.

After the initial acquisition is completed, data timing tracking is performed using a delay lock loop (DLL) or the like.

On the other hand, as a method of establishing synchronization, a method of using a matched filter (matched filter) instead of using such sliding correlation has been proposed. 22 and 24 show, for example, Vo
l. J69-B No. 11 pp. 15 shows a method of establishing synchronization using the matched filter shown in 1540-1547. FIG. 22 shows an example of a carrier wave phase synchronization and data timing synchronization circuit using a matched filter. This shows a method of synchronizing the phase of the carrier wave and the synchronization of the data timing after the frequency synchronization is established. A method of establishing frequency synchronization will be described later. The received SS signal is converted to a baseband signal by the low-pass filter LPF21 and two orthogonal local signals (a signal from the VCO 19 and a signal obtained by phase-shifting this signal by π / 2) prepared on the receiving side.
This is sampled by the sample hold circuit S / H22,
It is supplied to the correlator 23. The correlator 23 is composed of a matched filter, and has a PN code PN for a desired signal.
(K) is prepared, the PN1 cycle of the received SS signal is multiplied by the PN1 cycle prepared in advance for each chip, and the sum is calculated.

FIG. 23 shows a schematic configuration of the correlator 23 composed of a matched filter. Reception SS
The signals are sequentially stored in the shift register 23a chip by chip. On the other hand, the coefficient generator 23b generates a PN code sequence and multiplies the SS signal stored in the shift register 23a for each chip. The multiplication result is supplied to the adder 23c, the sum thereof is calculated and output. Coefficient generator 23
When the timings of the PN code sequence from b and the PN code of the received SS signal match, the output from the adder 23c becomes maximum (matched pulse). Then, the signal product from the correlator 23 (I and Q) is sampled and held with this matched pulse, whereby information regarding the phase difference is obtained for each PN1 cycle. Further, the phase synchronization of the carrier wave is established by supplying it to the VCO 19 through an appropriate loop filter 25. After the phase synchronization of the carrier wave is established, the phase difference of the carrier wave between transmission and reception becomes 0, so that data demodulation can be performed by the polarity of the matched pulse. Further, by using the matched pulse which is the maximum value of the correlator, the data timing is equivalently tracked.

Further, FIG. 24 shows an example of a frequency synchronizing circuit using a matched filter similar to that shown in FIG. This shows a method of frequency synchronization performed prior to the operation shown in the circuit of FIG. 22 is that a squarer 26, a matched pulse detector 27, a CPU 28 and a frequency counter 29 are added to the output side of the correlator 23. That is, the output from the squarer 26 is added by the adder and supplied to the matched pulse detector 27. This sum of squares output is the frequency difference Δω
Becomes maximum at 0, the CPU 28 commands the VCO to find the frequency so that the output detected by the matched pulse detector 27 becomes maximum, and establishes synchronization. After the frequency synchronization is established, the frequency of the VCO is monitored by the frequency counter 29, and the local signal frequency is controlled so that it always becomes the reference value, whereby the tracking is performed. Although not shown in FIG. 22, the matched pulse is detected by the same method as in FIG. The detection method in the matched pulse detector is described in detail in the same document.

[0010]

As described above, as a method of establishing frequency synchronization and timing synchronization, a method using a sliding correlator and a method using a matched filter are known. There was a problem that it took a long time to establish synchronization.

In other words, with regard to initial acquisition, whichever method is used, in principle, in the case of frequency synchronization, the frequency at which the correlation pulse level reaches the peak is searched while changing the center frequency. It is difficult to detect peaks when timing synchronization is not established. In particular, in the sliding correlation method, the peak must be detected by changing the timing at the same time as the frequency as described above, and in the example of FIG. 21, it takes a long time from the initial setting (t0, f0) to the synchronous cell. It takes money.

As a method for shortening the frequency search time, for example, (1) a beacon signal of a satellite is used, (2) one of the stations participating in the communication always transmits a pilot signal, and the other stations use the beacon signal. Receiving signals and compensating for frequency offset (3) Utilizing carrier recovery circuit (4) Utilizing passive synchronous circuit (5) Utilizing auxiliary signal, etc., but each has the following problems .
That is, (1) not applicable without a beacon signal, (2) not applicable without a pilot signal, even if there is spread spectrum, a frequency search operation is necessary, and if there is no spread spectrum Susceptible to interference waves or frequency selective fading.

(3) It takes time to reproduce the carrier wave.

(5) Not applicable without auxiliary signal. An example of using the passive synchronizing circuit of (4) is Japanese Patent Publication No. 63-31127,
Cycle and add characteristics of PN code, that is, delay multiplication of PN code is converted to PN code with different delay time, so obtain desired PN code with time coincidence by applying appropriate delay to the code after multiplication. It is possible to establish timing synchronization even if there is uncertainty in frequency by passive operation by utilizing the characteristics that can be achieved.
There is a problem that it cannot be applied to a more general PN code sequence that does not have the add property.

Further, it is conceivable to prepare a plurality of frequency synchronization systems and search for a frequency at which the correlation pulse level has a peak at a different frequency, but there arises a problem that the device structure becomes complicated and large.

Also, regarding tracking using a matched filter which is excellent in synchronization characteristics regarding timing, with respect to frequency deviation such that the phase changes during the time (data timing interval) required to detect a correlation pulse. Tracking is impossible, and especially in mobile communications and mobile satellite communications, if the Doppler effect caused by the position variation of the mobile device or satellite affects the frequency shift, this non-tracking condition may occur frequently. is there.

The present invention has been made in view of the above-mentioned problems of the prior art, and its purpose is to shorten the initial acquisition time and to reduce untracking due to frequency fluctuations, thereby reliably establishing synchronization and tracking. It is an object of the present invention to provide a spread spectrum (SS) communication receiver capable of performing the above.

[0018]

In order to achieve the above object, a spread spectrum communication receiver according to claim 1 is provided with:
Correlation between the received signal and the PN sequence, timing synchronization is established, and according to the correlation receiver that gives the data timing and the data timing given from the correlation receiver,
And a frequency control unit that controls the oscillation frequency of the VCO and establishes frequency synchronization based on the obtained correlation value by correlating the received signal with the PN sequence.

In order to achieve the above object, the spread spectrum communication receiver according to claim 2 is the spread spectrum communication receiver according to claim 1, wherein the delay circuit delays the received signal by one chip. And a multiplier for performing differential detection of the received signal by multiplying the received signal and the time-delayed received signal, and a correlation between the output of the multiplier and the PN series differential series, the PN series differential series From the multiplier, the integral discharge filter, and the determination unit that establishes the synchronization of the data timing by comparing the correlation value with the multiplier output PN sequence with a predetermined threshold value. It has a correlation receiver configured.

In order to achieve the above object, the spread spectrum communication receiver according to claim 3 is the spread spectrum communication receiver according to claim 1, wherein a delay circuit delays the received signal by one chip time. , A multiplier that multiplies the received signal by the time-delayed received signal and performs differential detection of the received signal, and inputs the multiplier output, and P
A matched filter using N differential series as a reference sequence, a cyclic adder for performing cyclic addition on the output of the matched filter for each output data in a data timing cycle, and a maximum determination for determining a maximum value from the output of the cyclic adder And a correlation receiver composed of a section and a section.

In order to achieve the above object, a spread spectrum communication receiver according to a fourth aspect of the present invention includes a correlation receiver that correlates a received signal and a PN sequence and tracks data timing, and the correlation reception. A multiplier for multiplying the received signal by the PN code according to the data timing given by the machine, an integral discharge filter for demodulating the data from the multiplication result, a sine wave and a cosine having positive and negative minute frequencies in the multiplication result. A spread spectrum communication characterized by comprising: an AFC unit that multiplies and integrates waves to obtain positive and negative frequency correlations, and controls the VCO oscillation frequency from the frequency correlation result to perform frequency synchronous tracking. Receiver.

To achieve the above object, the spread spectrum communication receiver according to claim 5 is the spread spectrum communication receiver according to claim 4, wherein a delay circuit delays the received signal by one chip time. A multiplier for performing differential detection of the received signal by multiplying the received signal by the time-delayed received signal, a shift register for slightly shifting the timing of the differential sequence of the PN sequence back and forth, A multiplier and an integral discharge filter that respectively take a correlation between the multiplier output and the differential sequence whose timing is slightly shifted forward and backward, an adder that takes a difference between the outputs of the integral discharge filter, and the adder output A loop filter for averaging, and a correlation receiver for tracking data timing by the output of the loop filter. .

In order to achieve the above object, the spread spectrum communication receiver according to claim 6 is the same as the spread spectrum communication receiver according to claim 4.
It is characterized by having the correlation receiver described and tracking the data timing so that the timing at which the maximum correlation value is given is at a fixed location.

In order to achieve the above object, a spread spectrum communication receiver according to a seventh aspect of the present invention averages a multiplication signal of a pseudo noise code generated at a predetermined data timing and the received signal. Averaging according to the parameters, comparing the averaged output with a predetermined threshold value, if the threshold value or less, shift the current data timing by a predetermined time, and if the threshold value or more, ,
The averaging parameter and the threshold value are sequentially changed, and the carrier frequency from the VCO is controlled.

In order to achieve the above object, a spread spectrum communication receiver according to an eighth aspect of the present invention provides a predetermined multiplication signal of the pilot signal pseudo noise code generated at a predetermined data timing and the reception signal. The averaged output is averaged according to the averaging parameter, and the averaged output is compared with a predetermined threshold value. In this case, the averaging parameter and the threshold value are sequentially changed and the carrier frequency from the VCO is controlled, and the received signal is converted to the baseband by using the frequency and the timing given by these controls, and the It is characterized in that data demodulation is performed by multiplication and integration with a pseudo noise code.

[0026]

In the receiver for SS communication according to any one of claims 1 to 6, since the PN code is detected in chip units by the delay circuit, the influence of the frequency offset and the phase difference between the transmitted and received carrier waves can be removed, and this can be ensured. The time can be synchronized with. Then, the frequency search is performed in synchronization with this time and the data is demodulated, so that the initial acquisition time can be shortened.

Further, in the SS communication receivers according to claims 7 and 8, an averaging time (mean parameter) and a threshold value according to the averaging time are set,
If the current data timing is not correct by comparison with the threshold value, fine adjustment of the frequency is not performed, and if it is above the threshold value, it is determined that the data timing may be correct and the averaging time (and Since the frequency control is performed by changing the (threshold value), it is possible to omit fine adjustment of redundant frequencies and complete the search in a short time.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the SS receiver according to the present invention will be described below with reference to the drawings. In the embodiment, the case of BPSK (two-phase phase modulation) is shown for both data modulation and spread modulation.

First Embodiment <Initial Acquisition> FIG. 1 shows the configuration of the first embodiment of the present invention. The SS signal received by the antenna is two orthogonal local signals (a signal from the VCO 100 and a signal obtained by phase-shifting this signal by π / 2 by the phase shifter 102) prepared on the receiving side and a low-pass filter (LPF). After being converted into a baseband signal, it is supplied to the correlation receiver 104.
The correlation receiver 104 performs delay detection as described below and outputs a data timing signal. Then, the data timing signal is supplied to the PN generator 106, the PN code is generated at the obtained timing, and the multiplier multiplies the SS signal. The multiplied signal is integrated discharge filter circuit (I &
After being integratedly discharged at the data timing interval in D), it is squared by the squarer 108, the I component and the Q component are added by the adder, and the result is supplied to the frequency control unit 110. The frequency controller 110 compares the input signal level with a predetermined threshold level, supplies a control signal to the VCO 100 so that the level becomes equal to or higher than the threshold value, and synchronizes the frequency.

Although not shown in the figure, when digital processing is performed, for example, low-pass filter outputs are converted into digital signals by A / D converters.

FIG. 2 shows the correlation receiver 10 in this embodiment.
4 configurations are shown. The correlation receiver 104 includes a one-chip delay circuit 104a, a multiplier 104b and a correlator 104d.
And a part of the received SS signal converted into the base band is supplied to the 1-chip delay circuit 104a. The 1-chip delay circuit 104a delays the input signal by 1 chip and supplies it to the multiplier 104b. Multiplier 104
In b, the undelayed SS signal and the SS signal delayed by one chip are multiplied and supplied to the correlator 104d. The correlator 104d multiplies a PN differential sequence prepared in advance with an input signal (delay detection) as described later, and outputs a correlation pulse.

3 and 4 show the concrete construction of the correlation unit 104d. FIG. 3 shows the case where a matched filter is used and FIG. 4 shows the case where a sliding correlator is used. First, in FIG. 3, the differential detection output from the multiplier 104b is sequentially stored in the register 105a. On the other hand, the coefficient generator 105b outputs a differential sequence of PN codes, the chips are multiplied by the multipliers, and the adder 105c calculates the sum. When the differential detection output and the timing of the differential sequence of the PN code match, the output pulse from the adder 105c becomes maximum, and this correlation pulse is output as the data timing.

It should be noted here that, in this embodiment, since the correlation pulse is output by using the differential detection output for each chip, the influence of the frequency rotation between chips due to the frequency difference between the transmission and reception carrier waves. In addition, it is possible to set the data timing without being affected by the phase difference between the transmitting and receiving carrier waves. When the differential detection is performed as described above, the influence of noise may be more strongly received, but the influence of noise can be eliminated by using a cyclic adder or the like. In the configuration of FIG. 3 as well, the output pulse from the adder 105c is supplied to the cyclic adder 105d, sequentially weighted for each PN period, and then added to the previous data. After several times of addition, the probability that the addition result becomes maximum corresponding to the matched pulse increases, and the data timing can be obtained. Although FIG. 3 shows the case where the differential detection output is input every 1 chip time, the same configuration is realized when inputting every 1/2 chip time. In that case, the shift register 105a
Is shifted every 1/2 chip time and the coefficient generator 105b
The content of is the same differential sequence repeated twice.

On the other hand, in FIG. 4, the differential detection output from the multiplier 104b is multiplied by the differential sequence of the PN code in the multiplier and then supplied to the integral discharge filter (I & D) 105e. The differential sequence of the PN code can be obtained by delaying the PN code sequence from the PN generator by one chip by a delay circuit and multiplying it as shown in FIG. In the integral discharge filter 105e, the multiplication result is, for example, 1
The PN cycle time is integrated, the integrated energy is discharged, and the output is sampled and supplied to the averaging circuit 105f.
The averaged output is compared with a predetermined threshold value in the determination unit 105g, and when it is less than the threshold value, the differential sequence generation unit 105h is instructed to shift the generation timing of the differential sequence. Then, the timing search is continued, and if it is equal to or more than the threshold value, the data timing signal is output.
Even when this integral discharge filter is used, the correlation between the differential detection output of one chip and the differential sequence of the PN code is calculated, as in the case of using the matched filter described above, so that there is no fluctuation in the frequency between the transmitting and receiving carriers. The data timing can be reliably obtained without being affected.

<During Tracking> FIG. 6 shows a circuit configuration for tracking. As described above, the correlation receiver 104 calculates the correlation between the differential detection output and the differential sequence of the PN code, and outputs the data timing signal. Then, at this timing, a PN code is generated and the multiplier multiplies the SS signal. At the time of initial capture, after squaring as shown in FIG. 1,
The frequency control unit 110 compared with a predetermined threshold value, but when tracking, the I component and the Q component from the multiplier are AFC.
It is supplied to the (Auto Frequency Control) unit 107.

In the AFC unit 107, the I component and the Q component are respectively multiplied by the cosine wave of the minute frequency Δf given from the oscillator 107a and the sine wave obtained by shifting the cosine wave by π / 2 by the phase shifter 107b by the multipliers 107c to 107f. The addition / subtraction units 107g to 107j add and subtract the multiplication results in the combinations shown in the figure, and the integration discharge filters 107k to 107n perform integral discharge on the addition / subtraction results in accordance with the data timing. Square with 107r, 2
The multiplier outputs are added by the adders 107s and 107t, the addition results are added with the polarities indicated by the adder 107u, the addition results are averaged through the loop filter 107v, and the averaging result becomes 0. The VCO 100 is controlled to track the frequency fluctuation. This method uses the property that the magnitude of the correlation pulse decreases with the amount of frequency difference, and the frequency is generated so that a positive and negative frequency difference is generated between the cosine wave and the sine wave and the difference between the two becomes zero. The control method is similar to the data timing tracking method using DLL. The output of the adder 107s has a positive frequency difference,
A correlation pulse having a negative frequency difference is output to the adder 107t.

The operation will be described below. Now, it is assumed that the carrier frequency for reception changes by a minute amount fx due to the movement of the mobile body or the position change of the satellite. As a result, the received SS signal is d (t) PN (t) cos [2π (f
c + fx) t + θ]. Here, d (t) is a data signal, PN (t) is a PN sequence, fc is a carrier frequency, and θ is an arbitrary phase defined by [0, 2π].

The product of the output of the VCO 100 and the received SS signal is: d (t) PN (t) cos [2π (fc + fx) t + θ] cos [2πfct] = (1/2) d (t) PN (t ) {Cos [2 · 2π (fc + fx) t + θ] + cos (2πfxt + θ)}. Then, the LPF removes the harmonic components, and obtains (1/2) d (t) PN (t) cos (2πfxt + θ). Similarly, (1/2) d (t) PN (t) sin (2πfxt + θ) is obtained by multiplying the received SS signal and the output of the π / 2 phase shifter 102 and removing the harmonic component by the LPF. . When the timing of the PN code is held by the timing tracking system, the generation timing of the PN code generator 106 is the same as the timing of the received SS signal,
As the I and Q components of the multiplier output, (1 /
2) d (t) cosX and (1/2) d (t) sinX are input to the AFC unit 107. Here, X = 2πfxt
+ Θ.

Next, φ is an arbitrary phase defined by [0, 2π], and the cosine wave given from the oscillator 107a is c
os (2πΔft + φ) = cosY, the sine wave given by the phase shifter 107b is sin (2πΔft + φ) = si
If nY, the multipliers 107c, 107d, 107e,
107f output has sinXcosY and sin respectively.
XsinY, cosXsinY, and cosXcosY are output. Therefore, by performing addition and subtraction as specified in the figure, the adder / subtractors 107g, 107h, 107i, 1
As the 07j output, sinXcosY-cosXsinY = sin (X-Y) = sin [2 [pi] (fx- [Delta] f) t + [theta]-[phi], cosXcosY + sinXsinY = cos (X-Y) = cos [2 [pi] (fx + [Delta] f + t-cos], sinX. sin (X + Y) = sin [2π (fx + Δf) t + θ + φ], cosXcosY−sinXsinY = cos (X + Y) = cos [2π (fx + Δf) t + θ + φ], respectively. The integral discharge filter performs an integral operation for obtaining a correlation value from the PN multiplication result, and further 2
The multiplier removes the influence of the phase terms (θ−φ) and (θ + φ). Note that the influence of the phase is removed by s
In ² A + cos ² A = 1. Therefore, a component corresponding to the correlation power relating to the frequency of the difference from which the influence of the phase (θ−φ) is removed is obtained at the output of the adder 107s, and the influence of the phase (θ + φ) is also removed at the adder 107t. A component corresponding to the correlation power with respect to the sum frequency is obtained. Since the magnitude of the correlation pulse decreases with the frequency difference, if fx is positive, the adder 107e has a larger value and the adder 107u has a negative value. Conversely f
If x is negative, the adder 107u becomes positive. Also, f
If x is zero, the value of the adder 107u is also zero. A
The FC unit 107 thus operates so as to cancel the fluctuation of the frequency difference.

The correlator 104d of the correlation receiver 104
In the case of using the integral discharge filter shown in FIG.
As shown in FIG. 7, the differential detection output is divided into two systems when the data timing is tracked, each is integrated and detected by the integral discharge filter, then one is inverted and added, and the output of the loop filter is set to 0. A configuration may be adopted in which the generation timing of the differential series of codes is adjusted. For example, 105i is a differential series whose timing is 1/2 chip time earlier than the data timing, and 105j is a differential series whose timing is 1/2 chip time later.

Although not shown in the figure, the phase difference between the transmitting and receiving carrier waves is detected by, for example, the arctangent function (tan ⁻¹ ) from the outputs of the integral discharge filters of I and Q in FIG. Is possible by controlling the VCO 100 so that the value becomes 0, and if the phase difference is 0, data demodulation is possible by determining the polarity of the matched pulse of the output of the integral discharge filter on the I side shown in FIG. Become.

In this embodiment, the case where the PN code that does not necessarily hold the Cycle and Add characteristic is used is shown. However, when the Cycle and Add characteristic is held,
It goes without saying that the circuit is further simplified by utilizing this characteristic.

Second Embodiment FIG. 8 shows the circuit configuration of the second embodiment. Receive S
The S signal is converted into two orthogonal local signals (a signal from the VCO 200 and a signal obtained by phase-shifting this signal by π / 2 by the phase shifter 202) and a baseband signal by the LPF, and then both the I and Q components are AFCmean. It is supplied to the section 204. Although not shown in the figure, when digital processing is performed, for example, the LPF outputs are converted into digital signals by A / D converters, respectively. The AFCmeans unit 204 outputs the demodulated data symbol by using the PN code as described later, and at the same time detects the correlation pulse P0 for data timing acquisition and supplies it to the processor 206. Further, the phase difference is detected by using the loop filter, and the VCO 200 is controlled so that the phase difference becomes zero. on the other hand,
Both the I and Q components are also supplied to the timing unit 208. The timing unit 208 shifts the timing of the PN code by Δ (or 2Δ) and −Δ (or −2Δ), PNΔ or PN2Δ code, PN−Δ or PN.
The correlation pulses PΔ and P−Δ are detected by the −2Δ code and supplied to the processor 206. The processor 206 compares the input correlation pulses P0, PΔ, and P−Δ with a predetermined threshold value to detect a data timing signal, and
The mean parameter used in the FC mean unit 204 is appropriately adjusted and output. The data timing signal obtained by the processor 206 is supplied to the clock controller 210, the PN code generator 212 generates a PN code at this timing, and the PN2 for parallel search is used.
It outputs Δ, PNΔ, PN-Δ, and PN-2Δ. In addition,
In this embodiment, Δ = Tc / 2 (Tc: 1 chip cycle) is set.

FIG. 9 shows the AFC mean unit 20 of this embodiment.
4 circuit configuration is shown. The PN code from the PN code generator 212 and the I and Q components of the SS signal are multiplied by the multiplier and supplied to the integral discharge filter 204a. The integral discharge filter 204a performs integral discharge of the input multiplication result over the data timing interval and detects the energy. The output from the integral discharge filter 204a is the squarer 20
4b squared and added, mean 3 parts (averaging part)
It is supplied to 204c. The mean3 unit performs the averaging processing of the correlation pulse using the mean parameter 3 supplied from the processor 206, and sets it as P0 to the processor 2
Supply to 06. On the other hand, the signal obtained by multiplying the PN code and the I and Q components of the SS signal by the multiplier is the mean1 part (averaging part)
It is supplied to 204d. The mean1 unit 204d performs an averaging process using the mean parameter 1 supplied from the processor 206, and supplies the average to the phase calculation unit 204e. The phase calculator 204e calculates tan ⁻¹ (Q / I), detects the phase difference θ, and detects the loop filter 204f.
And further averaging time (mean parameter 1)
The phase amount per hit (that is, the frequency correction amount)
Calculated by g and output the frequency control signal to VCO2
00 is controlled.

FIG. 10 shows the timing unit 208 of this embodiment.
The circuit configuration of is shown. I, Q of SS signal and PNΔ (or PN2Δ) signal from PN code generator 212
The component and PN-Δ (or PN-2Δ) from the PN generator 212 and the I and Q components of the SS signal are multiplied by the multiplier and supplied to the integral discharge filter 208a. The output from the integral discharge filter 208a is squared by a squarer to obtain the mea
It is supplied to the n3 unit (averaging unit) 208c. This mea
The n3 unit 208c is the me of the AFC mean unit 204 described above.
Similarly to the an3 unit 204c, the correlation pulse averaging process is performed using the mean parameter 3 supplied from the processor 206, and the processor 2 is set as P-Δ and PΔ, respectively.
06, and supplies the difference to the processor 206 as an output DLL for the delay locked loop.

Incidentally, the above-mentioned mean1 part, mean3
As shown in FIG. 11, the part is a cyclic adder (A), a low pass filter LPF, or a loop filter (B) such as a lag lead filter, an integral discharge filter I & D (C).
Or any combination of them (m
It is possible to use a cyclic adder for the ean1 section and an integral discharge filter for the mean3 section).

The SS communication receiving apparatus of this embodiment has the above-mentioned configuration, and its operation will be described in detail below with reference to the flowcharts of FIGS. 12 to 13. First, the processor 206 uses the mean parameter used by the AFC mean unit 204 and the timing unit 208, that is, mean.
Parameter 1 and mean parameter 3 are set to appropriate values (mp1 (1) and mp3 (1), respectively) and the band of the loop filter is set to a predetermined width B1 (S
101). Further, the code used in the timing unit 208, that is, the PN code is set to PN-2Δ and PN2Δ (S
102). Next, the data timing is set to T0 (S
103). At this time, the operation of the DLL is stopped,
Data timing is not changed by DLL output. Then, under this initial setting condition, the correlation pulse output P0 and the timing unit 208 supplied from the AFCmeans unit 204
Wait until the correlation pulse outputs PΔ and P−Δ supplied from the above are determined, and after the determination, the process proceeds to the following processing to perform parallel search.

First, the respective outputs P0, PΔ, P-Δ
Is compared with a predetermined first threshold value S1 (S104, S
105, S106). This threshold value is set according to the above-mentioned mean parameter 1 and mean parameter 3. If all of the outputs P0, PΔ, and P−Δ are equal to or less than the threshold value S1, the timing T is shifted to T + 2Δ and the same comparison is performed again (S107). This timing shift is continued until one of the outputs exceeds the threshold value, and when any of the outputs exceeds the threshold value S1, the mean parameter 1 is initialized to mp1 (1).
To mp1 (2) (S108). The mean parameter 1 is a parameter that gives the time for averaging the I and Q components of the SS signal to determine the frequency control amount in the AFC mean unit 204 and the time constant for differentiating the detected phase difference as described above. Is. Therefore, m
When the ean parameter 1 is small, it is weak to noise but responds quickly to the frequency offset, and conversely when it is large, it converges to the optimum value when there is no frequency offset, but responds to the frequency offset. Is slow. Therefore, if any of the outputs exceeds the threshold value S1, the mean parameter 1
By changing mp1 (1) from mp1 (1) to a larger mp1 (2) (that is, mp1 (1) <mp1 (2)), it is possible to perform fine adjustment of the frequency, which takes time.

Then, in this way, the mean parameter 1
Is changed to mp1 (2), parallel search is performed again, and the outputs P0, P.DELTA., And P-.DELTA. Are compared with the threshold value. In addition,
Since the mean parameter 1 is changed to a large value,
The threshold value to be compared with the output is also changed from S1 to a larger second threshold value S2 (S1 <S2) for comparison (S
109, S110, S111). If none of the outputs exceeds the threshold S2, set the mean parameter 1 to mp
The value is returned to 1 (1) (S112), the process proceeds to S107 again, the data timing is stepped, and the search is performed at the next timing. When the output exceeds the threshold value, it is determined that the acquisition (synchronization establishment) is completed, and the data timing T
To the timing at that time (S113, S11
4) The operation of the timing unit 208 is switched from the parallel search mode to the DLL mode to perform synchronous tracking. That is, the PN code used in the timing unit 208 is PN-Δ,
Set to PNΔ (S115), DLL output, that is, FIG.
The data timing T is controlled so that the difference ([PΔ] − [P−Δ]) in the correlation pulse output from the mean unit 208c at 0 becomes 0 (S116). In the tracking mode, it is first determined in S117 to S121 whether the correlation pulse output P0 still has a value equal to or greater than the threshold value S2, and the values of the mean parameter 1 and the mean parameter 3 are set to a larger value mp1 (3 ), Mp3 (2). This is a process for surely performing the initial pull-in operation of the DLL. Note that S117 to S120 may use a method of providing a timer and repeating a loop. Further, the band B1 of the loop filter is changed to B2 (S12).
2). Here, the characteristics of the mean parameter 1 are as described above, but the mean parameter 3 is a parameter that gives an averaging time for obtaining the outputs PΔ and P−Δ from the data timing unit 208. Therefore, when the mean parameter 3 is small, it reacts quickly to a data timing deviation, but is easily affected by noise,
On the other hand, if the mean parameter 3 is large, it will converge to the optimum value if there is no data timing deviation,
It has the characteristic that it reacts slowly to timing deviations. Therefore, by changing the mean parameter 3 to a large value in this way, it is possible to perform highly accurate tracking.

Along with the change of the mean parameters 1 and 3, the threshold value is also changed to a larger third threshold value (S2 <S3) and compared with the correlation output P0 (S).
123-S128). As long as the correlation output P0 is greater than or equal to the threshold value, it is determined that the tracking is being performed and the DLL operation is continued. On the other hand, when the correlation output P0 is less than or equal to the threshold value, it is determined that tracking is difficult. However, in the present embodiment, it is not determined immediately that tracking is impossible, but it is possible to continue tracking by gradually reducing the mean parameter. Is being determined. That is, the value of mean parameter 1 is changed to mp1 in S124.
When the value of (3) is changed to mp1 (2), and further, the value of mean parameter 3 is changed from mp3 (2) to mp3 (1), and the threshold value S3 or S2 is compared again and is equal to or more than the threshold value. Continue tracking, and mean parameters 1, 3
If mp1 (2) and mp3 (1) cannot obtain a value greater than the threshold value, that is, if only an output equal to or less than the correlation output at the completion of capture described above is obtained, it is determined that tracking is impossible and The process is restarted from the captured.

As described above, in this embodiment, a plurality of means are included.
The parameters and thresholds are appropriately changed to perform acquisition and tracking. Fine adjustment is required to remove the frequency offset by changing the value of the mean parameter only when the initially set timing may be correct. So do
The initial acquisition time can be shortened and tracking can be performed reliably.

Third Embodiment The second embodiment exemplifies a case where a data-modulated SS signal is captured and tracked from the transmission side (base station).
It is also conceivable that the base station side transmits a pilot signal, which is only spread modulation and is not data modulated, at the same frequency and at the same timing as the data signal. 14,
15 and 16 receive and capture a pilot signal,
FIG. 14 shows the overall configuration, and FIGS. 15 and 16 show AFCm in FIG. 14, respectively.
The configuration of the ean section and the configuration of the timing section. The difference between these configurations is the configuration for capturing and tracking the data signal described above (FIGS. 8, 9, and 10), in which the integral discharge filter 204a of the AFC mean unit is changed to the mean2 unit that performs averaging processing with the mean parameter 2. Point, a data spreading code generator 305 for obtaining demodulated data, a point having an integral discharge filter 306 separately, a mean3 section 20 for performing averaging processing in the AFC mean section and timing section
4c does not exist (averaging is performed only in the mean2 part).

That is, the received SS signal is converted into two orthogonal local signals (a signal from the VCO 200 and a signal obtained by phase-shifting this signal by π / 2 by the phase shifter 202) and a baseband signal by the LPF, and then I Both the Q and Q components are supplied to the AFC mean unit 300. Although not shown in the figure, when digital processing is performed, for example, low-pass filter outputs are converted into digital signals by A / D converters. The AFCmeans unit 300 detects a correlation pulse P0 for data timing acquisition using a pilot PN code as described later and supplies it to the processor 302. Further, the phase difference is detected by using the loop filter, and the VCO 200 is controlled so that the phase difference becomes zero. On the other hand, both the I and Q components are also supplied to the timing unit 304. The timing unit 304 shifts the timing of the pilot PN code by [Delta] (or 2 [Delta]) and-[Delta] (or -2 [Delta]) by PN [Delta] or PN2 [Delta] code, PN- [Delta] or PN-2 [Delta] code, and the correlation pulse P.
Δ and P−Δ are detected and supplied to the processor 302. In the processor 302, the input correlation pulses P0, P
A, P-Δ is compared with a predetermined threshold value, and AFCmean
The mean parameter used in the unit 300 is appropriately adjusted and output. The data timing signal obtained by the processor 302 is supplied to the clock controller 210, the PN code generator 212 generates a PN code at this timing, and PN2Δ, PNΔ, P for parallel search are used.
It outputs N-Δ and PN-2Δ.

FIG. 15 shows the circuit configuration of the AFCmeans unit 300. The PN from the PN code generator 212 is shown in FIG.
The sign and the I and Q components of the SS signal are multiplied by the multiplier to obtain the mea
It is supplied to the n2 unit 300a. In the mean2 unit, the averaging process is performed using the mean parameter 2 supplied from the processor 302, and the result is squared by the squarer 204b to obtain I,
The Q component is added and supplied to the processor 302 as P0. On the other hand, the signal obtained by multiplying the PN code and the I and Q components of the SS signal by the multiplier is supplied to the mean1 unit (averaging unit) 300c. In the mean1 unit 300c, the processor 30
The averaging process is performed using the mean parameter 1 supplied from No. 2 and supplied to the phase calculator 300d. The phase calculation unit 300d calculates tan-1 (Q / I), detects the phase difference θ, supplies it to the loop filter 300e, and further, the phase amount per averaging time (mean parameter 1) (that is, frequency correction). The quantity) is calculated by the differentiator 300f to control the VCO 200.

FIG. 16 shows the circuit configuration of the timing section 304. PNΔ from the PN code generator 212 is shown.
(Or PN2Δ) code, I and Q components of SS signal, and PN-Δ (or PN-2 from the PN generator 212).
Δ) and the I and Q components of the SS signal are multiplied by the multiplier to obtain mea
It is supplied to the n2 unit 304a. The output from the mean2 unit 304a is squared by the squarer 304b, and P−Δ and
The difference is output to the processor 302 as PΔ, and the difference is supplied to the processor 302 as an output DLL for the delay locked loop. In addition, as the mean2 part, FIG.
Any of the averaging means (A), (B) and (C) shown in 1 can be used.

Compared to the second embodiment, the integral discharge filter 2
04a and 208b mean each performing averaging processing
It is changed to 2 parts 300a, 304a, but this is
This is because the correlation processing is performed on the pilot signal that is not data-modulated. That is, for a signal that is data-modulated, if the averaging time is 1 data time or more, even if the timings match and there is a correlation,
The averaged output may become zero due to the polarity reversal of the data, but if the data modulation is not applied, there is no polarity reversal of the data, so there is no need to perform the integration time in data timing units, and there is more flexibility. In addition to the above design, the averaging operation after the squaring operation can be performed in advance in this part by performing averaging over one data time or more, so that the circuit scale can be reduced.

Since the mean parameter 1 is a parameter relating to establishment and tracking of frequency synchronization, a parameter corresponding to a time of 1 data time or less is assumed.

The processing method for capturing and tracking a pilot signal with such a configuration will be described in detail below with reference to the flowcharts of FIGS. First, the processor 30
2 is a mean parameter used in the AFC mean unit 300 and the timing unit 304, that is, mean parameters 1 and 2 are appropriate values (mp1 (1) and mp2, respectively).
(1)) (S201). Further, the code used in the timing unit 304, that is, the PN code is PN-2Δ,
It is set to PN2Δ (S202). Next, the data timing is set to T0 (S203). At this time, D
The operation of the LL is stopped and the data timing is not changed by the output of the DLL. And under this initial setting condition, AFC
Correlation pulse output P0 supplied from the mean unit 300 and correlation pulse output P supplied from the timing unit 304
Wait until Δ and P−Δ are respectively determined, and after the determination, shift to the following processing and perform parallel search.

First, the respective outputs P0, PΔ, P-Δ
Is compared with a predetermined first threshold value S1 (S204, S204
205, S206). This threshold value is set according to the above-mentioned mean parameter 1 and mean parameter 2. If any of the outputs P0, PΔ, and P−Δ is less than or equal to the threshold value S1, the timing T is shifted to T + 2Δ and the same comparison is performed again (S207). This timing shift is continued until one of the outputs exceeds the threshold value, and when any of the outputs exceeds the threshold value S1, the mean parameter 1 is initialized to mp1 (1).
To mp1 (2) (S208). The relationship between the reaction and convergence corresponding to the mean parameter 1 and the frequency offset is the same as in the second embodiment.

Then, in this way, the mean parameter 1
Is changed to mp1 (2), parallel search is performed again, and the outputs P0, P.DELTA., And P-.DELTA. Are compared with the threshold value. In addition,
Since the mean parameter 1 is changed to a large value,
The threshold value to be compared with the output is also changed from S1 to a larger second threshold value S2 (S1 <S2) for comparison (S
209, S210, S211). If none of the outputs exceeds the threshold S2, set the mean parameter 1 to mp
The value is returned to 1 (1) (S212), the process proceeds to S207 again, the data timing is stepped, and the search is performed at the next timing. When the output exceeds the threshold value, it is determined that the acquisition (synchronization establishment) is completed, and the data timing T
To the timing at that time (S213, S21
4) The operation of the timing unit 304 is switched from the parallel search mode to the DLL mode to perform tracking. That is,
The PN code used in the timing unit 304 is PN-Δ, PN
It is set to Δ (S215), and the data timing T is controlled so that the DLL output, that is, the difference ([PΔ] − [P−Δ]) in the correlation pulse output becomes 0 (S216). In the synchronous tracking mode, first, it is determined in S217 to S221 whether the correlation pulse output P0 still has a value equal to or greater than the threshold value S2, and the mean parameters 1 and me are determined.
The value of an parameter 2 is set to a larger value mp1 (3), m
Change to p2 (2). These are processes for surely performing the DLL pull-in operation. The operation of S217 to S220 may be a method of providing a timer and repeating a loop for a predetermined time. The characteristics of the mean parameter 1 are as described above. On the other hand, when the mean parameter 2 is small, it reacts quickly to a data timing deviation, but is easily affected by noise, and conversely, the mean parameter 2 is large. In this case, if there is no data timing deviation, it converges to the optimum value, but it has the characteristic that it reacts slowly to the timing deviation. Therefore, by changing the mean parameter 2 to a large value in this way, it is possible to perform highly accurate tracking.

Along with the change of the mean parameters 1 and 2, the threshold value is changed to a larger third threshold value (S2 <S3) and compared with the correlation output P0 (S).
223). As long as the correlation output P0 is greater than or equal to the threshold value, it is determined that the tracking is being performed and the DLL operation is continued. On the other hand, when the correlation output P0 is less than or equal to the threshold value, it is determined that tracking is difficult, but it is not immediately determined that tracking is impossible, but m
It is determined whether the tracking can be continued by gradually decreasing the ean parameter (S224 to S228). That is,
In step S224, the value of the mean parameter 1 is changed from mp1 (3) to mp1 (2), and further, the mean parameter 2 is changed to mp.
Change to 2 (1), compare again with threshold value S3 and further with S2 and if it is equal to or greater than the threshold value, continue tracking, m
ean parameters 1 and 2 are mp1 (2) and mp, respectively
Even in 2 (1), if a value equal to or greater than the threshold value is not obtained, that is, if the output is equal to or less than the correlation output at the time of completion of capture described above, it is determined that tracking is impossible, and the process is restarted from the capture described above.

As described above, in the case of the pilot signal, there is no polarity inversion (BPSK) in data units, and when the timings match, the product of the received SS signal and the PN code has the same polarity. It is not necessary to perform averaging processing like the data signal after the squaring processing by the squaring device, and the acquisition and tracking can be performed with a simpler configuration. Regarding data demodulation, it is possible to obtain the demodulated data symbol from the polarity of the correlation pulse by despreading using the spreading code for data according to the given timing. In the embodiment, BP is used for both data modulation and spread modulation.
The case of SK is shown, but one or both is QPS.
Even in the case of K modulation, it can be easily expanded by considering the spreading code or the polarity of the correlation pulse.

[0063]

As described above, the SS according to the present invention
According to the communication receiver, the initial acquisition time can be greatly shortened, and the information data can be demodulated by appropriately tracking the frequency shift of the carrier.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a correlation receiver of the same embodiment.

FIG. 3 is a configuration block diagram of a correlation unit of the same embodiment.

FIG. 4 is another block diagram of the configuration of the correlation unit of the same embodiment.

FIG. 5 is a configuration block diagram of a PN code differential sequence generation circuit of the embodiment.

FIG. 6 is a configuration block diagram of the same embodiment during tracking.

FIG. 7 is a configuration block diagram of the same embodiment during tracking.

FIG. 8 is a configuration block diagram of data signal processing according to the second embodiment of the present invention.

FIG. 9 is a configuration block diagram of an AFCmeans unit of the embodiment.

FIG. 10 is a configuration block diagram of a timing section of the embodiment.

FIG. 11 is a configuration block diagram of a mean unit of the embodiment.

FIG. 12 is an operation flowchart of the embodiment.

FIG. 13 is an operation flowchart of the embodiment.

FIG. 14 is a configuration block diagram of pilot signal processing according to the third embodiment of the present invention.

FIG. 15 is a configuration block diagram of an AFC mean unit in the embodiment.

FIG. 16 is a configuration block diagram of a timing section of the embodiment.

FIG. 17 is an operation flowchart of the embodiment.

FIG. 18 is an operation flowchart of the embodiment.

FIG. 19 is a configuration block diagram of a conventional system.

FIG. 20 is a configuration block diagram of a conventional receiving device.

FIG. 21 is an explanatory diagram of conventional frequency and timing search.

FIG. 22 is a block diagram of a configuration of a receiving device using a conventional matched filter when tracking.

FIG. 23 is a configuration diagram of a matched filter.

FIG. 24 is a block diagram of a configuration of a receiving device using a conventional matched filter during frequency acquisition and tracking.

[Explanation of symbols]

 6 Antennas 15, 106, 212 PN code generator 104 Correlation receiver 204, 300 AFCmean section 206, 302 Processor 208, 304 Timing section

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 8, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

(5) Not applicable without auxiliary signal. Examples in the case of utilizing passive synchronization circuit (4) is Ru include JP-B-63-31127. This
This is because Cycle and add characteristics of PN code, that is, delay multiplication of PN code is converted to PN code with different delay time, so by applying an appropriate delay to the code after multiplication, the desired PN code with time coincidence can be obtained. Using the characteristics that can be obtained, timing synchronization is established even if there is uncertainty in frequency in passive operation.
There is a problem that it cannot be applied to a more general PN code sequence that does not have the and add characteristic.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

<During Tracking> FIG. 6 shows a circuit configuration for tracking. As described above, the correlation receiver 104 calculates the correlation between the differential detection output and the differential sequence of the PN code, and outputs the data timing signal. Then, at this timing, a PN code is generated and the multiplier multiplies the SS signal. At the time of initial capture, after squaring as shown in FIG. 1,
The frequency control unit 110 compared with a predetermined threshold value, but when tracking, the I component and the Q component from the multiplier are AFC.
It is supplied to the ( Automatic Frequency Control) unit 107.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction content]

Next, φ is an arbitrary phase defined by [0, 2π], and the cosine wave given from the oscillator 107a is c
os (2πΔft + φ) = cosY, the sine wave given by the phase shifter 107b is sin (2πΔft + φ) = si
If nY, the multipliers 107c, 107d, 107e,
107f output has sinXcosY and sin respectively.
XsinY, cosXsinY, and cosXcosY are output. Therefore, by performing addition and subtraction as specified in the figure, the adder / subtractors 107g, 107h, 107i, 1
As the 07j output, sinXcosY−cosXsinY = sin (X−Y) = sin [2π (fx−Δf) t + θ−φ], cosXcosY + sinXsinY = cos (X−Y) = cos [2π (fx − Δf) t + θ−φ], sinXcosY + cosXsinY = sin (X + Y) = sin [2π (fx + Δf) t + θ + φ], cosXcosY−sinXsinY = cos (X + Y) = cos [2π (fx + Δf) t + θ + φ], respectively. The integral discharge filter performs an integral operation for obtaining a correlation value from the PN multiplication result, and further 2
The multiplier removes the influence of the phase terms (θ−φ) and (θ + φ). Note that the influence of the phase is removed by s
In ² A + cos ² A = 1. Therefore, a component corresponding to the correlation power relating to the frequency of the difference from which the influence of the phase (θ−φ) is removed is obtained at the output of the adder 107s, and the influence of the phase (θ + φ) is also removed at the adder 107t. A component corresponding to the correlation power with respect to the sum frequency is obtained. Since the magnitude of the correlation pulse decreases with the frequency difference, if fx is positive, the adder 107e has a larger value and the adder 107u has a negative value. Conversely f
If x is negative, the adder 107u becomes positive. Also, f
If x is zero, the value of the adder 107u is also zero. A
The FC unit 107 thus operates so as to cancel the fluctuation of the frequency difference.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

Second Embodiment FIG. 8 shows the circuit configuration of the second embodiment. Receive S
The S signal is converted into two orthogonal local signals (a signal from the VCO 200 and a signal obtained by phase-shifting this signal by π / 2 by the phase shifter 202) and a baseband signal by the LPF, and then both the I and Q components are AFCmean. It is supplied to the section 204. Although not shown in the figure, when digital processing is performed, for example, the LPF outputs are converted into digital signals by A / D converters, respectively. The AFCmeans unit 204 outputs the demodulated data symbol by using the PN code as described later, and at the same time detects the correlation pulse P0 for data timing acquisition and supplies it to the processor 206. Further, the phase difference is detected by using the loop filter, and the VCO 200 is controlled so that the phase difference becomes zero. on the other hand,
Both the I and Q components are also supplied to the timing unit 208. The timing of the PN code in the timing unit 208 delta (or 2.DELTA.) And - [delta (or -2Deruta) only the shifted was PNderuta (or PN2deruta) code, PNΔ (or PN2deruta) code correlation pulse PΔ, P- Δ is detected and supplied to the processor 206. The processor 206 compares the input correlation pulses P0, PΔ, and P−Δ with a predetermined threshold value, detects a data timing signal, and measures the mean used in the AFC mean unit 204.
Adjust the parameters appropriately and output. Processor 206
The data timing signal obtained in
0, and at this timing, the PN code generator 212
, PN2Δ, PNΔ, PN-Δ, PN-2Δ for parallel search are generated. In this embodiment, Δ = Tc / 2 (Tc: 1 chip cycle) is set.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction content]

That is, the received SS signal is converted into two orthogonal local signals (a signal from the VCO 200 and a signal obtained by phase-shifting this signal by π / 2 by the phase shifter 202) and a baseband signal by the LPF, and then I Both the Q and Q components are supplied to the AFC mean unit 300. Although not shown in the figure, when digital processing is performed, for example, low-pass filter outputs are converted into digital signals by A / D converters. The AFCmeans unit 300 detects a correlation pulse P0 for data timing acquisition using a pilot PN code as described later and supplies it to the processor 302. Further, the phase difference is detected by using the loop filter, and the VCO 200 is controlled so that the phase difference becomes zero. On the other hand, both the I and Q components are also supplied to the timing unit 304. The timing unit 304 shifts the timing of the pilot PN code by Δ (or 2Δ) and −Δ (or −2Δ), and outputs PNΔ ( or PN2).
Δ ) code and PN-Δ ( or PN-2Δ ) code are used to detect the correlation pulses PΔ and P-Δ and supply them to the processor 302. In the processor 302, the input correlation pulse P
0, PΔ, P−Δ are compared with a predetermined threshold value, and AFCm
The mean parameter used in the ean unit 300 is appropriately adjusted and output. The data timing signal obtained by the processor 302 is supplied to the clock controller 210, the PN code is generated from the PN code generator 212 at this timing, and PN2Δ and PN for parallel search are used.
It outputs Δ, PN-Δ, and PN-2Δ.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

FIG. 7 is a block diagram of the configuration of the correlation unit in tracking according to the embodiment.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

FIG. 8 is a configuration block diagram of a second embodiment of the present invention.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14 is a configuration block diagram of a third embodiment of the present invention.

Claims (8)

[Claims] 1. A spread spectrum communication receiving apparatus for receiving a signal spread spectrum by a direct spread method by a pseudo noise code and demodulating information data from the received signal, obtaining a correlation between the received signal and a PN sequence, Correlation receiver that establishes timing synchronization and gives data timing, and correlates the received signal with the PN sequence according to the data timing given from the correlation receiver, and oscillates the VCO based on the obtained correlation value. A frequency control unit that controls a frequency and establishes frequency synchronization, and a receiver for spread spectrum communication. 2. A delay circuit for delaying a received signal by one chip time, a multiplier for multiplying the received signal by the time-delayed received signal and performing differential detection of the received signal, an output of the multiplier and a PN. A correlation value between a multiplier and an integral discharge filter for calculating the correlation with the differential sequence of the sequence while shifting the generation timing of the differential sequence of the PN sequence and a predetermined threshold value The receiver for spread spectrum communication according to claim 1, further comprising: a correlation receiver configured to determine the synchronization of data timing by performing the above. 3. A delay circuit for delaying a received signal by one chip time, a multiplier for multiplying the received signal by the time-delayed received signal and performing differential detection of the received signal, and an input to the multiplier output A matched filter using a differential series of PN series as a reference series, a cyclic adder that performs cyclic addition for each output data of the matched filter output in a data timing cycle, and a maximum value is determined from the output of the cyclic adder. The spread spectrum communication receiving apparatus according to claim 1, further comprising a correlation receiver including a maximum determination unit. 4. In a spread spectrum communication receiving device for receiving a signal spread spectrum by a direct spread method by a pseudo noise code and demodulating information data from this received signal, the received signal and a PN sequence are correlated with each other, A correlation receiver that tracks data timing, a multiplier that multiplies a received signal and a PN code according to the data timing given by the correlation receiver, an integral discharge filter for demodulating data from the multiplication result, and An AFC unit for performing frequency synchronous tracking by multiplying a multiplication result by a sine wave and a cosine wave having small positive and negative frequencies, integrating the product, obtaining a positive and negative frequency correlation, and controlling the oscillation frequency of the VCO from the frequency correlation result. A receiver for spread spectrum communication, comprising: 5. A delay circuit that delays a received signal by one chip time, a multiplier that multiplies the received signal by the time-delayed received signal and performs differential detection of the received signal, and a PN series differential series. A shift register for slightly shifting the timing back and forth, a multiplier and an integral discharge filter that respectively correlate the output of the multiplier and the differential sequence whose timing is shifted slightly back and forth, and the integral An adder for taking a difference between outputs of a discharge filter, and a loop filter for averaging the output of the adder, and a correlation receiver for tracking data timing by the output of the loop filter. 4. The spread spectrum communication receiver according to item 4. 6. The spread spectrum apparatus according to claim 4, wherein the correlation receiver according to claim 3 is provided, and the data timing is tracked so that the timing at which the maximum correlation value is given is at a fixed location. Communication receiver. 7. A spread spectrum communication receiver for receiving a signal spread spectrum by a direct spread method by a pseudo noise code and demodulating information data from the received signal, the pseudo noise code generated at a predetermined data timing. And the received signal are averaged according to a predetermined averaging parameter, and the averaged output is compared with a predetermined threshold value. And a carrier frequency from the VCO is controlled while the averaging parameter and the threshold are sequentially changed when the difference is equal to or larger than the threshold. 8. A spread spectrum communication receiver for receiving a signal spread spectrum by a direct spread method by a pseudo noise code and demodulating information data from this received signal, for a pilot signal generated at a predetermined data timing. A signal obtained by multiplying the pseudo-noise code and the received signal is averaged according to a predetermined averaging parameter, and the averaged output is compared with a predetermined threshold value. If it is equal to or more than the threshold value by shifting by a predetermined time, the averaging parameter and the threshold value are sequentially changed and the carrier frequency from the VCO is controlled, and the frequency and timing given by these controls are used. Then, the received signal is converted to baseband, multiplied by the pseudo noise code for data, and integrated to obtain the data recovery. Spread spectrum communication receiver and performs.