JPH0687360B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory technology and a test technology in a semiconductor memory device, and is used, for example, when a semiconductor memory device that can be read from and written to at any time has a function of facilitating a test. And about effective technology.

2. Description of the Related Art A semiconductor memory device (hereinafter referred to as a semiconductor memory) such as a RAM (Random Access Memory) becomes a defective product if there is a defective cell even in one bit in a memory array. Therefore, the testing for detecting a good product or a defective product in a semiconductor memory in which data is read or written bit by bit is performed by changing all addresses to 1 bit for all memory cells in the memory array. It is necessary to access each of them and read the signal output from the output pin at that time to judge pass / fail.

Moreover, in the semiconductor memory, it is not enough to simply access all the bits one by one to make a judgment. That is,
Data in one memory cell in a memory array in which a plurality of memory cells are arranged in a matrix may be changed by accessing memory cells in adjacent rows or columns. Therefore, in order to make a complete pass / fail judgment in such a 1-bit semiconductor memory, in addition to a test for writing / reading each bit, a test called galloping for accessing in relation to all other bits, etc. Is performed. In such a galloping test, N ² accesses are required, where N is the number of bits of the memory array.

However, since the capacity of the semiconductor memory has been increasing more and more in recent years, the test time required to make a perfect pass / fail judgment exponentially increases as the memory capacity increases. As a result, when the test time for pass / fail judgment given to one product is limited, the test pattern that can be executed within the given time is relatively decreased, and the detection rate of defective products is lowered. There is a problem.

Therefore, the present applicant has previously configured the memory array by dividing it into a plurality of mats, providing a pad for output observation for each memory mat, and enabling simultaneous access to all memory mats. In a 1-bit memory, the output of memory cells of multiple bits can be viewed at the same time, so that the test time in a large-capacity memory can be shortened or the defective product detection rate can be improved. An invention relating to a semiconductor memory device has been proposed (Japanese Patent Application No. 58-123272).

However, in the above-mentioned prior invention, since a pad for observing the test output is newly provided, there is a disadvantage that the chip size becomes large accordingly.

[Object of the Invention] It is an object of the present invention to shorten the test time required to perform a good / bad judgment in a semiconductor memory without increasing the chip size so much or to improve the defective product detection rate. Is to be able to.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

That is, the memory array is divided into a plurality of mats (for example, 4 mats), a common input / output signal line and an amplifier circuit such as a main amplifier are provided corresponding to each mat, and the common input / output signal line from each mat is tested. A coincidence detection circuit for receiving the data read out is provided. This match detection circuit
A first state in which data read in parallel from the memory mats to the respective common input / output signal lines is received and all the bits take a first logical value, and a second state in which all the bits take a second logical value. , And the third state in which the logical values of all of these bits do not match even with 1 bit is determined, and the determination result is output from the output buffer circuit in three levels of high level, low level, and high impedance so as to be distinguishable from each other. For example, when the same data is written in the same address position of each mat and read out in parallel, and if all the data read in parallel match, "0" or "1" is associated with the logical value of the data. "Data is output from the output buffer,
When even 1 bit does not match, the output of the output buffer is set to a high impedance state. As a result, even in a semiconductor memory device that inputs / outputs data to / from the outside on a bit-by-bit basis, it is possible to simultaneously determine a plurality of bits according to the number of mat divisions of the memory array. further,
Since the judgment result is obtained in three values, the quality judgment can be made immediately by observing the test result, thus achieving the above-mentioned object of shortening the test time or improving the defective product detection rate. To do.

At this time, the test is set by the test control signal generated by the signal forming circuit on the semiconductor substrate that constitutes the semiconductor memory device of the present invention. The signal forming circuit forms the test control signal based on the change timing of the external control signal including the strobe signals of the row address signal and the column address signal.

[Embodiment] FIG. 1 shows the RA of 256 k × 1 bit configuration according to the present invention.
Shown as applied to M. Each circuit shown as a functional block in the drawing is formed on one semiconductor substrate such as silicon.

In the figure, reference numeral 1 denotes a memory array composed of memory cells of 256 k bits. The memory array 1 is not particularly limited, but four memory mats 1a and 1b in which memory cells of 64 k bits are arranged in a matrix respectively. , 1c, 1d.

Of the memory mats 1a to 1d, 1a and 1b are X decoders 2a.
, And the memory mats 1c and 1d are arranged symmetrically with the X decoder 2b in between. Further, column switch circuits 3a to 3d are arranged on one side of each of the memory mats 1a to 1d.

Reference numeral 4 denotes an address buffer circuit. The address buffer circuit 4 is provided with an external address multiplex method 2
The X-system address signal Ax and the Y-system address signal Ay, which are given separately in time, are input, and appropriate internal address signals ax,
▲ ▼ and ay, ▲ ▼ are formed. When this internal address signal ax, ▲ ▼ is supplied to the X decoders 2a, 2b, the corresponding one word line in the memory mats 1a, 1b is set to the selection level by the X decoder 2a.
Further, the X decoder 2b sets the corresponding one word line in each of the memory mats 1c and 1d to the selection level.
On the other hand, the internal address signal ay, ▲ ▼ is supplied to the Y decoder 5, and the Y decoder 5 turns on the corresponding column switch in each of the column switch circuits 3a to 3d,
It is arranged to select a pair of data lines.

Further, in this embodiment, common input / output lines I / O _{1 to} I / O ₄ as common input / output signal lines are provided for each of the memory mats 1a to 1d, and the column switch circuits 3a to 3d respectively The data line pairs selected for each memory mat are connected to the common input / output lines I / O _{1 to} I / O ₄ , respectively.

The common input / output lines I / O _{1 to} I / O ₄ are connected to the read / write circuit 6, and the common input / output lines I / O _{1 to} I / O _{4 are connected.}
Read / write of the selected memory cell is performed via the data line pair connected to. An input / output buffer circuit 7 is connected to the read / write circuit 6.

2 and 3 show specific configuration examples of the write circuit and the read circuit that constitute the read / write circuit 6.

The write circuit, as shown in FIG.
I / O ₁ ~I / O connected to the ₄ four write drivers WD ₁ ~WD ₄
It is composed by. The write drivers WD _{1 to} WD ₄ are supplied with the true level write data din and the false level write data ▲ ▼ formed in the input buffer DIB based on the input signal applied to the input terminal Din. Has been done. In addition, write drivers WD _{1 to} WD
₄ is activated based on a part of the internal address signal supplied from the address buffer 4 and the test control signal φt.

That is, in the write drivers WD _{1 to} WD ₄ , only one of the drivers is activated by, for example, the upper 2 bits of the address when writing in the normal mode in which the memory normally reads and writes. The pair of common input / output lines are driven according to the input data applied to the input terminal Din, and the data is written to the selected memory cell in any one of the memory mats.

On the other hand, in the test mode, the test control signal φt
Accordingly, all the write driver WD ₁ ~WD ₄ is to be activated. As a result, the input terminal Din
All the common input / output lines I / O _{1 to} I / O ₄ are driven in the same way according to the input data applied to the memory mats, and all the memory mats 1a to 1d have the same address position corresponding to each other. Can write the data.

As shown in FIG. 3, the read circuit is used for each common input / output line.
Four main amplifiers MA connected to I / O _{1 to} I / O ₄ respectively
_{1 to} MA ₄ and a logic gate unit LG including four-input NAND circuits G ₁ and G ₂ that take the logical product of signals on the common input / output lines I / O _{1 to} I / O ₄ .

The above main amplifiers MA _{1 to} MA ₄ are write drivers WD _{1 to} WD ₄
Same as the above, for example, it is activated by the upper 2 bits of the address, and amplifies the read data sent through the common input / output lines I / O _{1 to} I / O ₄ . And each main amplifier MA _1- M
Of the switches (not shown) provided at the final stage of A ₄ , only one switch corresponding to the upper 2 bits of the address is made conductive, and the output of the main amplifier is the common output signal line. It is designed to be sent to the logic gate unit LG through.

At the input terminal of the 4-input NAND circuit G ₁ that constitutes the logic gate unit LG, among the common input / output lines I / O _{1 to} I / O ₄ , the read data of the same phase as the write data is at the true level. Side (T)
Of the common input / output lines I / O _{1 to} I / O ₄ to the input terminals of the 4-input NAND circuit G ₂ are connected to the signal lines of The signal lines on the level side (B) are connected to each other.

Although not particularly limited, the above-mentioned output signal line is provided in the logic gate section LG. Inverters INV ₁ and INV ₂ that invert the above signals, and four outputs of the inverters INV ₁ and INV _{2 and} the outputs of the NAND circuits G ₁ and G ₂ are supplied to one input terminal respectively. of
AND circuits G _{3 to} G ₆ are provided. Further, among the NAND circuits G _{3 to} G ₆ , the outputs of G ₃ and G ₄ are supplied to the input terminals of the NOR circuit G ₇ , and the outputs of AND circuits G ₅ and G ₆ are of the second NOR circuit G ₈ . It is designed to be supplied to the input terminal.

The outputs of the NOR circuits G ₇ and G ₈ drive the MOSFETs (insulated gate type field effect transistors) Q ₁ and Q ₂ forming the push-pull type output buffer DOB.

Further, the other input terminal of the AND circuit G ₃ and G ₆ in which the output of the 4-input NAND circuit G ₁ and G ₂ are input respectively, the same test as the signal for controlling the write driver WD ₁ ~WD ₄ A control signal φt is applied, and this control signal φt causes AND
Circuits G ₃ and G ₆ are opened and closed. On the other hand, with the inverter INV ₁
The output of the inverter INV ₃ that inverts the test control signal φt is applied to the other input terminals of the AND circuits G ₄ and G ₅ to which the output of INV ₂ is input, and the AND signal is inverted by the inverted signal of the control signal φt. Circuits G ₄ and G ₅ are adapted to be opened and closed.

In the read circuit, when reading in the normal mode in which the memory is normally read and written, only one output of the main amplifiers MA _{1 to} MA ₄ is output by the upper 2 bits of the address. Through the inverters INV ₁ and INV ₂ , where it is inverted and input to the AND circuits G ₄ and G ₅ . Then, normal
In the mode, since the test control signal φt is not applied, the output of the inverter INV ₃ is set to the high level, and the AND circuits G ₄ and G ₅ are opened. Therefore, the outputs of the above-mentioned inverters INV ₁ and INV ₂ , that is, the amplified signal of the selected main amplifier, passes through AND circuits G ₄ and G ₅ , and NOR circuit G ₇
To be supplied to the G _8.

Further, in the normal mode, since the test control signal φt is not applied, the gates of the AND circuits G ₃ and G ₆ are closed, and the outputs of the NAND circuits G ₁ and G ₂ are not passed. as a result,
The outputs of the inverters INV ₁ and INV ₂ are inverted by the NOR circuits G ₇ and G ₈ and supplied to the gate terminals of the MOSFETs Q ₁ and Q ₂ . Thus, the output buffer DOB is, MOSFET Q ₁
And Q ₂ are complementarily turned on and off, and when Q ₁ is turned on, a high level signal is output to the output terminal Dout, and when the MOSFET Q ₂ is turned on, a low level (ground potential) signal is output.

On the other hand, the read circuit outputs the high-level test control signal φt.
In the test mode in which is applied, the test control signal φt closes the gates of the AND circuits G ₄ and G ₅ in the logic gate unit LG, and opens the gates of the AND circuits G ₃ and G ₆ instead. Therefore, the read data amplified by the main amplifiers MA _{1 to} MA ₄ are not supplied to the NOR circuits G ₇ and G ₈ , and the NAND circuit G ₁ connected to the common input / output lines I / O _{1 to} I / O ₄ The output of G ₂ is supplied to the NOR circuits G ₇ and G ₈ .

However, the signal of the data read from the same address location in each memory mat 1a~1d is at all "1", the true level side of the common input-output lines _{I / O 1 ~I / O 4} (T) is , And all become high level, the output of the NAND circuit G ₁ becomes low level. Further, at this time, the signals on the false level side (B) of the common input / output terminals I / O _{1 to} I / O ₄ are all at low level, so the output of the NAND circuit G ₂ is at high level.

As a result, the output (high level) of the NAND circuit G ₁ is
It is inverted in ₇ and applied to the gate terminal of MOSFET Q ₁ to turn it on, and the output (low level) of NAND circuit G ₂ is inverted in NOR circuit G ₈ to be applied to the gate terminal of MOSFET Q ₂ and turned off. Let Therefore, if all the data read from the four memory mats is "1",
A high level signal is output to the output terminal Dout.

Further, when the data read from the same address location in each memory mat 1a~1d conversely is all "0", the true level side of the common input-output lines I / O ₁ ~I / O ₄ of the (T) Since the signals are all at the low level, the output of the NAND circuit G ₁ is at the high level. Further, at this time, all the signals on the false level side (B) of the common input / output lines I / O _{1 to} I / O ₄ become high level, so that the output of the NAND circuit G ₂ becomes low level.

As a result, the output (low level) of the NAND circuit G ₁ is
It is inverted by ₇ and applied to the gate terminal of MOSFET Q ₁ to turn it off, and the output (high level) of NAND circuit G ₂ is inverted by NOR circuit G ₈ and applied to the gate terminal of MOSFET Q ₂ , which Turn it on. Therefore, if all the data read from the four memory mats is "0",
A low level signal is output to the output terminal Dout.

Further, if even one data read from the same address position of the memory mats 1a to 1d is different, the NAND circuit G ₁
And the output of G ₂ is driven high. Therefore, NOR circuit G
The outputs of ₇ and G ₈ are both set to low level, which turns off both MOSFETs Q ₁ and Q ₂ forming the output buffer DOB, and sets the output terminal Dout to high impedance.

Therefore, if the same data is written in advance at the same address position of each of the memory mats 1a to 1d and then read out and the output terminal Dout is observed, it is easy to determine whether or not all four data match. It can be known that if the output terminal has a high impedance despite writing the same data, it can be known that an erroneous write has occurred, and this can be immediately determined as a defective product.

Moreover, according to the above-described embodiment, by applying the high-level test control signal φt for writing, it is possible to write the same data at the same address position of the four memory mats at the same time, and to write the four data. By reading at the same time, it is possible to know whether or not there is an erroneous write. In this case, in the above embodiment, even if all the data are erroneous, the output is reversed, so that this can be detected.

As a result, the test can be completed in a quarter of the time required for the conventional memory in which data is written and read bit by bit for testing.

In the above embodiment, a switch is provided at the final stage of the four main amplifiers MA ₁ to MA ₄ provided corresponding to the respective memory mats 1a-1b, on the basis of the switch to the upper 2 bits of the address on, Turn off and output the output signal of one of the main amplifiers. However, instead of operating all the main amplifiers MA _{1 to} MA ₄ and selecting one of the outputs with a switch, for example, one output corresponding to the upper 2 bits of the address is used. It can be configured so that only the main amplifier is activated.

Similarly, for the write drivers WD _{1 to} WD ₄ , instead of activating one driver corresponding to the upper 2 bits of the address, the output of the driver is changed to the common I / O line I / I.
A switch for connecting to O _{1 to} I / O ₄ is provided to select one of the activated drivers at the same time, or the output of the input buffer is directly connected to one of the upper 2 bits of the address. It may be configured to supply to one common input / output line.

In the conventionally proposed nibble type memory (which has a mode capable of serially reading / writing 4-bit data at high speed), the memory array is divided into four mats, and each memory mat is divided into four mats. Since the main amplifier is provided, the present invention can be easily applied to such a memory.

Further, in the above embodiment, an example of the logic gate unit LG including the NAND circuits G ₁ and G ₂ for detecting the coincidence of the signals on the common input / output line is shown. The present invention is not limited to such a configuration, and various modifications can be considered. For example, an AND circuit may be used instead of the NAND circuits G ₁ and G ₂ , and an exclusive OR circuit may be used to detect a match or a mismatch.

Further, the test control signal φt described in the above embodiment is
It is formed by the signal forming circuit based on appropriate timing of external control signals such as ▲ ▼ signal (row address / strobe signal) and ▲ ▼ signal (column address / strobe signal) used in dynamic RAM and the like. The signal forming circuit for forming the test control signal φt is formed on the same semiconductor substrate as the semiconductor memory device of the above embodiment.

[Effect] A first state in which all the bits of the data read in parallel from the memory mats to the respective common input / output signal lines have the first logical value, and a second state in which all the bits have the second logical value, And the third state in which the logical values of all the bits do not match is determined, and the determination result is output from the output buffer circuit by the three values of high level, low level, and high impedance so that they can be distinguished from each other. A plurality of bits of test data read from each memory mat can be determined at the same time according to the number of mat divisions, which can shorten the test time and improve the defective product detection rate. The effect is that you can do it.

Moreover, since the test results can be distinguished from each other by the three values, the logical state of the data written for the test is a defect state in which all the bits to be collectively judged are reversed and a defect in which some of the bits are reversed. It is possible to obtain a determination result that distinguishes from the state and improve the reliability of the test. In addition, since the test result corresponding to the logical value of the read data can be obtained without supplying the expected value data to the semiconductor memory device in the determination operation after the write of the test data, the test can be simplified. is there. Also, the signal obtained by the NAND circuit in the test mode,
Then, for each of the signals output from the main amplifier selected in the non-test mode, the series connection transistor of the data output buffer is set to the push-pull drive and high impedance state, and both the test result and the normal read data are shared. It can be taken out from the output terminal of. This allows for external output of test results,
It is not necessary to newly provide an output circuit that requires a relatively large driving capability, and the area occupied by the chip for a circuit used only for testing can be reduced.

Although the invention made by the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Absent. For example, only one of the write circuit shown in FIG. 2 and the read circuit shown in FIG. 3 may be used to write or read 4 bits at the same time.

In the above embodiment, the memory array is divided into four memory mats, but the number of memory mats is not limited to four, but may be any number such as eight or sixteen. . Needless to say, the memory capacity is not limited to 256 kbits.

[Field of Use] In the above description, the invention mainly made by the present inventor is described as being applied to a 1-bit configuration RAM for reading and writing bit by bit, which is the field of use in the background of the invention, but is not limited thereto. Not a thing, for example, a multi-bit RAM or ROM such as 4 bits
It can also be applied to storage devices such as (read only memory).

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment when the present invention is applied to a 1-bit RAM, FIG. 2 is a circuit configuration diagram showing an example of a write circuit in the embodiment, and FIG. 3 is a circuit configuration diagram showing an example of a read circuit in the same manner. FIG. 1 ... Memory array, 1a-1d ... Memory mat, 2a, 2b
...... X decoder circuit, 3a to 3d …… Column switch circuit,
4 ... Address buffer circuit, 5 ... Y decoder circuit,
6 ... Read / write circuit, 7 ... Input / output buffer circuit,
I / O _{1 to} I / O ₄ ...... Common input / output signal line (common input / output line),
DIB …… Input buffer, WD _{1 to} WD ₄ …… Write drive circuit (write driver), MA _{1 to} MA ₄ …… Main amplifier, LG…
… Match detection circuit (logic gate), DOB …… output buffer, φt …… test control signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaya Muranaka 1479, Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi My Cross Computer Engineering Co., Ltd. Black Computer Engineering Co., Ltd. In-house (72) Inventor Takeshi Kajimoto 1450, Kamisuimotocho, Kodaira-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (56) Reference JP-A-56-71898 (JP, A) JP-A-57 -105897 (JP, A)

Claims (1)

[Claims] 1. A plurality of memory mats in which memory cells are arranged in a matrix, and an address decoder for decoding row address signals and column address signals to select memory cells from each of the memory mats at substantially the same timing. A complementary common input / output signal line provided for each memory mat and to which the memory cell selected by the address decoder is coupled, and a complementary common input / output signal line provided for each complementary common input / output signal line. The output terminal is coupled to the output signal line, the input terminal is commonly connected to the output of the data input buffer, and in the test mode instructed by the test control signal, it corresponds to the write data supplied from the data input buffer. Write-drive the complementary common input / output signal line to be set to the non-test mode instructed by the test control signal. The write driver that drives the corresponding complementary common input / output signal line corresponding to the write data supplied from the data input buffer only selected by the address signal, and the individual complementary common input / output signal line A corresponding main amplifier, whose input terminal is coupled to the corresponding complementary common input / output signal line and whose output terminal is commonly connected to the complementary common output signal line, and the respective complementary common input / output signal lines A first NAND circuit having an input terminal coupled to a non-inverted signal line constituting the second NAND circuit having an input terminal coupled to an inverted signal line constituting each of the complementary common input / output signal lines; The output of the first NAND circuit and one of the first signal lines forming the complementary common output signal line are coupled to the input terminal, and in the test mode, the first NAND circuit of the first NAND circuit is connected. The output of the second NAND circuit and the complementary common output signal line for selecting the output of the transmission signal from the first signal line in the non-test mode A second signal line of the second NAND circuit is coupled to the input terminal, and the output of the second NAND circuit is selected in the test mode and the transmission signal from the second signal line is selected and output in the non-test mode. A second selection circuit, a first transistor switch-controlled based on the output of the first selection circuit, and a second transistor switch-controlled based on the output of the second selection circuit are connected in series. In the non-test mode, the first and second transistors are complementarily switch-controlled in accordance with the logical value of the complementary common output signal line, and in the test mode, all the above-mentioned transistors are switched. Complementary common input / output signal line is first
The first and second transistors are complementarily switch-controlled in accordance with the first state in which the logical value of 1 is taken and the second state in which all of them take the second logical value, and the complementary common input / output signal line is also provided. And a data output buffer in which both the first and second transistors are cut off in accordance with a third state in which the logical values of 1 are not matched with each other, and a single semiconductor substrate is provided. And semiconductor memory device.