JPH0685675A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPH0685675A
JPH0685675A JP23078392A JP23078392A JPH0685675A JP H0685675 A JPH0685675 A JP H0685675A JP 23078392 A JP23078392 A JP 23078392A JP 23078392 A JP23078392 A JP 23078392A JP H0685675 A JPH0685675 A JP H0685675A
Authority
JP
Japan
Prior art keywords
converter
resolution
output
series
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23078392A
Other languages
Japanese (ja)
Inventor
Daisaku Yoshioka
大作 吉岡
Masashi Yonemaru
政司 米丸
Yoshiki Shibata
喜樹 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP23078392A priority Critical patent/JPH0685675A/en
Publication of JPH0685675A publication Critical patent/JPH0685675A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To apply A/D conversion with high resolution to only a required part. CONSTITUTION:Resistor strings R1-R192 which show n-bit resolution and resistor strings R193-R447 which show (n+a)-bit resolution are arranged in series in an A/D converter. The resistance value of the resistor string which shows (n+a)- bit resolution is set 1/2 times as much as that of the resistor string which shows the n-bit resolution, and digital output shows (n+a)-bits. Therefore, cost reduction, the reduction of a chip area, and low power consumption can be attained comparing with the case where the whole of A/D converter is made to high resolution.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はA/D変換器に関し、主
に非線形特性をA/D変換するときに利用されるもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter and is mainly used for A / D conversion of nonlinear characteristics.

【0002】[0002]

【従来の技術】従来技術の8ビットのA/D変換器の構
成を図5に示す。この回路では、基準電圧発生のための
抵抗値の等しいRr1〜Rr256が直列に配置され、
前記各基準電圧値とアナログ入力電圧Vinとを比較す
るためのコンパレ−タCc1〜Cc255が配置され、
これらのコンパレ−タの出力がエンコ−ダ11に入力さ
れ、8ビットのディジタルデ−タ12が出力される構成
となっている。従来の8ビットのA/D変換器では分解
能が均一なため、線形特性については問題なかったが、
一方、CCDのアナログ出力をA/D変換するように、
非線形特性を取り扱う場合には、各基準電圧を発生する
抵抗列の各抵抗値が等しいため一定の間隔で量子化され
るので、分解能が充分である部分と不充分な部分が発生
し、CCDのアナログ出力のA/D変換を充分な分解能
で行えなかった。
2. Description of the Related Art FIG. 5 shows the configuration of a conventional 8-bit A / D converter. In this circuit, Rr1 to Rr256 having the same resistance value for generating the reference voltage are arranged in series,
Comparators Cc1 to Cc255 for comparing the respective reference voltage values with the analog input voltage Vin are arranged.
The outputs of these comparators are input to the encoder 11, and the 8-bit digital data 12 is output. Since the conventional 8-bit A / D converter has uniform resolution, there was no problem with the linear characteristic.
On the other hand, so that the analog output of the CCD is A / D converted,
When dealing with the non-linear characteristic, since the resistance values of the resistance strings that generate the reference voltages are equal, the resistance values are quantized at regular intervals, so that a part with sufficient resolution and a part with insufficient resolution occur, and The analog output A / D conversion could not be performed with sufficient resolution.

【0003】これまで、非線形特性を取り扱う場合に
は、A/D変換器の分解能をあげる方法があった。例え
ば、8ビットの分解能をもつA/D変換器を、10ビッ
トの分解能をもつA/D変換器にかえるような場合であ
る。8ビットの分解能をもつA/D変換器を10ビット
の分解能をもつA/D変換器にした場合、8ビットA/
D変換器の場合は255個のコンパレ−タが必要である
が、10ビットA/D変換器の場合は1023個のコン
パレ−タが必要になり、当然、8ビットと比較して10
ビットの方が、消費電力、チップ面積の点で不利であ
り、あるいは、回路規模が大きくなったり、回路構成が
複雑になったりした。
Heretofore, there has been a method of increasing the resolution of the A / D converter when dealing with nonlinear characteristics. For example, there is a case where an A / D converter having a resolution of 8 bits is replaced with an A / D converter having a resolution of 10 bits. When an A / D converter with 8-bit resolution is replaced with an A / D converter with 10-bit resolution, 8-bit A / D
In the case of a D converter, 255 comparators are required, but in the case of a 10-bit A / D converter, 1023 comparators are required.
Bits are disadvantageous in terms of power consumption and chip area, or have a large circuit scale or a complicated circuit configuration.

【0004】また、非線形特性を取り扱う場合には、各
分圧抵抗の値を非線形特性にあわせて、異なる抵抗値に
設定する方法があった。この場合には、8ビットのA/
D変換器では255個のコンパレ−タが必要で、非線形
特性にあわせて異なった抵抗値をもつ抵抗を直列に配置
する必要があり、やはり、回路構成が複雑になったりし
た。
In the case of handling the non-linear characteristic, there has been a method of setting the value of each voltage dividing resistor to a different resistance value according to the non-linear characteristic. In this case, 8-bit A /
The D converter requires 255 comparators, and it is necessary to arrange resistors having different resistance values in series according to the non-linear characteristic, which again complicates the circuit configuration.

【0005】[0005]

【発明が解決しようとする課題】以上、従来技術によれ
ば、非線形特性をA/D変換する場合、回路規模が大き
くなったり、回路構成が複雑になるなどして、消費電力
の増大、チップ面積の増大等の問題を生じた。
As described above, according to the prior art, when A / D converting the non-linear characteristic, the circuit scale becomes large and the circuit configuration becomes complicated, resulting in an increase in power consumption and a chip. Problems such as increase in area occurred.

【0006】本発明は上記問題点を比較的簡単な構成で
解決することにある。
The present invention is to solve the above problems with a relatively simple structure.

【0007】[0007]

【課題を解決するための手段】入力されたアナログ信号
に対して高分解能の要する部分にのみ、より抵抗値の低
い抵抗列に分割してアナログ信号電圧の分解能をあげる
方法による。
According to a method of increasing the resolution of an analog signal voltage by dividing a resistance series having a lower resistance value into only a portion requiring high resolution for an input analog signal.

【0008】すなわち、本発明のA/D変換器は、複数
の抵抗が直列接続されると共に、その両端に所定の電圧
が印加され、上記各抵抗の接続点より複数の基準電圧を
発生する抵抗列と、上記各基準電圧と入力アナログ電圧
とを比較し、比較結果を出力する複数のコンパレ−タ
と、該コンパレ−タよりの出力に基ずいて所定ビット数
のディジタル信号を出力するエンコ−ダとを有するA/
D変換器において、第1の抵抗値をもつ複数の抵抗が直
列接続された第1の抵抗列と、上記第1の抵抗値に対し
て1/2a(a:自然数)の関係を有する第2の抵抗値
をもつ複数の抵抗が直列接続された第2の抵抗列とが直
列接続された上記抵抗列と、上記コンパレ−タよりの出
力に基ずいて、入力アナログ電圧が上記第1の抵抗列よ
り発生される基準電圧範囲にあるときはnビットのディ
ジタル信号を出力し、入力アナログ電圧が上記第2の抵
抗列より発生される基準電圧範囲にあるときは、(n+
a)ビットのディジタル信号を出力する上記エンコ−ダ
とを設けたことを特徴とするものである。
That is, in the A / D converter of the present invention, a plurality of resistors are connected in series, and a predetermined voltage is applied to both ends of the resistors to generate a plurality of reference voltages from the connection points of the resistors. A column, a plurality of comparators for comparing the respective reference voltages with the input analog voltage and outputting the comparison result, and an encoder for outputting a digital signal of a predetermined number of bits based on the outputs from the comparators. A / with da
In the D converter, a first resistor string in which a plurality of resistors having a first resistance value are connected in series and a first resistor string having a relationship of 1/2 a (a: natural number) with respect to the first resistance value. Based on the output from the comparator and the resistor string in which a second resistor string in which a plurality of resistors having a resistance value of 2 are connected in series and the output from the comparator are input, When it is in the reference voltage range generated by the resistor string, an n-bit digital signal is output, and when the input analog voltage is in the reference voltage range generated by the second resistor string, (n +
a) The above encoder for outputting a bit digital signal is provided.

【0009】[0009]

【作用】A/D変換器で必要な部分のみ高分解能に設定
することができる。
It is possible to set high resolution only to the required portion of the A / D converter.

【0010】[0010]

【実施例】以下に、CCDの出力をA/D変換する場合
の本発明の実施例について述べる。図2に示すようにC
CDに入力する光量と出力電圧の関係は線形であるが,
CCDの情報を出力するCRT等ではガンマ特性を有す
るため、図3に示すように逆ガンマ特性により補正する
ため、線形でない。ここで、A−C間で8ビットの分解
能でA/D変換すると、B−C間では分解能が低くなっ
てしまう。A−B間での分解能と同程度な分解能を得る
ためには B−C間では、8ビットより高い分解能が必
要である。
EXAMPLE An example of the present invention for A / D converting the output of the CCD will be described below. As shown in FIG.
The relationship between the amount of light input to the CD and the output voltage is linear,
Since a CRT or the like that outputs CCD information has a gamma characteristic, it is not linear because it is corrected by the inverse gamma characteristic as shown in FIG. Here, if A / D conversion is performed between A and C with 8-bit resolution, the resolution between B and C becomes low. In order to obtain a resolution similar to that between A and B, a resolution higher than 8 bits is required between B and C.

【0011】例えば、光量の少ない領域であるA−B間
は8ビット、光量の多い領域B−C間は10ビットで量
子化したときは、A−B間は191段階に分割され、B
−C間は254段階に分割され、全体として8ビットの
分解能(256段階)であるが、補助ビット2ビット分
があるため、A/D変換後のディジタル出力は補助ビッ
ト2ビット分が加わり、10ビットのディジタル出力と
なる。
For example, when quantization is performed with 8 bits between A and B, which is a low light amount region, and with 10 bits between a high light amount region B and C, A and B are divided into 191 steps and B is divided.
-C is divided into 254 steps, and the resolution is 8 bits as a whole (256 steps), but since there are 2 bits of auxiliary bits, 2 bits of auxiliary bits are added to the digital output after A / D conversion, It becomes a 10-bit digital output.

【0012】図4に本発明のディジタル出力とアナログ
入力電圧との関係を、図1に本発明の回路構成の実施例
を示す。この回路では、アナログ入力信号値Vinを比
較するためにA−C間に基準電圧Vrefを設け、A側
をGNDとして、8ビット分解能となる抵抗列R1〜R
192、10ビット分解能となる抵抗列R193〜R4
47が直列に配置され、Vrefを各抵抗分圧によって
定められた各基準電圧値とVinを比較するためにコン
パレ−タC1〜C446があり、これらのコンパレ−タ
の出力がエンコ−ダ1に入力され、8ビット出力2と補
助2ビット出力3のデ−タが出力される。本発明では分
解能の分布にあわせた抵抗値を選択すればよく、R2か
らR192までの抵抗値をrとした場合、抵抗列R19
3〜R447の抵抗値をr/4の値に設定すればよく、
その結果、B−C間ではA−B間と比較して2ビット分
の分解能が増す。その結果、精度が要求されるアナログ
入力信号の高い所でも必要な分解能が確保される。その
結果、約450個のコンパレ−タで10ビットと同等な
分解能が得られる。
FIG. 4 shows the relationship between the digital output of the present invention and the analog input voltage, and FIG. 1 shows an embodiment of the circuit configuration of the present invention. In this circuit, a reference voltage Vref is provided between A and C in order to compare the analog input signal value Vin, the A side is set to GND, and the resistor strings R1 to R having 8-bit resolution are provided.
192, 10-bit resolution resistor series R193 to R4
47 are arranged in series, and there are comparators C1 to C446 for comparing Vref with each reference voltage value determined by each resistance voltage division, and the outputs of these comparators are provided to the encoder 1. The data is input and 8-bit output 2 and auxiliary 2-bit output 3 data is output. In the present invention, the resistance value may be selected according to the distribution of resolution, and when the resistance value from R2 to R192 is r, the resistance string R19
The resistance value of 3 to R447 may be set to a value of r / 4,
As a result, the resolution between B and C is increased by 2 bits as compared with that between A and B. As a result, the required resolution can be ensured even in a place where the analog input signal, which requires precision, is high. As a result, a resolution equivalent to 10 bits can be obtained with about 450 comparators.

【0013】さらに、本発明は、基本ビットが8ビット
構成のため、量子化値は従来のA/D変換器と同様に扱
うことができるので、非線形特性のみならず、線形特性
についても適用が可能である。
Furthermore, since the present invention has an 8-bit basic bit, the quantized value can be handled in the same manner as a conventional A / D converter, so that it can be applied to not only nonlinear characteristics but also linear characteristics. It is possible.

【0014】なお、本発明は上記実施例に限定されな
い。
The present invention is not limited to the above embodiment.

【0015】[0015]

【発明の効果】以上詳述したように、本発明によれば、
A/D変換器全体を高分解能に設定せずに、必要な部分
にのみ高分解能に設定できるA/D変換器が実現でき、
その結果、効率的なデバイス構成のため、コストダウ
ン、チップ面積の縮小、低消費電力化が可能となる。
As described in detail above, according to the present invention,
It is possible to realize an A / D converter that can set high resolution only in a necessary part without setting the entire A / D converter to high resolution,
As a result, cost reduction, chip area reduction, and power consumption reduction are possible due to the efficient device configuration.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のA/D変換器の回路構成図
である。
FIG. 1 is a circuit configuration diagram of an A / D converter according to an embodiment of the present invention.

【図2】入射光量とCCDの出力電圧の関係を示す図で
ある。
FIG. 2 is a diagram showing the relationship between the amount of incident light and the output voltage of a CCD.

【図3】CCD出力とカメラ出力、及び、逆ガンマ−特
性とカメラ出力の関係を示す図である。
FIG. 3 is a diagram showing a relationship between a CCD output and a camera output, and an inverse gamma-characteristic and a camera output.

【図4】ディジタル信号の量子化値とアナログ入力電圧
との関係を示す図である。
FIG. 4 is a diagram showing a relationship between a quantized value of a digital signal and an analog input voltage.

【図5】従来のA/D変換器の回路構成図である。FIG. 5 is a circuit configuration diagram of a conventional A / D converter.

【符号の説明】[Explanation of symbols]

1 エンコ−ダ 2 8ビットディジタル出力信号線 3 補助2ビットディジタル出力信号線 R1〜R447 基準電圧設定用分圧抵抗 C1〜R446 コンパレ−タ Vin アナログ電圧値 Vref 基準電圧 1 Encoder 2 8-bit digital output signal line 3 Auxiliary 2-bit digital output signal line R1 to R447 Voltage dividing resistors for setting reference voltage C1 to R446 Comparator Vin Analog voltage value Vref Reference voltage

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数の抵抗が直列接続されると共に、その
両端に所定の電圧が印加され、上記各抵抗の接続点より
複数の基準電圧を発生する抵抗列と、上記各基準電圧と
入力アナログ電圧とを比較し、比較結果を出力する複数
のコンパレ−タと、該コンパレ−タよりの出力に基づい
て所定ビット数のディジタル信号を出力するエンコ−ダ
とを有するA/D変換器において、 第1の抵抗値をもつ複数の抵抗が直列接続された第1の
抵抗列と、上記第1の抵抗値に対して1/2a(a:自
然数)の関係を有する第2の抵抗値をもつ複数の抵抗が
直列接続された第2の抵抗列とが直列接続された上記抵
抗列と、上記コンパレ−タよりの出力に基ずいて、入力
アナログ電圧が上記第1の抵抗列より発生される基準電
圧範囲にあるときはnビットのディジタル信号を出力
し、入力アナログ電圧が上記第2の抵抗列より発生され
る基準電圧範囲にあるときは、(n+a)ビットのディ
ジタル信号を出力する上記エンコ−ダとを設けたことを
特徴とするA/D変換器。
1. A resistor string in which a plurality of resistors are connected in series and a predetermined voltage is applied to both ends thereof to generate a plurality of reference voltages from a connection point of the resistors, the reference voltages, and an input analog. In an A / D converter having a plurality of comparators that compare a voltage and output a comparison result, and an encoder that outputs a digital signal of a predetermined number of bits based on the output from the comparators, A first resistance string in which a plurality of resistances having a first resistance value are connected in series and a second resistance value having a relationship of 1/2 a (a: natural number) with respect to the first resistance value A second resistor string in which a plurality of resistors are connected in series is connected in series, and an input analog voltage is generated from the first resistor string based on the output from the comparator. N-bit digit when within the reference voltage range And an encoder for outputting a digital signal of (n + a) bits when the input analog voltage is within the reference voltage range generated by the second resistor string. A / D converter.
JP23078392A 1992-08-31 1992-08-31 A/d converter Pending JPH0685675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23078392A JPH0685675A (en) 1992-08-31 1992-08-31 A/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23078392A JPH0685675A (en) 1992-08-31 1992-08-31 A/d converter

Publications (1)

Publication Number Publication Date
JPH0685675A true JPH0685675A (en) 1994-03-25

Family

ID=16913202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23078392A Pending JPH0685675A (en) 1992-08-31 1992-08-31 A/d converter

Country Status (1)

Country Link
JP (1) JPH0685675A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798370B1 (en) * 2001-09-20 2004-09-28 Matsushita Electric Industrial Co., Ltd. Parallel A/D converter
JP2008263613A (en) * 2007-04-11 2008-10-30 Mediatek Inc Data readout system having non-uniform adc resolution and related method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798370B1 (en) * 2001-09-20 2004-09-28 Matsushita Electric Industrial Co., Ltd. Parallel A/D converter
JP2008263613A (en) * 2007-04-11 2008-10-30 Mediatek Inc Data readout system having non-uniform adc resolution and related method therefor
US7859441B2 (en) 2007-04-11 2010-12-28 Mediatek Inc. Data readout system having non-uniform ADC resolution and method thereof
US8040268B2 (en) 2007-04-11 2011-10-18 Mediatek Inc. Data readout system having non-uniform ADC resolution and method thereof
DE102008018164B4 (en) 2007-04-11 2018-08-23 Mediatek Inc. Non-uniform resolution analog-to-digital converter system and method therefor

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