JPH0685202A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide the manufacturing method, of a semiconductor memory device, wherein, when the memory cell pattern of a DRAM or the like is exposed by using a Levenson-type phase shift method, a phase shifter can be arranged and designed with good efficiency and an integration density can be enhanced. CONSTITUTION:In the manufacturing method of a semiconductor memory device provided with a cell array composed of a plurality of memory cells, the memory cells are cells manufactured by a process wherein element isolation regions and element regions 1 to 10 other than them are formed on a semiconductor substrate and, when patterns for the element regions 1 to 10 are exposed by using a phase shift method, a phase shifter 11 is arranged and designed in such a way that phases of light coming from opening parts adjacent in a direction (direction of bit line) in which the size of an element region pattern is short are always opposite.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a semiconductor memory device having an improved design method when a pattern of a highly integrated memory cell or the like is formed by exposure by a phase shift method. Manufacturing method.

[0002]

2. Description of the Related Art In recent years, semiconductor circuit elements have been miniaturized at an extremely high speed. For example, in DRAM, the area is reduced by the miniaturization, and further high integration is further advanced. The miniaturization of this element is largely dependent on the lithography technique, and in particular, the phase shift method is indispensable in order to increase the resolution and process a fine pattern while securing a certain depth of focus. Among the phase shift methods, the Levenson-type phase shift method is one of the methods that is most improved in resolution and depth of focus.

FIG. 13 is a diagram showing the principle of the Levenson type phase shift method. In this technique, by arranging a phase shifter on one of the adjacent openings on the exposure mask, the phases of the light emitted from the adjacent openings are shifted by 180 degrees and the phases are opposite to each other. This is a technology that makes it possible to process a finer pattern than the conventional exposure method by utilizing the interference of. Therefore, when using the Levenson type phase shift method,
It can be seen that in order to make the best use of this ability, the arrangement of the phase shifter must be devised so that the phases of the light emitted from the adjacent openings on the exposure mask are always reversed.

From the above, when designing a device such as a DRAM using the Levenson-type phase shift method, it is a policy to always reverse the relation between the presence and absence of a phase shifter between adjacent patterns. Must. That is, it may be designed so that the pattern without the phase shifter is located next to the pattern with the phase shifter. Hereinafter, if the presence / absence of the phase shifter is reversed between the adjacent patterns, the arrangement of the phase shifters between the adjacent patterns is called a normal arrangement, and if not, it is called an abnormal arrangement. FIG. 14 is a diagram showing an example of a normal arrangement and an abnormal arrangement.

However, in an actual device such as a DRAM, not only a simple line-and-space pattern but also an irregular pattern such as an isolated pattern exists. It is difficult to make a completely normal arrangement between matching patterns. Especially in row decoders and sense amplifiers, there is generation and disappearance of wiring, that is, word lines or bit lines.
In addition, an isolated pattern is inserted between the wirings for the reason that a potential is applied to the electrode of the transistor.

At this time, if it is possible to finish the attachment of the phase shifter in the middle of the pattern, it is possible to always reverse the phase to avoid an abnormal arrangement, but to finish the attachment of the phase shifter in the middle. It is impossible because there is a slit in the finished pattern,
Complicating the problem is that once the phase shifter is attached, it must be kept attached to the end.

FIG. 15 shows a conventional example in which a phase shifter is arranged in the pattern of the bit lines of the memory cell array and the sense amplifier section. In this case, due to the existence of the isolated pattern 16 in the sense amplifier section, it is impossible to completely arrange the phase shifter 11 between all the adjacent patterns 12. For example, bit lines BL1 and B
Regarding L2, BL2 and BL3, the arrangement of the phase shifter 11 is the normal arrangement, but BL3 and BL
Regarding No. 4, the cell array section is in an abnormal arrangement. Therefore, although the Levenson-type phase shift method is adopted, the ability of the Levenson-type phase shift method cannot be utilized to the maximum due to its abnormal arrangement.
Therefore, it becomes difficult to process a fine bit line pattern, and it becomes difficult to obtain a highly integrated memory.

FIG. 16 shows a conventional example in which phase shifters are arranged in the pattern of the element region in the memory cell array.
Also in this case, it is impossible to completely arrange the normal patterns between all the adjacent patterns. For example, in the element regions 1 and 2 and the element regions 2 and 6, the phase shifters 11 are arranged in the normal arrangement. However, the element regions 2 and 3 and the element regions 2 and 5 are in an abnormal arrangement,
Despite adopting the Levenson type phase shift method, it is difficult to process a fine element region pattern.

FIG. 17 is an example of a pattern in a memory cell array. In the memory cell array, word lines WL,
The patterns of the bit line BL and the element region A are densely packed,
This is one of the factors that determine the size of one bit of the memory cell. Therefore, if a partial abnormal arrangement exists in the memory cell array as in the conventional example of FIGS. 15 and 16, even if the Levenson-type phase shift method is adopted, the area of the memory cell array will be increased due to the existence of the partial abnormal arrangement. It turns out that it becomes difficult to reduce.

Generally, in a 64-Mbit DRAM chip, the memory cell array occupies about 60% of the chip area. For this reason, if it is difficult to reduce the area of the memory cell array as in the conventional example, even if the Levenson type phase shift method is adopted, the effect of reducing the area is small as a result.

FIG. 18 shows a conventional example in which a phase shifter is arranged in a bit line pattern of a memory cell array and a row decoder. In this example, the normal arrangement is preferentially set to the area where the isolated pattern exists in the row decoder. In this case, due to the existence of the isolated pattern, it is impossible to completely arrange the phase shifter between all the adjacent patterns.
In other words, in the region where the isolated pattern exists in the row decoder, all the wirings are in the normal arrangement, but in the memory cell array, WL1 and WL2 are in contact with each other, and there is the abnormal arrangement there. Therefore, even though the Levenson-type phase shift method is adopted, the ability of the Levenson-type phase shift method cannot be utilized to the maximum due to the abnormal arrangement, and it becomes difficult to process a fine word line pattern. It becomes difficult to obtain a highly integrated memory.

FIG. 19 shows a conventional example in which phase shifters are arranged in the pattern of word lines of the memory cell array and row decoder. In this example, unlike FIG. 18, DRA
The normal arrangement is preferentially arranged in the memory cell array which occupies a large proportion of the M chip area. Even in this case, due to the existence of the isolated pattern in the row decoder, it is impossible to completely arrange the phase shifter between all the adjacent patterns. That is, all the WLs are in the normal arrangement in the memory cell, but in the row decoder, WL2 and WL4 are in contact with each other because WL3 disappears in the middle, so that there is an abnormal arrangement. . Further, since an isolated pattern is generated between WL1 and WL2, an abnormal arrangement is provided between WL1 and the isolated pattern. Therefore, similarly to the example of FIG. 18, the Levenson-type phase shift method cannot be fully utilized.

[0013]

As described above, the conventional DR
When exposing a memory cell pattern such as AM using the Levenson-type phase shift method, the phase shifter cannot be efficiently arranged and designed, which is a factor that hinders improvement in the integration degree of the memory cell. Further, the above problem is not limited to the memory cell and is the same in the peripheral circuits such as the row decoder and the sense amplifier.

The present invention has been made in consideration of the above circumstances, and an object thereof is to efficiently use a phase shifter when exposing a memory cell pattern of a DRAM or the like by using the Levenson type phase shift method. It is an object of the present invention to provide a method of manufacturing a semiconductor memory device which can be arranged and designed and can contribute to improvement of integration and the like.

[0015]

The essence of the present invention is DRA.
A bit line that restricts pattern miniaturization in a memory cell array that occupies a large proportion of the memory area such as M.
This is to design the word line, the element region, and the like (particularly the element region) so as to have the optimum phase shifter arrangement for the Levenson-type phase shift method.

That is, the present invention (claim 1) is a method for manufacturing a semiconductor memory device having a cell array composed of a plurality of memory cells, wherein the memory cells include an element isolation region and other element regions on a semiconductor substrate. Is a cell that is manufactured through the step of providing a pattern of the element region using the phase shift method, and on the exposure mask, the size of the element region pattern It is characterized by being designed so that the phases are always opposite.

According to a preferred embodiment of the present invention, in order to maximize the effect of the phase shift method when processing the bit line, the light emitted from the adjacent openings on the exposure mask in the cell array section is used. Design so that the phases are always opposite. Similarly, in order to maximize the effect of the phase shift method when processing the word lines, in the cell array section, the phase of the light emitted from the adjacent openings on the exposure mask is always reversed. To do.

According to the present invention (claim 2), there is provided a cell array having memory cells provided at respective intersections of a plurality of bit lines and a plurality of word lines, and a peripheral circuit provided adjacent to the cell array. A method of manufacturing a semiconductor memory device provided, wherein when processing a wiring layer used for a bit line or a word line in a peripheral circuit, the phases of light emitted from adjacent openings on an exposure mask are always opposite to each other. As described above, when a pattern is newly generated and deleted, the pattern is arranged in pairs every two times.

In a preferred embodiment of the present invention, a predetermined space between word lines is reserved in the row decoder as one of the peripheral circuits in case a new isolated pattern is generated, and the space is reserved there. Other than that, the isolated pattern is not arranged. Similarly, in the sense amplifier, a space between predetermined bit lines is reserved in preparation for a new isolated pattern, and the isolated pattern is not arranged in other areas.

[0020]

When the element regions of the memory cell are arranged in an island shape, it is impossible to arrange all the element regions in the normal arrangement. In the Levenson-type phase shift method, the resolution of these patterns can be increased by making one phase of the adjacent openings different from the phase of the other by 180 degrees. The effect is great. Therefore, as in the present invention (Claim 1), the openings adjacent to each other in the direction in which the element region pattern has a long dimension have an abnormal arrangement, and the openings adjacent to each other in the direction with a short element region pattern have a normal arrangement. This makes it possible to maximize the effect of the Levenson-type phase shift method.

Further, by preferentially arranging the optimum phase shifter for the Levenson-type phase shift method in a memory cell array that occupies a large proportion of the area of a memory such as DRAM, the area can be efficiently reduced, and eventually the degree of integration can be increased. Will be easier. As a result, even if it becomes difficult to arrange the optimum phase shifter for the Levenson-type phase shift method in the row decoder, the sense amplifier, etc., in which the pattern of the wiring or the like is directly connected to the memory cell array, it becomes difficult to reduce the area. Since the area occupies a smaller proportion of the entire area than the memory cell array, the influence is small.

Further, if the generation and extinction of the patterns are always performed in pairs, which is originally the normal arrangement, the abnormal arrangement does not newly appear. Therefore, as in the present invention (claim 2), a pattern is generated,
By always arranging the patterns in pairs in order to eliminate them, it is possible to maximize the performance of the Levenson-type phase shift method, and it becomes possible to process fine row decoders and sense amplifiers and to achieve high integration. It is easy to get memory.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment in which a phase shifter is arranged in a pattern of an element region in a memory cell array according to the present invention. In the figure, 1 to 10 indicate element regions, 1
Reference numeral 1 indicates a phase shifter.

In this embodiment, the element region has a rectangular shape, but all the phase shifter arrangements are normal arrangements in the short side direction. On the other hand, the phase shifter arrangement is an abnormal arrangement in the long side direction.

Here, the reason why the short side direction in the island pattern is normal arrangement and the long side direction is abnormal arrangement will be described. Considering the two-dimensional intensity distribution of light passing through the island pattern on the exposure mask, the intensity generally becomes weak at the corners of the rectangle. Therefore, considering the adjacent side between the patterns adjacent to each other in the long side direction (bit line direction), the average light intensity is weak due to the above two-dimensional effect in addition to the short length. On the other hand, in the adjacent side between the patterns adjacent in the short side direction (word line direction), the length is long and the average light intensity is strong. Therefore, the resolution will be better if all of them are in the normal arrangement.

2A and 2B show the above-described state. FIG. 2A is a two-dimensional distribution of the light intensity in the opening 12, and FIG. 2B is the adjacent portion (light-shielding portion 13) in the short side direction (BB 'cross section). under)
And (c) shows the intensity distribution of the adjacent portion (below the light shielding portion 13) in the long side direction (AA ′ cross section).

As described above, according to the present embodiment, the effect of the Levenson-type phase shift method can be maximized by arranging the patterns adjacent to each other in the short side direction where the light intensity distribution is large, in the normal arrangement. The pattern of the memory cell can be exposed with high resolution. Therefore, DRA
It is possible to miniaturize and highly integrate the memory cell array such as M. The present invention can be applied not only to the element region but also to an island pattern such as a contact.

FIG. 3 shows a second embodiment in which the present invention is applied to a 1/4 pitch array type element region pattern. Also in this embodiment, as in the first embodiment, the phase shifter arrangement is all normal in the short side direction of the element region, and the phase shifter arrangement is abnormal in the long side direction.

In this embodiment, the adjacent patterns have a greater overlap in the short-side direction than in the long-side direction, so the above phase shifter arrangement is desirable.

FIG. 4 shows a third embodiment in which a phase shifter is arranged in the bit line pattern of the memory cell array and the sense amplifier section according to the present invention. In this example,
BL1 and BL2, BL2 and B in the cell array region
The phase shifter arrangement is a normal arrangement between all bit lines such as L3. Therefore, the capacity of the phase shift method can be utilized to the maximum in the cell array region, and it becomes easy to process a fine bit line pattern, and as a result, it becomes easy to obtain a highly integrated memory.

In this case, the phase shifter arrangement is optimally performed for the memory cell array, so that the sense amplifier portion has an abnormal arrangement. Therefore, the sense amplifier unit may be devised such as widening the interval between the patterns. Here, since the area occupied by the sense amplifier section is smaller than the area occupied by the cell array, an increase in the area of the sense amplifier section causes almost no problem.

FIG. 5 shows a fourth embodiment in which phase shifters are arranged in the pattern of word lines in the memory cell array according to the present invention. In this embodiment, since word line shunting is performed, every other word line disappears in the shunt region.

According to the present invention, all the phase shifter arrangements are normal arrangements in the memory cell array. on the other hand,
In the shunt area, WL1 and WL3 and WL3 and WL5
The phase shifter arrangement is an abnormal arrangement. However, in this case, since the pattern interval is wide in the shunt region, it is possible to sufficiently cope with this, and there is no problem in reducing the area of the memory cell. As a result, it can be seen that by adopting the phase shift method, it becomes easy to process a fine word line pattern even when performing a word line shunt.

FIG. 6 shows the case of performing the bit line twist.
It is a fifth embodiment in which a phase shifter is arranged in a bit line pattern according to the present invention. In the figure, 11 is a phase shifter, 14 is a second layer poly Si, and 15 is an interlayer contact between the second layer poly Si and the bit line poly Si.

According to the present invention, all the phase shifter arrangements of the bit lines in the memory cell array are normal arrangements. On the other hand, in the twist region, the phase shifter arrangement is abnormal, such as BL1 and / BL1 near the center. However, since the area of the twist region is generally smaller than the area of the memory cell array, there is almost no problem with respect to the area reduction even if the interval between the patterns is widened to cope with the abnormal arrangement in comparison with the normal arrangement. .

FIG. 7 shows a sixth embodiment in which the phase shifters are arranged in the word line pattern of the memory cell array and the row decoder section according to the present invention. In the figure, the unhatched portions are patterns in which shifters are not arranged, and the hatched portions are patterns in which shifters are arranged.

In the case of this embodiment, WL1, WL2 and WL
The phase shifter arrangement is a normal arrangement between all bit lines such as 2 and WL3. Even if the termination of WL which is a concern occurs, for example, between WL2 and WL5, WL3 and W
The appearance of abnormal arrangement is avoided by eliminating L4 in pairs at the same time. Between WL5 and WL7, WL6 disappears and three new patterns appear. The generation and disappearance of this set of four is 2
It is considered to be an extension of the case of one set, and in fact, the abnormal arrangement does not appear anywhere.

As a result of the above, by avoiding the abnormal arrangement, the ability of the phase shift method can be utilized to the maximum, and the fine word line pattern can be easily processed, resulting in high integration. It will be easier to get the memory. In this case, the optimum phase shifter arrangement, that is, the completely normal arrangement is adopted for the memory cell array.

As described above, according to the present embodiment, two sets of adjacent patterns (two without a shifter and one with a shifter) are set when the pattern is generated and deleted in the completely normal arrangement. By arranging the patterns as, it is possible to prevent the abnormal layout from newly appearing. Therefore, the word line pattern in the row decoder can be arranged in a completely normal arrangement, and the row decoder can be formed by maximizing the performance of the Levenson-type phase shift method. It should be noted that since patterns are generated and erased in pairs, useless patterns (dummy patterns) may be arranged, but the integration degree is improved by perfect normal arrangement rather than the reduction in integration degree due to the existence of dummy patterns. Is a sufficiently large total effect.

FIG. 8 shows a seventh embodiment in which the phase shifters are arranged in the word line pattern of the memory cell array and row decoder section according to the present invention. In this case, the phase shifter arrangement is a normal arrangement between all bit lines such as WL1 and WL2, WL2 and WL3, as in FIG.
Therefore, the capability of the phase shift method can be utilized to the maximum, and the processing of fine word line patterns becomes easy.

FIG. 9 shows an eighth embodiment in which a phase shifter is arranged in the pattern of word lines in the memory cell array and row decoder section according to the present invention. Also in this case, FIG.
Similarly, the phase shifter arrangement is a normal arrangement between all bit lines such as WL1 and WL2, WL2 and WL3, and so on. Therefore, the capability of the phase shift method can be utilized to the maximum, and the processing of fine word line patterns becomes easy.

FIG. 10 shows an eighth embodiment in which a phase shifter is arranged in the bit line pattern of the memory cell array and the sense amplifier section according to the present invention. In this case,
As shown in 0 (a), an isolated pattern appears between BL1 and BL2, but the phase shifter arrangement is the normal arrangement between all the patterns, and there is no abnormal arrangement. Therefore, the capability of the phase shift method can be utilized to the maximum extent, the processing of fine bit line patterns is facilitated, and as a result, it is easy to obtain a highly integrated memory.

Incidentally, FIG. 10B shows an arrangement example of the phase shifters formed on the actual exposure mask. The hatched portion is a thin film that serves as a phase shifter, and the phase shifter thin film is formed so as to cover the pattern to be arranged in the shifter among the patterns that serve as the light transmitting portion.

FIG. 11 shows a ninth embodiment in which phase shifters are arranged in the bit line pattern of the memory cell array and the sense amplifier section according to the present invention. Also in this case, as shown in FIG. 11A, an isolated pattern appears between BL1 and BL2, and the pattern is the same as that in FIG. 10A. However, in this embodiment, as shown in FIG. 11B, the arrangement of the phase shifter is not the Levenson type phase shift method but the shifter edge utilization type.

The bit lines can be formed by using the shifter edge type, but the advantage of this embodiment is that the formation of the isolated pattern is performed by the shifter edge type while the bit lines are formed by the Levenson type phase shift method. Is where it is possible to do in.

Also in this embodiment, the phase shifter arrangement is the normal arrangement between all the patterns.
There is no abnormal arrangement. Therefore, as in the eighth embodiment, the capability of the phase shift method can be utilized to the maximum.

FIG. 12 shows a first arrangement in which phase shifters are arranged in the word line pattern of the row decoder section according to the present invention.
0 is an example. In this case, the appearance of isolated patterns is limited between WL2 and WL3. Therefore, FIGS.
The pattern is simpler than the pattern 1. Therefore,
Pattern design is easier. Moreover, since the generation of the pattern accompanies the disappearance of the pattern, the phase shifter arrangement is the normal arrangement among all the patterns, and there is no abnormal arrangement.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Although the row decoder and the sense amplifier are described as the peripheral circuits in the embodiments, the present invention can be applied to various peripheral circuits arranged around the memory cell array and connected to bit lines and word lines.

[0050]

As described above in detail, according to the present invention, the phase shifter is arranged in the normal arrangement in the short side direction of the element region.
By arranging abnormally in the long side direction, DRA
When a memory cell pattern such as M is exposed by using the Levenson-type phase shift method, a phase shifter can be efficiently arranged and designed, and a method of manufacturing a semiconductor memory device that can contribute to improvement of integration degree is realized. be able to.

Further, according to the present invention, when the patterns are newly generated and disappeared, the patterns are always arranged in a set of two, whereby the complete normal arrangement of the phase shifter can be realized, and the Levenson type phase can be realized. It is possible to maximize the capabilities of the shift method.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment in which a phase shifter is arranged in a pattern of an element region in a memory cell array,

FIG. 2 is a diagram showing a two-dimensional distribution of light intensities and intensity distributions in short-side and long-side directions in the first embodiment,

FIG. 3 is a diagram showing a second embodiment in which phase shifters are arranged in a 1/4 pitch array type element region pattern;

FIG. 4 is a diagram showing a third embodiment in which a phase shifter is arranged in a bit line pattern of a memory cell array and a sense amplifier section;

FIG. 5 is a diagram showing a fourth embodiment in which a phase shifter is arranged in a pattern of word lines in a memory cell array,

FIG. 6 is a fifth diagram in which a phase shifter is arranged in a bit line pattern according to the present invention when performing a bit line twist.
FIG.

FIG. 7 is a diagram showing an embodiment in which a phase shifter is arranged in a word line pattern of a memory cell array and a row decoder section,

FIG. 8 is a diagram showing an embodiment in which a phase shifter is arranged in a pattern of word lines of a memory cell array and a row decoder part,

FIG. 9 is a diagram showing an embodiment in which a phase shifter is arranged in a pattern of word lines of a memory cell array and a row decoder part,

FIG. 10 is a diagram showing an embodiment in which a phase shifter is arranged in a pattern of bit lines of a memory cell array and a sense amplifier,

FIG. 11 is a diagram showing an embodiment in which a phase shifter is arranged in a pattern of bit lines of a memory cell array and a sense amplifier,

FIG. 12 is a diagram showing an embodiment in which a phase shifter is arranged in a word line pattern of a row decoder section,

FIG. 13 is a diagram showing the principle of the Levenson-type phase shift method,

FIG. 14 is a diagram showing a normal arrangement and an abnormal arrangement,

FIG. 15 is a diagram showing a conventional example in which a phase shifter is arranged in a pattern of bit lines of a memory cell array and a sense amplifier part,

FIG. 16 is a diagram showing a conventional example in which a phase shifter is arranged in a pattern of an element region in a memory cell array,

FIG. 17 is a diagram showing an example of a pattern in a memory cell array.

FIG. 18 is a diagram showing a conventional example in which a phase shifter is arranged in a bit line pattern of a memory cell array and a row decoder,

FIG. 19 is a diagram showing a conventional example in which a phase shifter is arranged in a bit line pattern of a memory cell array and a row decoder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1-10 ... Element area | region, 11 ... Phase shifter, 12 ... Opening part (pattern), 13 ... Light-shielding part, 14 ... 2nd layer poly Si, 15 ... Interlayer contact, 16 ... Isolation pattern, BL ... Bit line, WL ... Word line,

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor memory device having a cell array composed of a plurality of memory cells, wherein the memory cell is manufactured through a step of providing an element isolation region and other element regions on a semiconductor substrate. The cell is a cell, and when the pattern of the element region is exposed by using the phase shift method, the phase of the light emitted from the adjacent openings in the direction in which the dimension of the element region pattern is short on the exposure mask is always opposite. And a semiconductor memory device manufacturing method. 2. A cell array in which a memory cell is provided at each intersection of a plurality of bit lines and a plurality of word lines,
A method of manufacturing a semiconductor memory device, comprising: a peripheral circuit provided adjacent to a cell array, wherein a wiring layer used for the bit line or word line in the peripheral circuit is processed on an exposure mask. 2. A method of manufacturing a semiconductor memory device, wherein patterns are always arranged in pairs when a new pattern is generated and erased so that the phases of light emitted from adjacent openings are always opposite to each other.