JPH0685200A - Semiconductor device provided with triple well structure - Google Patents

Abstract

PURPOSE: To restrain power supply noises from affecting a memory cell array and a peripheral region so as to prevent a memory device from malfunctioning, by a method wherein the memory device is possessed of a triple-well structure where a power supply is separately fed. CONSTITUTION: Only the well bias of a P well 23 in a memory cell array region 100 is set at a negative voltage VBB, and the well bias of a P well 24 in a peripheral circuit region 400 is set at a grounding voltage VSS. The well biases of N wells 22 and 25 in the memory cell array region and the peripheral circuit region are set at a power supply voltage VCC. When a negative voltage VBB is supplied to the P well 23 in the memory cell array region 100, a junction between the P well and an N<+> diffusion region which serves as the drain region of a sense amplifier MOS transistor 31 is reversely biased, so that bit lines are lessened in capacitance, and noise troubles caused by mutual interference can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a triple well structure.

[0002]

2. Description of the Related Art The capacity of a semiconductor memory device is 4 every few years.
The structure and process technology of a new memory device have been proposed in the midst of increasing the capacity and increasing the integration. For example, in a 4 Mbit class memory device, in order to increase the capacity in a limited area, a memory cell array or the like has a three-dimensional structure, and after becoming a 16 Mbit class or higher memory device, it is integrated in a memory. MOS
With the miniaturization of transistors, low level internal power supply voltage is being used. Along with this, it becomes necessary to further consider the noise problem caused by structural reduction in the memory device, and further, a memory cell structure suitable for realizing a high-speed access time with low power and high integration. Construction of is also required at the same time.

FIG. 18 shows a schematic structure of a 64 Mbit class DRAM. The semiconductor memory device shown in FIG.
16 Mbit memory cell array regions 100, 11
0, 120, 130 and row decoder / word line driver regions 30 arranged one by one on the center line of the memory device.
0, 310, and four column decoder areas 200, 210, 220 corresponding to the memory cell array areas, respectively.
230, and a peripheral circuit region 400 and pad regions 500 and 510 arranged in the central portion.

A plurality of memory cells, word lines and bit lines, and sense amplifiers are integrated in the memory cell array region 100, and TTL level input buffers, data output buffers, and output drivers are integrated in the peripheral circuit region 400. . Row decoder / word line driver area 30
The circuits 0 and 310 are provided with a circuit for generating a word line drive clock. These circuits are CMOS composed of a plurality of NMOS transistors and PMOS transistors.
It is a circuit and is formed from a large number of wells, diffusion regions, and the like formed on one substrate (or wafer).

19 to 22 show the memory cell array region 1
00 and the peripheral circuit region 400, a representative example of the circuits respectively present. The bit line system circuit shown in FIG. 19 includes bit line equalization circuits 50 and 60, memory cells 51 and 61, N type sense amplifier 52 and P type sense amplifier 62, isolation gates 53 and 63, column gate 55, word line WL1, W
It is composed of L2, bit line BL, and bar BL.

Bit line system circuit of FIG. 19, row decoder / word line drive clock generation circuit of FIG. 20, RA of FIG.
The equivalent circuit configuration of the TTL input buffer for S and the data output buffer / driver of FIG. 22 is already known. However, the transistors 86, 87, 88 to which the back gate voltage V _BB shown in FIGS. 21 and 22 is applied.
The part relating to is the part relating to the present invention.

In manufacturing a memory device as shown in FIG. 18, when the substrate is a P type, a PMOS transistor is formed in the N well and an NMOS transistor is formed in the substrate. In this case, the substrate is supplied with a substrate bias of a predetermined level (usually the ground voltage), and the N well is provided with a back gate voltage (a MOS transistor is formed in the N well in order to maintain the threshold voltage of the transistor). Therefore, it may be referred to as “back gate voltage” or may be referred to as “well bias” in the sense of a bias voltage directly applied to a well. In the following, both are the same. . On the other hand, when the substrate is N type, a back gate voltage of a predetermined level is supplied to the P well in order to adjust the threshold voltage of the NMOS transistor formed in the P well. Regarding the back gate voltage, in Korean Patent Application No. 86-6557, in order to prevent data leakage due to a difference in threshold voltage between a word line driving transistor and a cell transistor, a cell transistor is used. A technique of supplying a back gate voltage of a predetermined level to the formed P well is disclosed.

When a memory device is highly integrated (at least 16 Mbit or more), many wells are formed in a substrate, and a well bias (or a back gate voltage of a transistor) required according to the application of a corresponding device is generated. Is set. FIG. 23 shows a well bias application state in the memory cell array region and the peripheral circuit region. The triple well structure consisting of N ⁺ / P / N as shown in the figure is "A 45ns
16Mbit DRAM with Triple-Well Structure "IEEE JSS
C., vol. 24, no. 5, Oct. 1989, pp. 1170-1174. P in the N well 22 in the memory cell array region 100
An NMOS transistor 31 formed in the well 23,
The PMOS transistors 32 formed in the N well 22 are transistors that form N-type and P-type sense amplifiers in the memory cell array region 100, respectively. Further, the N formed in the P well 24 in the peripheral circuit region 400.
The MOS transistor 33 and the PMOS transistor 34 formed in the N well 25 are transistors existing in the TTL input buffer and the data output driver, respectively.

For circuits corresponding to the sectional structure of FIG. 23, refer to FIGS. In the memory cell array region 100, the well bias electrode 2 of the P well 23
6 (or the back gate electrode of the NMOS transistor 31) is applied with the ground voltage V _SS or the negative voltage V _BB , and the well bias electrode 27 of the N well 22 (or the back gate electrode of the PMOS transistor 32) is supplied with the power supply voltage V _CC is applied. In the peripheral circuit region 400, the P well 2
The ground voltage V _SS or the negative voltage V _BB is applied to the well bias electrode 28 (or the back gate electrode of the NMOS transistor 33) of No. 4 and the well bias electrode 29 of the N well 25 (or the back gate electrode of the PMOS transistor 34). ) Is applied with the power supply voltage V _CC . The electrode 30 of the P-type substrate 21 is grounded. The P well 23 is formed by the N well 22 formed in the memory cell array region 100.
And the P-type substrate 21 are electrically separated from each other, and interference between well biases set in the respective wells is eliminated. This is an advantage of using triple wells in highly integrated memory devices.

However, the above conventional techniques have the following problems. First, P wells 23 and 2
When the ground voltage V _SS is applied to the well bias electrodes 26 and 28 of No. 4, since the bit line is mostly on the P well region in the memory cell array region, the capacitance of the bit line becomes large and the bit line capacitance is increased. This has the adverse effect of increasing the ratio C _B / C _S between C _B and the capacitance C _S of the storage capacitor of the memory cell. That is, the NMOS transistor 3 formed in the P well 23 in the memory cell array region
A bit line is connected to the N ⁺ diffusion region serving as the drain of 1 (which constitutes a current mirror type N type sense amplifier) (see the N type sense amplifier 52 in FIG. 19). It is a well-known fact in the technical field of the present invention that the time for reading data from the memory cell is delayed when the capacitance becomes relatively large as compared with the capacitance of the storage capacitor. Further, since the common ground voltage is supplied to both the P well in the peripheral circuit region and the P well in the memory cell array region, noise generated from the ground voltage in the peripheral circuit region interferes with the ground voltage in the memory cell array region. Therefore, it may cause deterioration of circuit operation characteristics in the memory cell array.

Secondly, when a negative voltage V _BB is applied to the well bias electrodes 26 and 28 of the P wells 23 and 24, the transistors in the peripheral circuit region have short channels for high integration. The threshold voltage has dropped,
Therefore, the latch-up phenomenon is likely to occur before the negative voltage V _BB output from the negative voltage generating circuit reaches a predetermined normal level. In the memory device, the negative voltage generated from the separate negative voltage generation circuit is not almost constant like the power supply voltage or the ground voltage (of course, the power supply voltage and the ground voltage may vary somewhat due to external influences). ),
It is necessary to make a correction by an oscillator or a charge booster so as to maintain a predetermined normal level by continuous feedback. If this negative voltage is at a normal level, the latch-up phenomenon can be suppressed, but when the distance from the predetermined level is increasing or the process of returning to the predetermined level, the parasitic elements existing in the substrate should be driven. It cannot be suppressed, and the above-mentioned latch-up phenomenon is induced to cause a malfunction of the memory device.

[0012]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the influence of power supply noise between a highly integrated semiconductor device having a memory cell array region and a peripheral circuit region in one memory device. An object of the present invention is to provide a device capable of preventing the malfunction of the device. Another object of the present invention is to provide a highly integrated semiconductor device having a large number of wells, which can surely realize electrical insulation between a substrate or wells.

[0013]

In order to achieve the above object, the present invention is integrated on one first conductivity type substrate, and includes a plurality of word lines, bit lines, memory cells, sense amplifiers, and row lines. In a semiconductor device including a memory cell array region having a decoder and a word line driver, and a peripheral circuit region having a TTL input buffer and a data output driver, a first memory cell array region is provided.
Power supply pad group, second power supply pad group for peripheral circuit area, third power supply pad group for word line and TTL input buffer, fourth power supply pad group for data output driver, and second power supply pad group for memory cell array area A first conductivity type substrate and having at least a first well of the first conductivity type therein,
The first well of the second conductivity type connected to the first power supply pad group and the second well of the first conductivity type in the peripheral circuit region, and having at least the second well of the first conductivity type therein; A second well of the second conductivity type connected to the power supply pad group; a second conductivity type MOS transistor formed in the first well of the first conductivity type and connected to the third power supply pad group; Formed in the second well of the first conductivity type,
Second conductivity type MOS connected to the fourth power supply pad group
And a transistor.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. 2 to 4 are examples showing the application state of the well bias (or back gate voltage) according to the present invention on the same sectional structure as FIG. In addition, common portions are denoted by the same reference numerals, and overlapping description will be omitted.

In FIG. 2, the memory cell array region 10
Only the well bias of the P well 23 of 0 is set to the negative voltage V _BB, and the well bias of the P well 24 of the peripheral circuit region 400 is set to the ground voltage V _SS . The well bias of the N wells 22 and 25 in the memory cell array and the peripheral circuit area is set to the power supply voltage V _CC . When the negative voltage V _BB is supplied to the P well 23 in the memory cell array region 100 as described above, the junction between the N ⁺ diffusion region serving as the drain of the sense amplifier NMOS transistor 31 and the P well is reversely biased, and thus the bit line. Capacity is reduced, resulting in a decrease in the aforementioned C _B / C _S ratio. In addition, the peripheral circuit area 4
00 and the well bias applied to both P wells of the memory cell array region 100 are the ground voltage V _SS and the negative voltage V _BB , respectively, so that the above-mentioned noise problem due to mutual interference can be prevented. In addition, P in the peripheral circuit area 400
Since the ground voltage V _SS is applied to the well 24, the conventional latch-up phenomenon due to the short channel is suppressed.

In FIG. 3, the power supply voltage V _CC is applied to the N well 25 of the peripheral circuit region 400, the ground voltage V _SS or the negative voltage V _BB is applied to the P well 24, and the N well of the memory cell array region 100 is applied. A voltage V _PP higher than the power supply voltage V _CC generated by the high voltage generation circuit in the memory device (hereinafter referred to as “boosted voltage”) V _PP is applied to the P-well 22.
A ground voltage V _SS or a negative voltage V _BB is applied to. In this way, noise generated at the power supply voltage V _CC of the peripheral circuit area 400 does not affect the memory cell array area.

In FIG. 4, N in the peripheral circuit area 400 is
A power supply voltage V _CC or an internal voltage (hereinafter referred to as “internal voltage”) V _INT lower than the power supply voltage is applied to the well 25, and a ground voltage V _SS or a negative voltage V _BB is applied to the P well 24. Then, the internal voltage V _INT is applied to the N well 22 of the memory cell array region 100, and the ground voltage V _SS or the negative voltage V _BB is applied to the P well 23. Even in this case,
The effect as shown in FIG. 3 can be obtained.

The above-described embodiments of the present invention shown in FIGS. 2 to 4 are intended to eliminate the interference effect between power sources by selectively setting the well bias and adjusting the application state. In FIGS. 5 and 6 described below, wells of the same conductivity type are separated from each other, and at the same time, wells of the same conductivity type as the substrate are prevented from being short-circuited with the substrate.

FIG. 5 shows an application example in the memory cell array region. In FIG. 5, two N's are formed in the P-type substrate 70.
The wells 71 and 72 are isolated from each other, and in the N well 71, a P well 73 in which an NMOS transistor 74 forming an N type sense amplifier in the memory cell array region is formed is formed. On the other hand, the PMOS transistor 75 formed in the N well 72 is a transistor forming a P-type sense amplifier in the memory cell array region. A negative voltage V _BB is applied as a well bias (or back gate voltage) to the P well 73, and the boosted voltage V _PP is applied to the N well 71 surrounding the P well 73.
Alternatively, the internal voltage V _INT is applied, and the power supply voltage V _CC is supplied to the other N well 72 isolated from the N well 71. Since the boosted voltage V _PP or the internal voltage V _INT that is not the power supply voltage V _CC is applied to the N well 71 and the N wells are isolated from each other, the well of the P well 73 is resistant to noise induced by the power supply voltage. Bias does not interfere and stable operation is possible.

FIG. 6 shows an application example in the peripheral circuit area. In FIG. 6, the N well 81 surrounds the P well 83 in which the NMOS transistor 86 is formed,
P well 84 in which S transistors 87 and 88 are formed
Is surrounded by an N well 82 isolated from the N well 81. The transistor 86 is the TT existing in the peripheral circuit area.
It is an NMOS transistor in the L input buffer (see FIG. 21). The transistors 87 and 88 are NMOS transistors in the data output buffer (or output driver: see FIG. 22) in the peripheral circuit area.
The back gate voltage of the NMOS transistor (or the well bias of the P well) is a negative voltage V _BB , and the P wells 83 and 84 are separated from the substrate 70 by the N wells 81 and 82, respectively. And N wells 81 and 8
2 the power supply voltage V _CC, respectively is applied to the power supply voltage V _CC applied to the N well is supplied from the power supply pads separated from each other.

FIG. 7 shows an arrangement of power supply pads of a memory device as a means for achieving the object of the present invention. In general, the power pad used in the memory device uses one power voltage pad and one ground voltage pad.
When noise is generated in the power supply used for the peripheral circuits, it also interferes with the memory cell array region and adversely affects it. Therefore, in the present invention as shown in FIG. 7, the power supply voltage V _CC
And dividing the ground voltage V _SS to the memory cell array and for the peripheral circuit, respectively, further distinction is made between the use right for the left side of the figure, the left power supply voltage pad memory cell array (V _CCLA), the right supply voltage for the memory cell array Pad (V _CCRA ), memory cell array left ground voltage pad (V _SSLA ), memory cell array right ground voltage pad (V _SSRA ), peripheral circuit left power supply voltage pad (V _CCLP ), peripheral circuit right power supply voltage pad ( V _CCRP ), left ground voltage pad for peripheral circuits (V _SSLP ), right ground voltage pad for peripheral circuits (V _SSRP )
Placed as. Further, the ground voltage pads for word lines / TTL input buffers are respectively arranged on the left and right, and the left ground voltage pads for word lines / TTL input buffers (V
_SSLQ ), right line ground voltage pad (V _SSRQ ) for word line / TTL input buffer. Further, a power supply voltage pad (V _CCRD ) and a ground voltage pad (V _SSRD ) for driving data output are separately provided. This is a structure for preventing adverse effects due to power supply noise or the like expected when the power supply pads are commonly used from reaching other areas using the same power supply pad.

A preferred embodiment of the present invention which can be adopted in a memory device as shown in FIG. 18 will be described with reference to FIG. 1 by integrating the partial embodiments shown in FIGS. . 2 to 7 in the following description and FIG.
The same reference numerals are given to the same parts as in the inside. At the same time, refer also to FIGS.

In FIG. 1, a memory cell array region 100 of a P-type semiconductor substrate 70 has a first N well 22 and a second N well 91 isolated from each other, and a peripheral circuit region 4
00 has a third N well 25, a fourth N well 81, a fifth N well 82 and a first P well 24 which are separated from each other. A second P well 23 and a first P well 23 are provided in the first N well 22.
There is a MOS transistor 32, and there is a first NMOS transistor 31 in the second P well 23. This first NM
The OS transistor 31 is the same as a transistor used in various circuits such as a memory cell, an N-type sense amplifier, an input / output gate, a row decoder / word line driver or an equalizer circuit, and the back gate voltage (or the second gate voltage)
A negative voltage V _BB is used as the well bias of the P well. The first PMOS transistor 32 is a transistor used in a P-type sense amplifier, and the back gate voltage (or well bias of the second N well) is the array power supply voltage V _{CC (A)} (V _CCLA or V _{CCRA ).} Represent). Second formed in the second N well 91
The PMOS transistor 92 is a transistor used in the word line drive clock generation circuit (FIG. 20), and the back gate voltage (or well bias of the second N well) is the boost voltage V _PP .

On the other hand, the PMOS transistor 34 is provided in the third N well 25 of the peripheral circuit region 400. This transistor is any PMOS transistor in the peripheral circuit area, and this back gate voltage uses the power supply voltage V _{CC (P)} (representing V _CCLP or V _{CCRP )} for the peripheral circuit. In the first P well 24, there is an arbitrary NMOS transistor 33, which is one of the transistors integrated in the peripheral circuit region, and the back gate voltage (or the first P
Well bias of well) is the ground voltage V for the peripheral circuit
_{Use SS (P),} which stands for V _SSLP or V _SSRP . 4th N
In the well 81, there is a third P well 83 having an NMOS transistor 86 formed therein. The back gate voltage of the transistor 86 is a negative voltage V _BB , and the ground voltage applied to the source of the transistor uses the ground voltage V _{SS (Q)} (representing V _SSLQ or V _{SSRQ )} for the word line and the TTL input buffer. To do. Within the fifth N-well 82 is a fourth P-well 84 having NMOS transistors 87 and 88 formed therein. Transistors 87 and 88 are the output transistors of FIG. The source of the transistor 88 is supplied with the driving ground voltage V _{SS (D)} , and the drain of the transistor 87 is supplied with the driving power supply voltage V _{CC (D)} . Then, the back gate voltage of these transistors (or
The well bias of the fourth P well) is the negative voltage V _BB .
The power supply voltage V for the peripheral circuit is applied to the fifth N-well 82.
A well bias of _{CC (P)} (representing V _CCLP or V _CCRP ) is applied.

It is easy for a person having ordinary skill in the art to change the setting of the well bias (or the back gate voltage of each transistor) applied to each well according to the present invention as shown in FIG. Can understand.
Needless to say, the embodiment shown in FIG. 1 can be applied to the N-type substrate.

FIGS. 8 and 9 show an embodiment of a MOS capacitor using the above-described triple well structure of the present invention. FIG. 8 shows a case where capacitors are designed in parallel. As shown in FIG. 8, the P ⁺ diffusion regions 107 and 108 formed in the gate 111 and the N well 102 of the NMOS transistor are formed.
, And the N ⁺ diffusion region 109 are connected together, and the power supply voltage V _CC is applied using this as the first common electrode of the parallel capacitor. Further, the N ⁺ diffusion regions 104 and 105 formed in the P well 103, the P ⁺ diffusion region 106 for applying the back gate voltage, and the P ⁺ diffusion region 1 formed in the substrate 101.
10 and the gate 112 of the PMOS transistor are connected together, and this is used as the second common electrode of the parallel capacitor.
The ground voltage V _SS is applied. In this way, an NMOS capacitor and a PMOS capacitor are connected in parallel to form a capacitor structure.

On the other hand, FIG. 9 shows a configuration in which a PMOS capacitor and an NMOS capacitor are connected in series and a clock needs to be applied to each gate. As shown in the figure, a clock is commonly supplied to the gates of the NMOS and PMOS transistors, all diffusion regions formed in the P well are grounded in common, and a power supply voltage is supplied to all diffusion regions formed in the N well. Is being supplied. Of course, other embodiments are possible other than the above configuration.

10 to 14 show a process for manufacturing a triple well according to the present invention. Note that only a part of the substrate is illustrated for simplification of the drawing. First, an oxide film 2 and a nitride film 3 are sequentially formed on a P-type silicon single crystal substrate 1 (see FIG. 1).
0). Next, after the first photoresist pattern 4 is formed, the nitride film 3 and the oxide film 2 are selectively etched to form an opening 5 for forming an N well and a Group 5 impurity such as arsenic or phosphorus. Are ion-implanted (FIG. 11). Next, the exposed surface of the substrate is wet-oxidized, and at the same time, the implanted ion impurities are diffused to form the N well 7. A thick oxide film 6 is formed on the surface of the substrate exposed by this wet oxidation (FIG. 12). Next, the thick oxide film 6 and the remaining oxide film 2 and nitride film 3 are removed, a thin pad oxide film 8 is formed on the substrate surface, and then a second photoresist pattern 9 is formed to form a Group III impurity such as boron. Are ion-implanted (FIG. 13). P wells 10 and 11 are formed outside and inside the N well 7, respectively, and then necessary transistors are formed in the wells, and accordingly contact diffusion regions for back gate voltage (or well bias) are formed. (Fig. 1
4).

FIGS. 15, 16 and 17 are output characteristic diagrams of the negative voltage V _BB generation circuit, the boosted voltage V _PP generation circuit and the internal voltage V _INT generation circuit used in the present invention. Figure 1
The output characteristics of FIGS. 5 and 16 are those of a negative voltage generating circuit and an internal voltage generating circuit generally used in a DRAM or the like. The output characteristic of FIG. 17 is “IEEE JSSC, Aug.1991, pp.117.
1 ”is disclosed in detail.

In the embodiments of the present invention, the case where the substrate is the P type has been described, but the present invention can be applied even if the substrate is the N type by exchanging the conductivity types. Further, the present invention is not limited to DRAM and can be applied to all highly integrated devices manufactured by a CMOS process.

[0031]

As described above, the present invention prevents malfunctions due to interference of power supply noise in an element by adopting a triple well structure in which power supplies are separately supplied in a semiconductor memory device. The effect is to improve the operational stability and reliability of the device.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a semiconductor device showing an embodiment of a well bias application state according to the present invention.

FIG. 3 is a partial cross-sectional view of a semiconductor device showing another embodiment of a well bias application state according to the present invention.

FIG. 4 is a partial cross-sectional view of a semiconductor device showing still another embodiment of a well bias application state according to the present invention.

FIG. 5 is a partial cross-sectional view of a semiconductor device showing an example of a well forming state and a well bias applying state in a memory cell array region according to the present invention.

FIG. 6 is a partial cross-sectional view of a semiconductor device showing an example of a well forming state and a well bias applying state in a peripheral circuit region according to the present invention.

FIG. 7 is a layout diagram of a power supply pad according to the present invention.

FIG. 8 is a partial sectional view showing an embodiment of a MOS capacitor according to the present invention.

FIG. 9 is a partial cross-sectional view showing another embodiment of the MOS capacitor according to the present invention.

FIG. 10 is a manufacturing process diagram for forming a triple well used in the present invention.

FIG. 11 is a manufacturing step diagram subsequent to the manufacturing step shown in FIG. 10;

FIG. 12 is a manufacturing step diagram subsequent to the manufacturing step shown in FIG. 11.

FIG. 13 is a manufacturing step diagram subsequent to the manufacturing step shown in FIG. 12;

FIG. 14 is a manufacturing step diagram subsequent to the manufacturing step shown in FIG. 13;

FIG. 15 is a diagram showing a voltage waveform of a negative voltage generating circuit used in the present invention.

FIG. 16 is a diagram showing voltage waveforms of a boosted voltage generating circuit used in the present invention.

FIG. 17 is a diagram showing voltage waveforms of the internal voltage generating circuit according to the present invention.

FIG. 18 shows, as an example to which the present invention is applicable, 64 Mbi.
t A layout diagram showing a schematic configuration of a DRAM memory device.

FIG. 19 is a bit line system circuit diagram in the memory cell array region of FIG. 18;

20 is a row decoder / word line drive clock generation circuit diagram in the row decoder / word line driver area of FIG. 18;

21 is a circuit diagram of the TTL input buffer in the peripheral circuit area of FIG.

22 is a circuit diagram of a data output buffer / driver in the peripheral circuit area of FIG.

FIG. 23 is a partial cross-sectional view of a semiconductor device showing a well bias application state according to a conventional technique.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) The inventor, formerly Yongjia, No.4, No.4, 1348, 1348, 1348, Jinwol apartment, 1348, 4 Pyeong-ri, Dong-gu, West-gu, Daegu, Republic of Korea

Claims (22)

[Claims] 1. A semiconductor device formed on a first conductivity type substrate, wherein a first well of a second conductivity type formed on the first conductivity type substrate and supplied with a first bias, and the second conductivity type. Of the first conductivity type formed in the first well of the second conductivity type and the second conductivity type of the second conductivity type formed in the well of the first conductivity type and in contact with the second bias. A semiconductor device having two wells. 2. The semiconductor device according to claim 1, wherein a third bias is supplied to the first conductivity type substrate. 3. A second conductivity type M in a well of the first conductivity type.
The semiconductor device according to claim 2, wherein an active region of the OS transistor is formed. 4. The semiconductor device according to claim 3, wherein at least one well of the wells of the second conductivity type is provided with a MOS transistor of the first conductivity type. 5. A first conductivity type well isolated from a well of a second conductivity type.
3. The semiconductor device according to claim 2, further comprising a third well of the second conductivity type having a conductivity type MOS transistor, to which the fourth bias is supplied. 6. The first bias is a voltage higher than a power supply voltage, the second bias is a negative voltage, the third bias is a ground voltage, and the fourth bias is a power supply voltage. The semiconductor device described. 7. The first bias is an internal voltage lower than the power supply voltage, the second bias is a negative voltage, the third bias is a ground voltage, and the fourth bias is a power supply voltage. 5. The semiconductor device according to item 5. 8. A semiconductor device integrated on a first conductivity type substrate and having a memory cell array region and a peripheral circuit region, wherein the semiconductor device is formed on the first conductivity type substrate in the memory cell array region and has a first conductivity type MOS transistor. , A first well of the second conductivity type to which the first bias is supplied, and a MOS transistor of the second conductivity type formed in the first well of the second conductivity type and to which the second bias is supplied. A second well of the first conductivity type having a first conductivity type first well and a second conductivity type MOS transistor formed in the first conductivity type substrate of the peripheral circuit region and supplied with a third bias. And a MOS of the first conductivity type formed on the first conductivity type substrate in the peripheral circuit region, separated from the second well of the first conductivity type.
A second having a transistor and supplied with a first bias
A semiconductor device having a second well of conductivity type. 9. The semiconductor device according to claim 8, wherein the first-conductivity-type substrate includes a first-conductivity-type high-concentration diffusion region connected to the third bias. 10. The semiconductor device according to claim 9, wherein the first bias is a power supply voltage, the second bias is a negative voltage, and the third bias is a ground voltage. 11. The semiconductor device according to claim 10, further comprising a negative voltage generation circuit that outputs a negative voltage serving as a second bias. 12. A semiconductor device integrated with a first conductivity type substrate and having a memory cell array region and a peripheral circuit region, wherein the semiconductor device is formed on the first conductivity type substrate of the memory cell array region and has a first conductivity type MOS transistor. , A first well of the second conductivity type to which the first bias is supplied, and a MOS transistor of the second conductivity type formed in the first well of the second conductivity type and to which the second bias is supplied. A first well of the first conductivity type and a second conductivity type MOS transistor formed in the first conductivity type substrate of the peripheral circuit region, the second conductivity type second transistor supplied with the second bias. A well and a first conductivity type substrate in the peripheral circuit region are formed to be isolated from the second well of the first conductivity type.
A second having a transistor and supplied with a third bias
A semiconductor device having a second well of conductivity type. 13. The semiconductor device according to claim 12, wherein the first-conductivity-type high-concentration diffusion region isolated from each well and connected to the second bias is provided in the first-conductivity-type substrate. 14. The semiconductor device according to claim 13, wherein the first bias is a voltage higher than a power supply voltage, the second bias is a ground voltage, and the third bias is a power supply voltage. 15. The semiconductor device according to claim 12, wherein the first bias is a voltage higher than a power supply voltage, the second bias is a negative voltage, and the third bias is a power supply voltage. 16. The semiconductor device according to claim 15, wherein the first-conductivity-type high-concentration diffusion region connected to the ground voltage is provided in the first-conductivity-type substrate. 17. The semiconductor device according to claim 14, further comprising a voltage booster circuit that generates a voltage higher than a power supply voltage. 18. The method according to claim 12, wherein the first bias is an internal voltage lower than the power supply voltage, the second bias is a negative voltage, and the third bias is a power supply voltage.
The semiconductor device described. 19. The first bias is an internal voltage lower than the power supply voltage, the second bias is a negative voltage, and the third bias is an internal voltage lower than the power supply voltage.
The semiconductor device described. 20. An internal voltage generation circuit for outputting an internal voltage lower than a power supply voltage is provided.
9. The semiconductor device according to any one of 9. 21. A memory cell array region integrated on one first conductivity type substrate, comprising a plurality of word lines, bit lines, memory cells, sense amplifiers, row decoders, and word line drivers, and a TTL. In a semiconductor device including a peripheral circuit region having an input buffer and a data output driver, a first power supply pad group for a memory cell array region, a second power supply pad group for a peripheral circuit region, a word line and The third power supply pad group for the TTL input buffer, the fourth power supply pad group for the data output driver, and the first well of the first conductivity type formed in the first conductivity type substrate of the memory cell array region are provided inside. A first well of the second conductivity type connected to the first power supply pad group and a first conductivity type substrate of the peripheral circuit region, at least a first well of the first conductivity type. A second well of the second conductivity type having two wells therein and connected to the second power supply pad group; and a second well of the first conductivity type formed in the first well and connected to the third power supply pad group. A second conductivity type MOS transistor, and a second conductivity type MOS transistor formed in the second well of the first conductivity type and connected to the fourth power supply pad group. Semiconductor device. 22. A first conductivity type substrate, a second conductivity type well formed in the first conductivity type substrate, and a first conductivity type well formed in the second conductivity type well. A second MOS transistor of the second conductivity type and a first high-concentration diffusion region of the first conductivity type formed in the well of the first conductivity type; and a first conductivity type of the first conductivity type formed in the well of the second conductivity type. Second MO
An S transistor and a second high-concentration diffusion region of the second conductivity type; and a third conductivity type of the first conductivity type formed on the substrate of the first conductivity type.
A high-concentration diffusion region of the first MOS transistor, comprising: a source and a drain of the first MOS transistor;
High-concentration diffusion region, the gate of the second MOS transistor, and the third high-concentration diffusion region are commonly connected, and the gate of the first MOS transistor, the source and drain of the second MOS transistor, and the second high-concentration diffusion region A semiconductor device, which is commonly connected to a concentration diffusion region.