JPH0685005A - Mounting structure of semiconductor chip - Google Patents
Mounting structure of semiconductor chipInfo
- Publication number
- JPH0685005A JPH0685005A JP4263018A JP26301892A JPH0685005A JP H0685005 A JPH0685005 A JP H0685005A JP 4263018 A JP4263018 A JP 4263018A JP 26301892 A JP26301892 A JP 26301892A JP H0685005 A JPH0685005 A JP H0685005A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring board
- printed wiring
- mounting structure
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、表面にバンプが形成さ
れた半導体チップをフェースダウンでプリント配線板上
に実装した、いわゆるフリップチップ方式における半導
体チップの実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called flip-chip type semiconductor chip mounting structure in which a semiconductor chip having bumps formed on its surface is mounted face down on a printed wiring board.
【０００２】[0002]
【従来の技術】図２はこの種の実装構造を説明する側断
面図である。図において、１は半導体チップであり、こ
の半導体チップ１の表面には図示せぬ電極パッドが形成
されている。また、半導体チップ１の電極パッド上には
バンプ２が突出して形成されている。一方、図中３はプ
リント配線板であり、このプリント配線板３の表面には
図示せぬ配線パターンが形成されている。このような構
成において、半導体チップ１はバンプ２を介してプリン
ト配線板３上に実装されている。2. Description of the Related Art FIG. 2 is a side sectional view for explaining a mounting structure of this type. In the figure, 1 is a semiconductor chip, and an electrode pad (not shown) is formed on the surface of the semiconductor chip 1. Further, bumps 2 are formed so as to project on the electrode pads of the semiconductor chip 1. On the other hand, reference numeral 3 in the drawing denotes a printed wiring board, and a wiring pattern (not shown) is formed on the surface of the printed wiring board 3. In such a configuration, the semiconductor chip 1 is mounted on the printed wiring board 3 via the bumps 2.
【０００３】[0003]
【発明が解決しようとする課題】ところで、一般に、半
導体チップ１がシリコン（Ｓｉ）を素材としているのに
対し、プリント配線板３は価格性、機能性、量産性など
の面からガラスエポキシ基板が多く使用される。しかし
ながら、その場合は半導体チップ１とプリント配線板３
の熱膨張係数が大きく異なるため、信頼性試験等で加熱
冷却を行うと両者間の変形格差によってバンプ２に大き
な熱応力がかかり、温度条件によってはバンプ２が破壊
されてしまうこともあった。By the way, in general, the semiconductor chip 1 is made of silicon (Si), but the printed wiring board 3 is made of a glass epoxy substrate in view of price, functionality, mass productivity and the like. Used a lot. However, in that case, the semiconductor chip 1 and the printed wiring board 3
Since the thermal expansion coefficients of the two are very different from each other, when heating and cooling are performed in a reliability test or the like, a large thermal stress is applied to the bumps 2 due to a deformation difference between the two, and the bumps 2 may be broken depending on temperature conditions.
【０００４】そこで従来では、バンプ２にかかる熱応力
を緩和するため、図３に示すように半導体チップ１とプ
リント配線板３との間隙Ｇに樹脂４を充填した構造を採
用しているが、これでも十分とは言えなかった。Therefore, conventionally, in order to reduce the thermal stress applied to the bump 2, a structure in which a resin 4 is filled in a gap G between the semiconductor chip 1 and the printed wiring board 3 as shown in FIG. That wasn't enough either.
【０００５】本発明は、上記問題を解決するためになさ
れたもので、従来よりもバンプにかかる熱応力を緩和す
ることができる半導体チップの実装構造を提供すること
を目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a mounting structure for a semiconductor chip that can reduce the thermal stress applied to the bumps as compared with the prior art.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、表面に電極パッドが形成
された半導体チップと、この半導体チップの電極パッド
上に形成されたバンプと、上面に配線パターンが形成さ
れたプリント配線板とから成り、このプリント配線板上
にバンプを介して半導体チップを実装したものであっ
て、半導体チップとプリント配線板とがなす間隙と、プ
リント配線板のチップ実装部に設けられた孔とに、少な
くともプリント配線板よりも熱膨張係数が小さい樹脂を
充填したものである。SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and includes a semiconductor chip having electrode pads formed on the surface thereof and bumps formed on the electrode pads of the semiconductor chip. A printed wiring board having a wiring pattern formed on its upper surface, wherein a semiconductor chip is mounted on the printed wiring board via bumps, and a gap formed between the semiconductor chip and the printed wiring board The hole provided in the chip mounting portion of the board is filled with at least a resin having a thermal expansion coefficient smaller than that of the printed wiring board.
【０００７】[0007]
【作用】本発明の半導体チップの実装構造においては、
半導体チップとプリント配線板とがなす間隙に充填され
た樹脂によりプリント配線板の上面側に基板の伸縮を抑
える力が働き、これと同時に、チップ実装部の孔に充填
された樹脂によりプリント配線板の内部側にも基板の伸
縮を抑える力が働くようになる。これにより、温度変化
に伴う半導体チップとプリント配線板の変形格差が小さ
くなり、バンプにかかる熱応力が緩和される。In the semiconductor chip mounting structure of the present invention,
The resin filled in the gap formed between the semiconductor chip and the printed wiring board acts on the upper surface side of the printed wiring board to suppress the expansion and contraction of the substrate, and at the same time, the resin filled in the holes in the chip mounting part The force that suppresses the expansion and contraction of the substrate also acts on the inside of the. As a result, the deformation difference between the semiconductor chip and the printed wiring board due to the temperature change is reduced, and the thermal stress applied to the bumps is relaxed.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。図１は本発明の一実施例を示す側断面図で
ある。図示した半導体チップの実装構造において、１は
半導体チップであり、この半導体チップ１の表面には図
示せぬ電極パッドが形成されている。また、半導体チッ
プ１の電極パッド上にはバンプ２が形成されている。一
方、図中３はプリント配線板であり、このプリント配線
板３の表面には図示せぬ配線パターンが形成されてい
る。そして半導体チップ１はバンプ２を介してプリント
配線板３上に実装されている。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a side sectional view showing an embodiment of the present invention. In the semiconductor chip mounting structure shown in the figure, 1 is a semiconductor chip, and an electrode pad (not shown) is formed on the surface of the semiconductor chip 1. Moreover, bumps 2 are formed on the electrode pads of the semiconductor chip 1. On the other hand, reference numeral 3 in the drawing denotes a printed wiring board, and a wiring pattern (not shown) is formed on the surface of the printed wiring board 3. The semiconductor chip 1 is mounted on the printed wiring board 3 via the bumps 2.
【０００９】本実施例では、まずプリント配線板３のチ
ップ実装部５に複数の孔６が設けられている。これらの
孔６は半導体チップ１とほぼ対向する位置にプリント配
線板３を貫通するかたちで明けられている。ここで、プ
リント配線板３のチップ実装部５に孔６を設ける方法と
しては、例えば、金型を用いた打ち抜きによるものや、
或いはドリルを用いた孔明け加工によるものなど、種々
の方法が考えられる。因みに、プリント配線板３の基材
を打ち抜く際に、孔６も一緒に打ち抜くようにすれば、
余計な工数がかからず非常に好適である。In this embodiment, first, a plurality of holes 6 are provided in the chip mounting portion 5 of the printed wiring board 3. These holes 6 are opened at positions substantially facing the semiconductor chip 1 so as to penetrate the printed wiring board 3. Here, as a method of providing the holes 6 in the chip mounting portion 5 of the printed wiring board 3, for example, punching using a mold,
Alternatively, various methods such as drilling using a drill can be considered. By the way, when the base material of the printed wiring board 3 is punched out, the holes 6 are also punched out together.
It is very suitable because it does not require extra man-hours.
【００１０】かかる実装構造において、半導体チップ１
とプリント配線板３との間には、両者を電気的に接続す
るバンプ２の高さに応じた間隙Ｇが形成される。本実施
例では、この半導体チップ１とプリント配線板３とがな
す間隙Ｇと、上述したプリント配線板３の孔６とに、そ
れぞれ樹脂４が充填されている。ここで用いられる樹脂
４としては、少なくともプリント配線板３よりも熱膨張
係数が小さいものが選定される。In such a mounting structure, the semiconductor chip 1
A gap G is formed between the printed wiring board 3 and the printed wiring board 3 according to the height of the bump 2 that electrically connects the two. In this embodiment, resin 4 is filled in the gap G formed between the semiconductor chip 1 and the printed wiring board 3 and the hole 6 of the printed wiring board 3 described above. As the resin 4 used here, at least one having a thermal expansion coefficient smaller than that of the printed wiring board 3 is selected.
【００１１】その一例として、半導体チップ１がシリコ
ン基板で構成され、プリント配線板３がガラスエポキシ
基板で構成されている場合、半導体チップ１の熱膨張係
数は３．５ｐｐｍとなるのに対して、プリント配線板３
の熱膨張係数は１５ｐｐｍとなるので、この場合の樹脂
４材料としては、例えば熱膨張係数が８ｐｐｍ程度の変
性エポキシや、或いは変性ポリイミドなどを選定すると
よい。As an example, when the semiconductor chip 1 is made of a silicon substrate and the printed wiring board 3 is made of a glass epoxy substrate, the coefficient of thermal expansion of the semiconductor chip 1 is 3.5 ppm, whereas Printed wiring board 3
Since the coefficient of thermal expansion is 15 ppm, the resin 4 material in this case may be, for example, modified epoxy having a coefficient of thermal expansion of about 8 ppm or modified polyimide.
【００１２】このような構成からなる本実施例の実装構
造においては、半導体チップ１とプリント配線板３との
間隙Ｇに加え、プリント配線板３のチップ実装部５に設
けた孔６にも樹脂４が充填されているため、温度変化に
伴う半導体チップ１とプリント配線板３との変形格差が
従来よりも小さくなる。In the mounting structure of this embodiment having such a structure, in addition to the gap G between the semiconductor chip 1 and the printed wiring board 3, resin is also provided in the hole 6 provided in the chip mounting portion 5 of the printed wiring board 3. 4 is filled, the difference in deformation between the semiconductor chip 1 and the printed wiring board 3 due to the temperature change becomes smaller than in the conventional case.
【００１３】すなわち、温度変化に伴ってプリント配線
板３は半導体チップ１よりも大きく伸縮しようとする
が、まず、半導体チップ１とプリント配線板３とがなす
間隙Ｇに充填された樹脂４によりプリント配線板３の上
面側に基板の伸縮を抑える力が働き、これと同時に、チ
ップ実装部５の孔６に充填された樹脂４によりプリント
配線板３の内部側にも基板の伸縮を抑える力が働くよう
になる。これにより、温度変化に伴う半導体チップ１と
プリント配線板３の変形格差が小さくなり、従来に比較
してバンプ２にかかる熱応力が大幅に緩和される。That is, the printed wiring board 3 tends to expand and contract larger than the semiconductor chip 1 due to the temperature change. First, the resin 4 filled in the gap G formed between the semiconductor chip 1 and the printed wiring board 3 is used for printing. A force that suppresses the expansion and contraction of the board acts on the upper surface side of the wiring board 3, and at the same time, a force that suppresses the expansion and contraction of the board also exists inside the printed wiring board 3 due to the resin 4 filled in the holes 6 of the chip mounting portion 5. Get to work. As a result, the difference in deformation between the semiconductor chip 1 and the printed wiring board 3 due to the temperature change is reduced, and the thermal stress applied to the bump 2 is relieved as compared with the conventional case.
【００１４】なお、本実施例の説明では、プリント配線
板３のチップ実装部５に複数の孔６を設けるようにした
が、本発明の半導体チップの実装構造は、孔６の数やそ
の形状、さらにはチップ実装部５における孔６の配置状
態に限定されるものではない。Although a plurality of holes 6 are provided in the chip mounting portion 5 of the printed wiring board 3 in the description of this embodiment, the semiconductor chip mounting structure of the present invention has the number of holes 6 and its shape. Further, it is not limited to the arrangement state of the holes 6 in the chip mounting portion 5.
【００１５】[0015]
【発明の効果】以上、説明したように本発明の半導体チ
ップの実装構造によれば、半導体チップとプリント配線
板との間隙に加え、プリント配線板のチップ実装部に設
けた孔にも樹脂が充填されることから、温度変化に伴う
半導体チップとプリント配線板の変形格差が小さくな
り、従来に比較してバンプにかかる熱応力が大幅に緩和
される。これにより温度変化に伴うバンプの破壊が起こ
りにくくなり、最終的な製品の信頼性向上が期待でき
る。As described above, according to the mounting structure of the semiconductor chip of the present invention, in addition to the gap between the semiconductor chip and the printed wiring board, the resin is also provided in the hole provided in the chip mounting portion of the printed wiring board. Since the filling is performed, the difference in deformation between the semiconductor chip and the printed wiring board due to the temperature change is reduced, and the thermal stress applied to the bump is significantly reduced as compared with the conventional case. As a result, the bumps are less likely to break due to temperature changes, and the final product reliability can be expected to improve.
【図１】本発明の一実施例を示す側断面図である。FIG. 1 is a side sectional view showing an embodiment of the present invention.
【図２】実装構造の一例を説明する側断面図である。FIG. 2 is a side sectional view illustrating an example of a mounting structure.
【図３】従来例を示す側断面図である。FIG. 3 is a side sectional view showing a conventional example.
１ 半導体チップ ２ バンプ ３ プリント配線板 ４ 樹脂 ５ チップ実装部 ６ 孔 1 semiconductor chip 2 bumps 3 printed wiring board 4 resin 5 chip mounting part 6 holes
Claims (1)
ップと、前記半導体チップの電極パッド上に形成された
バンプと、表面に配線パターンが形成されたプリント配
線板とから成り、 前記プリント配線板上に前記バンプを介して前記半導体
チップを実装したものであって、 前記半導体チップと前記プリント配線板とがなす間隙
と、前記プリント配線板のチップ実装部に設けられた孔
とに、少なくとも前記プリント配線板よりも熱膨張係数
が小さい樹脂を充填したことを特徴とする半導体チップ
の実装構造。1. A printed wiring board comprising: a semiconductor chip having electrode pads formed on its surface; bumps formed on the electrode pads of the semiconductor chip; and a printed wiring board having a wiring pattern formed on its surface. The semiconductor chip is mounted on the above via the bump, and at least the gap formed by the semiconductor chip and the printed wiring board and the hole provided in the chip mounting portion of the printed wiring board, A semiconductor chip mounting structure characterized by being filled with a resin having a thermal expansion coefficient smaller than that of a printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4263018A JPH0685005A (en) | 1992-09-04 | 1992-09-04 | Mounting structure of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4263018A JPH0685005A (en) | 1992-09-04 | 1992-09-04 | Mounting structure of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0685005A true JPH0685005A (en) | 1994-03-25 |
Family
ID=17383744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4263018A Pending JPH0685005A (en) | 1992-09-04 | 1992-09-04 | Mounting structure of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0685005A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0694965A1 (en) * | 1994-07-26 | 1996-01-31 | STMicroelectronics S.A. | BGA package for integrated circuits and method for manufacturing |
| US6238777B1 (en) | 1997-10-06 | 2001-05-29 | Denso Corporation | Printed-circuit board |
| US6404062B1 (en) | 1999-03-05 | 2002-06-11 | Fujitsu Limited | Semiconductor device and structure and method for mounting the same |
| JP2006324271A (en) * | 2005-05-17 | 2006-11-30 | Renesas Technology Corp | Semiconductor device |
-
1992
- 1992-09-04 JP JP4263018A patent/JPH0685005A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0694965A1 (en) * | 1994-07-26 | 1996-01-31 | STMicroelectronics S.A. | BGA package for integrated circuits and method for manufacturing |
| FR2723257A1 (en) * | 1994-07-26 | 1996-02-02 | Sgs Thomson Microelectronics Sa | BGA INTEGRATED CIRCUIT BOX |
| US6238777B1 (en) | 1997-10-06 | 2001-05-29 | Denso Corporation | Printed-circuit board |
| US6404062B1 (en) | 1999-03-05 | 2002-06-11 | Fujitsu Limited | Semiconductor device and structure and method for mounting the same |
| JP2006324271A (en) * | 2005-05-17 | 2006-11-30 | Renesas Technology Corp | Semiconductor device |
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