JPH0684824A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain that the drain current of a transistor is dropped by preventing that the contact resistance of a silicide with a semiconductor diffused layer is increased. CONSTITUTION:After the junction of a semiconductor diffused layer 3 has been formed and before a silicide layer is formed, an impurity concentration is increased by implanting ions 6 additionally in such a way that the peak of a concentration is situated near a part where the bottom of the silicide layer is positioned. Thereby, even when the silicide layer is formed and the silicide layer sucks out impurities in the semiconductor diffused layer, it is possible to prevent that a contact resistance is increased without making a Schottky barrier high because the impurity concentration has been increased in advance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical connection formed by a semiconductor impurity diffusion layer and a compound of the semiconductor and a refractory metal.

[0002]

2. Description of the Related Art A compound of a semiconductor (for example, Si) and a refractory metal (for example, Ti, Co, Ni, Ta, W) is called refractory metal silicide (hereinafter referred to as "silicide"), which is used in MOS type transistors. It is one of the materials effective for reducing the resistance of the source / drain regions and the gate electrode. Therefore, it is possible to suppress the resistance of the source / drain regions and the gate wiring, which tend to increase as the scaling of the MOS transistor becomes finer in response to higher integration.

This technique will be described with reference to FIGS. 12 to 16 by taking titanium silicide (TiSi ₂ ) as a silicide and making contact with silicon having a P ⁺ / N junction.

FIG. 12 shows a cross-sectional view of a PchMOS transistor having a junction formed. The transistor separated by the field oxide film 5 has a gate electrode 1, a sidewall oxide film 2, a P ⁺ diffusion layer 3, and a gate oxide film 4. The P ⁺ diffusion layer 3 contains BF ₂ ⁺ of 4 × 10 on the N-type substrate 20.
It is formed by implanting under the conditions of ¹⁵ / cm 2 and 20 keV and performing heat treatment at 900 ° C. in a nitrogen atmosphere.

FIG. 13 shows a titanium film 8 deposited on the entire surface by a sputtering method. Then, heat treatment is performed in a nitrogen atmosphere at 700 ° C. for 30 seconds using a lamp annealing device. As a result, a titanium nitride (TiN) layer 9 is formed on the surface of the titanium film 8, and a titanium nitride (TiSi _x ) layer 11 is formed on the titanium film 8 in contact with the substrate 20 and the gate electrode 1 by reaction with silicon. It is formed.
At this time, the titanium film 8 in contact with the oxide films 4 and 5 does not react with the oxide film (SiO ₂ ), and the unreacted titanium film 10 does not react.
Exist as (FIG. 14).

Next, as shown in FIG. 15, the titanium nitride layer 9 and the unreacted titanium film 10 are removed to remove the silicon nitride layer 1.
Leave 1. For this, sulfuric acid and hydrogen peroxide solution are used.

Then, the lamp annealing apparatus is used again to perform heat treatment at 800 ° C. for 30 seconds in a nitrogen atmosphere. By this process, the silicon nitride layer 11 becomes a low resistance silicide (TiSi ₂ ) layer 12 (FIG. 16).

[0008]

By the way, the silicide has a property of absorbing impurities in the silicon which is in contact with the silicide. Therefore, the impurity concentration of the P ⁺ diffusion layer 3 decreases at the junction surface with the silicide layer 12.

17 to 18 are impurity concentration distribution charts for explaining this. 17 shows the P ⁺ diffusion layer 3 formed, and FIG. 18 shows the silicide layer 12 formed thereafter.
The respective boron concentration distributions are shown. However, the titanium film 8 is 5
This is for the case where the film is formed at 00 angstrom. The horizontal axis represents the distance from the surface of the substrate 20, and the vertical axis represents the boron concentration.

From the graph 31 of FIG. 17, it can be seen that the peak of the boron concentration when the P ⁺ diffusion layer 3 is formed is located at a position of about 700 angstroms from the surface. On the other hand, FIG.
As shown in FIG. 8, the bottom surface of the silicide layer 12 has a graph 31
It reaches to the position of the peak of the boron concentration indicated by.

However, as described above, the silicide layer 1
2 in order to suck the boron which is an impurity of the P ⁺ diffusion layer 3, the boron concentration of the P ⁺ diffusion layer 3 in contact with the bottom surface of the silicide layer 12 as shown in the graph 32 decreases.

Such a decrease in the boron concentration increases the height of the Schottky barrier formed by the P ⁺ diffusion layer 3 and the silicide layer 12, resulting in an increase in contact resistance. This phenomenon has a problem that the drain current is lowered in the characteristics of the transistor.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor manufacturing method for reducing the resistance at the junction between a semiconductor compound of a refractory metal and the semiconductor.

[0014]

A first aspect of a method of manufacturing a semiconductor device according to the present invention comprises: (a) preparing a semiconductor layer having a predetermined impurity concentration; and (b) forming a semiconductor layer on the semiconductor layer. The method includes a step of forming a compound of a semiconductor layer and a refractory metal, and a step of increasing the impurity concentration in the vicinity of the bottom surface of the compound in the semiconductor layer (c) prior to the step (b).

A second aspect of the method for manufacturing a semiconductor device according to the present invention is (a) a step of preparing a semiconductor layer having a predetermined impurity concentration, and (b) a semiconductor layer and a refractory metal on the semiconductor layer. And a step of increasing the impurity concentration in the semiconductor layer in the vicinity of the bottom surface of the compound in the semiconductor layer.

[0016]

In the present invention, the impurity concentration of the semiconductor layer in the vicinity of the compound of the semiconductor layer and the refractory metal is increased so as to compensate for the decrease of the impurity concentration due to the compound sucking out the impurity of the semiconductor layer.

[0017]

【Example】

First embodiment. 1 to 6 show a method of manufacturing a PchMOS transistor according to a first embodiment of the present invention in the order of steps. After forming the gate oxide film 4 and the gate electrode 5 on the field, BF ₂ ⁺ is set to 20 keV and 4 by ion implantation.
Inject under the condition of × 10 ¹⁵ / cm 2. Then, heat treatment is performed at 900 ° C. for 20 minutes in a nitrogen atmosphere to form the P ⁺ diffusion layer 3 (FIG. 1).

Next, as shown in FIG. 2, the implantation energy is selected so that the projection range RP of BF ₂ ⁺ becomes approximately the same as the film thickness of the silicide layer 12 formed later, 10 ¹⁵ / c
Additional ion implantation 6 is performed with m2 units. BF was driven in
₂ ⁺ increases the boron concentration in the P ⁺ diffusion layer 3 near the peak position 7. The subsequent heat treatment may or may not be performed.

Next, as shown in FIG. 3, a titanium layer 8 is deposited on the entire surface by a sputtering method to have a thickness of about 500 Å.

Next, heat treatment is performed in a nitrogen atmosphere at 700 ° C. for 30 seconds using a lamp annealing device. As a result, as shown in FIG. 4, the titanium nitride layer 9 is formed on the surface of the titanium film 8, the titanium film 8 in contact with the substrate 20 and the gate electrode 1 is formed of the silicon nitride layer 11 due to the reaction with silicon, Formed respectively. At this time, oxide films 4, 5
The titanium film 8 in contact therewith does not react with the oxide film and exists as an unreacted titanium film 10.

Next, as shown in FIG. 5, the titanium nitride layer 9,
The unreacted titanium film 10 is removed and the silicon nitride layer 11 is left. For this, sulfuric acid and hydrogen peroxide solution are used.

Next, the lamp annealing apparatus is used again to perform heat treatment at 800 ° C. for 30 seconds in a nitrogen atmosphere. By this process, the silicon nitride layer 11 becomes the low resistance silicide layer 12 (FIG. 6).

As can be seen from the above steps, the present invention adds an additional ion implantation 6 to the conventional steps. Therefore, P that contacts the bottom surface of the silicide layer 12
^{+ The} diffusion layer 3 has a high concentration.

Therefore, even if the silicide layer 12 sucks out boron from the P ⁺ diffusion layer 3, the sucked-out portion is already replenished by the additional ion implantation 6.
It is possible to prevent an increase in contact resistance between the bottom surface of the silicide layer 12 and the P ⁺ diffusion layer 3.

This will be further described with reference to a boron concentration distribution chart. FIG. 7 corresponds to the process shown in FIG.
The concentration distribution with respect to the distance from the surface of the substrate 20 when BF ₂ ⁺ was implanted under the conditions of 20 keV and 4 × 10 ¹⁵ / cm 2 and heat-treated at 900 ° C. for 20 minutes in a nitrogen atmosphere is shown. The horizontal axis represents the distance from the surface of the substrate 20, and the vertical axis represents the boron concentration. As can be seen from graph 31, the peak boron concentration is located approximately 700 angstroms from the surface.

FIG. 8 corresponds to the process shown in FIG. 2 and has a BF of 10 ¹⁵ / cm 2 at an energy of several tens keV.
The distribution of the boron concentration when the additional ion implantation 6 of ₂ ⁺ or B ⁺ is performed is shown. The implantation energy of the additional ion implantation 6 is controlled so as to have a projection range RP that is approximately the same as the film thickness of the silicide layer 12 that is formed later.

Graph 33 shows the distribution of the boron concentration added by the additional ion implantation 6. Therefore, after all, P ⁺
The distribution of boron concentration in the diffusion layer 3 is shown in graphs 31 and 33.
It is the sum of the boron concentrations represented by and, and is represented by the graph 34.

FIG. 9 shows the distribution of the boron concentration when the silicide layer 12 having a thickness of 700 angstrom is formed on the P ⁺ diffusion layer 3 having the boron concentration shown in the graph 34.

As shown by the graph 35, the boron of the P ⁺ diffusion layer 3 is sucked by the silicide layer 12, and the concentration thereof becomes lower than the concentration shown by the graph 34.

However, since the boron concentration of the P ⁺ diffusion layer 3 in the vicinity of the silicide layer 12 is sufficiently increased in advance, the height of the Schottky barrier is not increased and the increase in contact resistance is suppressed. Therefore, a decrease in drain current of the PchMOS transistor can be suppressed.

Second embodiment. In the first embodiment, after forming the P ⁺ diffusion layer 3 and before forming the silicide layer 12, P <sup>+
+ Although</sup> the boron concentration of the diffusion layer 3 is increased, the silicide layer 12
The boron concentration of the P ⁺ diffusion layer 3 may be increased over the silicide layer 12 after the formation of.

In FIG. 10, P with the silicide layer 12 formed
A sectional view of a chMOS transistor is shown. After the silicide layer 12 is formed in this way, as shown in FIG.
Additional ion implantation 6 of B ^{+ and} BF ₂ ⁺ is performed through the silicide layer 12. The energy is controlled so that the projection range RP comes to the bottom surface of the silicide layer 12 as in the first embodiment. Further, it is desirable that the injection amount is about the same as that shown in the first embodiment.

The activation of the added impurities is performed by the P
This is performed by depositing an interlayer film on the chMOS transistor and reflowing it. By increasing the impurity concentration in this way, the P ⁺ diffusion layer 3 by the silicide layer 12 is formed.
Even if the boron is sucked out, the amount of boron is compensated by the additional ion implantation 6, so that the same effect as in the first embodiment can be obtained.

Third Embodiment. In the first and second embodiments, the case where TiSi ₂ is used as the silicide has been described, but the present invention can be applied even when other silicide such as CoSi ₂ , NiSi, TaSi ₂ , WSi ₂ is used.
The same effect can be obtained.

[0035]

As described above, according to the present invention, the impurity of the semiconductor layer absorbed by the compound of the semiconductor layer and the refractory metal is compensated, so that the height of the Schottky barrier formed by the compound and the semiconductor layer is high. Does not increase, and the increase in contact resistance is suppressed. Therefore, a decrease in the drain current of the transistor can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in process order.

FIG. 3 is a cross-sectional view showing the first embodiment of the present invention in process order.

FIG. 4 is a sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing the first embodiment of the present invention in process order.

FIG. 7 is a distribution diagram of impurity concentration according to the first embodiment of the present invention.

FIG. 8 is a distribution diagram of impurity concentration according to the first embodiment of the present invention.

FIG. 9 is a distribution diagram of impurity concentration according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view showing a second embodiment of the present invention in process order.

FIG. 12 is a cross-sectional view showing a conventional technique in order of steps.

FIG. 13 is a cross-sectional view showing a conventional technique in order of steps.

FIG. 14 is a cross-sectional view showing a conventional technique in order of steps.

FIG. 15 is a cross-sectional view showing a conventional technique in order of steps.

FIG. 16 is a cross-sectional view showing a conventional technique in order of steps.

FIG. 17 is a distribution diagram of impurity concentration according to a conventional technique.

FIG. 18 is a distribution diagram of impurity concentration according to a conventional technique.

[Explanation of symbols]

3 P ⁺ Diffusion layer 6 Additional ion implantation 12 Silicide (TiSi ₂ ) layer

Claims (2)

[Claims] 1. A method comprising: (a) preparing a semiconductor layer having a predetermined impurity concentration; and (b) forming a compound of the semiconductor layer and a refractory metal on the semiconductor layer, Prior to the step (b), the method for manufacturing a semiconductor device further comprising: (c) increasing the impurity concentration in the semiconductor layer in the vicinity of the bottom surface of the compound formed. 2. (a) preparing a semiconductor layer having a predetermined impurity concentration; (b) forming a compound of the semiconductor layer and a refractory metal on the semiconductor layer; (c) And a step of increasing an impurity concentration in the semiconductor layer near the bottom surface of the compound.