JPH0683614A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide a microcomputer which can reduce the program capacity and also shorten the program executing time. CONSTITUTION:A control register group 8 is provided with a 2-operand/3- operand control switching register 11. An instruction decoding part 9 decodes an instruction code as well as the logical value of the register 11 that is set at every task execution queues. Thus the information on the operands can be decided. Thus, the switching is facilitated between the 2-operand and 3-operand control states at every task even with the same instruction code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer capable of switching between 2-operand control and 3-operand control with the same instruction code by the output of a 2-operand control 3-operand control switching register inside a control register group. It is about.

[0002]

2. Description of the Related Art In a conventional two-operand control microcomputer program, an instruction code (n
In many cases, the source address was stored in the (+1) address and the destination address was stored in the (n + 2) address.

For example, in the case of an addition instruction, after the data at the address indicated by the source address and the data at the address indicated by the destination address are added, the added data is stored again at the address indicated by the destination address. It Therefore, when it is not desired to rewrite the data of the address indicated by the destination address, it is necessary to copy the data of the address indicated by the destination address to another place in advance and then add the data. An example of an assembler program in this case is as follows: (Program) MOV B C ADD A C (A, B, and C indicate addresses), the data indicated by address B is copied to address C, and It was necessary to execute two instructions such as adding the data indicated by A and the data indicated by address C.

On the other hand, in a three-operand control microcomputer program, the assembler program as described above becomes ADD ABC and only one instruction needs to be executed.

However, the destination address B
If you want to rewrite the result of adding the data shown in,
That is, when the data indicated by the address A and the data indicated by the address B are added and the addition result is to be stored again at the address B, ADD A B is obtained in the two-operand control, and the instruction code and the two addresses are stored. The designated part is enough,
Three-operand control results in ADD ABBB, which requires an instruction code and three addressing sections.

In the conventional microcomputer, either one of the two-operand control and the three-operand control is performed, so that the program capacity and the execution time are increased.

[0007]

As described above, since the conventional microcomputer controls only one of the two-operand control and the three-operand control, the capacity of the program is increased due to the increase of the address designation section. There is a problem that the execution time becomes longer due to the increase in the number of execution instructions.

An object of the present invention is to provide a microcomputer capable of reducing the program capacity and the execution time.

[0009]

In order to solve the above problems, the microcomputer according to the present invention has the following configuration. That is, a plurality of task execution queues each including an instruction decoding unit that decodes an instruction code, an instruction execution unit that executes the instruction decoded by the instruction decoding unit, a control register group, and a data register, an address pointer, and the like. , Which is a microcomputer for performing time-division multitask processing by hardware switching, and in which a different logical value is set in the control register group for each task execution queue by two-operand control or three-operand control It is characterized by having a register.

[0010]

According to the structure of the present invention, two-operand control or three-operand control is performed.
A switching register in which a different logical value is set depending on operand control is provided in the control register group, and the output of this register is decoded by the instruction decoding unit.
Operand control can be switched appropriately.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a basic system configuration diagram. This microcomputer has task execution queues 0 to 7 provided with register files composed of data registers, address pointers, etc. in order to enable time-division multitask processing to be performed by hardware, and all of these tasks are performed. It is composed of a control register group 8 common to the execution queues, an instruction decoding unit 9 that decodes an instruction code read from a program storage area (not shown), and an instruction execution unit 10 that executes the decoded instruction. Also,
The control register group 8 is provided with a 2-operand control 3-operand control switching register 11 having a bit width equal to the number of task execution queues, and is given a specific address.

A signal a is an access signal to the control register group, and data in the control register group can be read and written.

A signal b is an output signal of the control register group and includes an output signal of the 2-operand control 3-operand control switching register. The output of this switching register is input to the instruction decoding unit together with the instruction code.

The signal c is a signal output as a result of being decoded by the instruction decoding unit, and is a signal for controlling the instruction execution unit.

The signal d is an access signal to each task execution queue. FIG. 2 is a diagram showing a 2-operand control 3-operand control switching register. This register is b
There are 8 bit positions from p (bit position) 0 to bp 7, and each bit position indicates to which task execution queue the switching register is directed.
That is, the logical value set in bp0 indicates whether the task execution queue 0 performs 2-operand control or 3-operand control. Further, this switching register can be written only from a specific task execution queue and can be read from all task execution queues.

FIG. 3 shows an example of an assembler program using the present invention (the assembler program description method is as described in the prior art). Task 0 is a task execution queue in which switching registers can be written, and tasks 1 and 2 are read-only task execution queues. Now, it is assumed that three-operand control is performed when the logical value of the switching register is set to "1" and two-operand control is performed when the logical value is reset to "0".

The instruction indicated by e of task 0 is an instruction for writing 22 (hexadecimal number) into the 2-operand control 3-operand control switching register assigned to the address X.
That is, the task execution queues 1 and 5 are set to perform 3-operand control, and the remaining six task execution queues are set to perform 2-operand control.

The data in the switching register in which this 22 (hexadecimal number) is written is sent to the instruction decoding unit 9 through the signal b in FIG.
Sent to. When the task execution queue 1 is the task execution queue to be executed next, the logical value "1" of the corresponding bit position 1 of the operand control register is decoded together with the instruction code fetched from the program storage area.

As a result, the information about the operands such as the number of addressing sections arranged after the instruction code is sequentially decoded. By repeating this operation, three-operand control is performed on the instruction executed thereafter.

Next, when the task execution queue is switched to 2, the logical value "0" of the corresponding bit position 2 of the operand control switching register is decoded together with the instruction code fetched from the program storage area.

As a result, the information about the operands such as the number of addressing parts arranged after the instruction code is sequentially decoded. By repeating this operation, two-operand control is performed on the instructions executed thereafter.

When it is desired to switch the operand control of the task currently being executed or another task, it is possible to call a task execution queue in which a specific operand control register can be written and rewrite the contents of this switching register. Becomes

Further, when the flow of the program is interrupted due to interruption or exception handling during the execution of the program, the value of the switching register is saved as internal information of the CPU in a specific storage space together with other information. . next,
When returning from a processing routine such as interrupt or exception processing, the value saved as internal information of the CPU is also written in the switching register. This causes the state of the CPU to be equal to before the program flow was interrupted.

By performing the above operation, it is possible to easily
Operand control and three-operand control can be switched.

[0025]

According to the microcomputer of the present invention, a switching register in which different logical values are set depending on two-operand control or three-operand control is provided in the control register group, and the output of this switching register is used by the instruction decoding unit. By this, it becomes possible to appropriately switch the two-operand control and the three-operand control with the same instruction code.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention.

FIG. 2 is a two-operand control 3 in one embodiment of the present invention.
Operand control switching register diagram

FIG. 3 is a diagram showing an example of an assembler program in a microcomputer according to an embodiment of the present invention.

[Explanation of symbols]

0 to 7 task execution queue 8 control register group 9 instruction decoding unit 10 instruction execution unit 11 2 operand control / 3 operand control switching register a control register access signal b 2 operand control 3 operand control switching register output signal c instruction Execution unit control signal d Access signal for each task execution queue e Two-operand control Three-operand control switching register access instruction

Claims (1)

[Claims] 1. A plurality of instruction decoding units for decoding an instruction code, an instruction executing unit for executing an instruction decoded by the instruction decoding unit, a control register group, and a plurality of data registers, address pointers and the like. A microcomputer for performing time-division multitask processing by switching the task execution queue by hardware, wherein different logical values are set in the control register group for each task execution queue depending on whether two-operand control or three-operand control is performed. A microcomputer provided with an operand control switching register.