JPH0681136B2 - Data converter - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data converter for protecting data from errors and alteration in data communication.

(Prior art and its problems) In packet data communication, when an error is detected in a packet on the receiving side, there are many methods in which the packet is discarded and a retransmission request is issued. In this case, an error detection code is used. By the way, when encryption is used, it is conventionally known that data can be protected from alteration by a third party by performing error detection encoding before encoding.

However, even if combined with a cipher, error detection coding is not easy as compared with the case where there is no cipher.

(Object of the Invention) An object of the present invention is to provide a data converter in which the above-mentioned drawbacks are eliminated.

(Structure of the Invention) According to the present invention, first storage means for storing the latest N pieces of input data, second storage means for storing the latest M pieces of output of the conversion means, and the first and A data converter characterized by comprising a conversion means for converting the input data depending on the contents stored in the second storage means.

Further, according to the present invention, a digit series adding means for adding a redundant digit series to a part of the packet data and outputting the data, and a first storage for storing the latest N pieces of the outputs of the digit series adding means. Means, a second storage means for storing the latest M outputs of the conversion means, and a conversion means for converting the output digit of the digit system addition means existing in the storage contents of the first and second storage means. A data converter is obtained which is characterized in that

Further, according to the present invention, for packet data in which a redundant digit sequence is added to a part of the packet, each digit of the packet data depends on the N digit immediately before the digit and the M digit of the digit of the converter. A data converter to which the generated and converted data is supplied as input data, means for storing the latest M pieces of the input data, and means for storing the latest N pieces of the output of the conversion means, Conversion means for converting the input data depending on the stored contents of the first and second recording means, and means for detecting whether or not the redundant digit sequence exists in the output of the code conversion means. A data converter is obtained which is characterized in that

(Operation / Principle of the Present Invention) FIG. 2 is a view showing the operation / principle of the present invention. In the figure, the packet sent from the information source 201 on the transmission side is
A specific pattern is finally added by the pattern adding circuit 202, encrypted by the encryptor 203, and transmitted.

On the receiving side, the packet sent from the transmitting side is combined by the decoder 204, and the pattern detection circuit 205 judges whether or not the pattern is added to the end of the packet, and if it is added, an error or alteration is made. If there is no error and the pattern changes to a different pattern, it is determined that there is an error or tampering, and the reception purpose is 20.
Send packet to 6. Here, if a bit error occurs in the encryption device 203 and the composite device 204 on the transmission path, if the encryption device and the composite device are such that the error propagates to the end of the packet, an error during transmission or alteration by a third party Influences the specific pattern at the end of the packet, and the specific pattern changes. Therefore, an error or tampering can be detected. An example of an error propagating encryption device and compound device will be shown in the embodiment.

(Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention. In order to make the explanation easy to understand, it is assumed that all data are represented in binary. In the figure shift register
101 stores N bits of input, and shift register 102 stores M bits of output of this embodiment. Here, N and M are positive integers determined in advance. The code converter 103 performs code conversion of the data in the shift registers 101 and 102, and the exclusive OR element 104 performs exclusive OR with the input bit and outputs it as the output bit.

This embodiment is used for the transmission side, and the reception side is used for this embodiment in which M and N are exchanged. At this time, if the initial state of the shift register is the same on the transmitting side and the receiving side and there is no error or tampering during packet transmission, the contents of the shift register are the same on the transmitting and receiving sides. A match is made and the data is restored to its original state. Further, when an error or tampering occurs during transmission, the influence of the error is fed back to the shift register 102, so that error propagation occurs. Therefore, if the specific pattern is added to the end of the packet, the specific pattern changes on the receiving side, so that an error or falsification can be detected. The method of code conversion is kept secret in order to detect falsification. The code converter 103 is a commercially available cipher or RAM or
It can consist of ROM memory. In this embodiment,
Errors and tampering cannot be detected unless the input packet has redundancy. This is improved in the next embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention. This embodiment is installed on the transmitting side. First, a packet start pulse is given to selectors 309 and 310 at the start of packet input, and the selector selects the initial values of shift registers 301 and 302 from registers 306 and 307, respectively.
Send to 1 and 302. When the packet is input, the pattern adding circuit 305 adds the specific pattern at the end. The pattern addition circuit outputs the data bit by bit. The specific pattern may be any pattern that is predetermined. Selectors 309 and 310 select the output of the pattern circuit 305 and the output of the exclusive OR element 304, respectively. Code converter 303
Performs code conversion on the contents of the shift registers 301 and 302, and the code-converted bits are subjected to exclusive OR with the output of the pattern adding circuit 305 and transmitted from the transmitter 308. The pattern adding circuit 305 can be composed of a memory. That is, the specific pattern may be written in advance, and the entire packet may be read after writing the packet.

FIG. 4 is a block diagram for showing the third embodiment of the present invention, which is the receiving side for FIG. When the receiver 405 receives the packet, the packet start pulse is sent to the selector 40.
9 and 410, and the selectors are shift registers 401 and 4 respectively.
The contents of the registers 406 and 407 are selected as the initial value of 02 and sent to the shift register. After that, the selectors 409 and 410 select the received packet and the output of the late exclusive OR element 404, respectively. The code conversion circuit 403 is the shift registers 401, 40.
The content of 2 is code-converted, and the code-converted bit is subjected to exclusive OR with the bit from the receiver 405 and sent to the pattern detection circuit 408. The pattern detection circuit 408
It is determined whether or not the end of the packet has the above-described specific pattern, and the determination result is output together with the packet.

By using the second and third embodiments, an error or falsification can be detected even if the packet has no redundancy.

(Effect of the Invention) As described in detail above, according to the present invention, an error and tampering can be detected only by adding a specific pattern on the transmitting side and detecting the specific pattern on the receiving side. Is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
FIG. 4 is a block diagram showing the operating principle of the present invention, FIG. 3 is a block diagram showing the second embodiment of the present invention, and FIG.
The figure is a block diagram showing a third embodiment of the present invention. In the figure, 101, 102, 301, 302, 401, 402 are shift registers, 103, 303, 403 are code converters, 104, 304, 404 are exclusive ORs, 201 is an information source, and 202, 305 are pattern additions. Reference numeral 203 is an encoder, 204 is a decryptor, 205 and 408 are pattern detection circuits, 206 is a receiving purpose, 306, 307, 406 and 407 are registers, 308 is a transmitter, 309, 310, 409 and 410 are selectors. , 405 are receivers, respectively.

Claims (1)

[Claims] 1. Data comprising a transmitter for adding redundant data to a part of packet data and encrypting and outputting the data, and a receiver for decoding data from the transmitter and detecting the presence or absence of the redundant data. In the converter, the transmitter stores a digital sequence adding means for adding a redundant digit sequence to a part of the packet data and outputting it, and a latest N number of outputs of the digit sequence total adding means. 1 storage means, a second storage means for storing the latest M outputs of encrypted data, and an output digit of the digit series addition means depending on the stored contents of the first and second storage means. A third converting means for converting the encrypted data and outputting the encrypted data, wherein the receiver stores the latest N pieces of the decrypted data.
Storage means for storing the latest M pieces of input data
Storage means, second conversion means for converting the input data and outputting the decoded data depending on the stored contents of the third and fourth storage means, and an output of the second conversion means. And a means for detecting whether or not the redundant digit sequence added by the transmitter is present in the data converter.