JPH0677483A - Thin-film transistor and its manufacture - Google Patents
Thin-film transistor and its manufactureInfo
- Publication number
- JPH0677483A JPH0677483A JP10720392A JP10720392A JPH0677483A JP H0677483 A JPH0677483 A JP H0677483A JP 10720392 A JP10720392 A JP 10720392A JP 10720392 A JP10720392 A JP 10720392A JP H0677483 A JPH0677483 A JP H0677483A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- film
- silicon film
- layer
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はアモルファスシリコンを
用いた薄膜トランジスタの構造に関し、特にアクティブ
マトリクス型液晶ディスプレイの駆動用素子として用い
られる薄膜トランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor using amorphous silicon, and more particularly to a thin film transistor used as a driving element of an active matrix type liquid crystal display.
【０００２】[0002]
【従来の技術】従来の薄膜トランジスタの構造を図３に
示す。2. Description of the Related Art The structure of a conventional thin film transistor is shown in FIG.
【０００３】ガラス等の絶縁基板１上にアルミ、クロ
ム、タンタル等の金属をスパッタ法により成膜し、これ
をフォトリソグラフィとウエットエッチングの方法によ
りゲート電極２にパターニングする。A metal such as aluminum, chromium or tantalum is formed on an insulating substrate 1 such as glass by a sputtering method, and the gate electrode 2 is patterned by photolithography and wet etching.
【０００４】次にアモルファス窒化シリコン膜等のゲー
ト絶縁膜（５００ｎｍ）と、アモルファスシリコン膜
（３００ｎｍ）３と、リンをドープしたｎ型アモルファ
スシリコン膜（６０ｎｍ）７をプラズマＣＶＤ法により
真空中で連続成膜する。この時アモルファスシリコン膜
の成膜条件はＳｉＨ4 ＝３０ＳＣＣＭ、Ｈ2 ＝２００Ｓ
ＣＣＭ、圧力＝１００Ｐａ、高周波放電出力＝０．０１
Ｗ／ｃｍ2 で成膜時間は約４５分である。Next, a gate insulating film (500 nm) such as an amorphous silicon nitride film, an amorphous silicon film (300 nm) 3, and a phosphorus-doped n-type amorphous silicon film (60 nm) 7 are continuously formed in a vacuum by a plasma CVD method. Form a film. At this time, the film forming conditions of the amorphous silicon film are SiH 4 = 30 SCCM, H 2 = 200S
CCM, pressure = 100 Pa, high frequency discharge output = 0.01
The film formation time is about 45 minutes at W / cm 2 .
【０００５】次にアモルファスシリコンとｎ型アモルフ
ァスシリコン膜をフォトリソグラフィとドライエッチン
グの方法により島状に加工してアイランド層３及びオー
ミックコンタクト層７を形成し、さらに窒化シリコン膜
４も同様の方法により電極接続用のコンタクトホール
（図示省略）を形成する。その後、これらの上に再度ア
ルミ、クロム等の金属を成膜しこれをフォトリソグラフ
ィの方法によりソース電極５及びドレイン電極配線６を
パターニングする。Next, the amorphous silicon and the n-type amorphous silicon film are processed into an island shape by a method of photolithography and dry etching to form an island layer 3 and an ohmic contact layer 7, and a silicon nitride film 4 is also formed by the same method. A contact hole (not shown) for electrode connection is formed. After that, a metal such as aluminum or chromium is again formed on these, and the source electrode 5 and the drain electrode wiring 6 are patterned by the method of photolithography.
【０００６】次にチャネル形成のため、ゲート電極２上
のアイランド層上に残ったｎ型アモルファスシリコン膜
をドライエッチング法により除去する（以下、チャネル
エッチングと称する）。このときｎ型アモルファスシリ
コン膜７の除去が十分でないと薄膜トランジスタがＯＦ
Ｆ動作出来なくなるため、アモルファスシリコン層３ま
で堀込む必要がある。Next, in order to form a channel, the n-type amorphous silicon film remaining on the island layer on the gate electrode 2 is removed by a dry etching method (hereinafter referred to as channel etching). At this time, if the removal of the n-type amorphous silicon film 7 is not sufficient, the thin film transistor becomes OF
Since the F operation cannot be performed, it is necessary to dig up to the amorphous silicon layer 3.
【０００７】最後に堀込んだチャネルを保護するための
パシベーション膜８として窒化シリコン膜をプラズマＣ
ＶＤ法により成膜し電極接続用のコンタクトホール（図
示省略）をフォトリソグラフィの方法により形成してこ
の薄膜トランジスタは完成する。A silicon nitride film is used as plasma C as a passivation film 8 for protecting the finally dug channel.
The thin film transistor is completed by forming a film by the VD method and forming a contact hole (not shown) for electrode connection by the photolithography method.
【０００８】[0008]
【発明が解決しようとする課題】上述の薄膜トランジス
タはチャネルエッチングにおける堀込み深さとそのばら
つきを考慮して、アモルファスシリコンの膜厚を必要膜
厚に堀込みマージンを加えたかなり厚いものを用いてい
る。そのため、成膜時間が長くなりスループットが低下
すると言う問題点があった。The thin film transistor described above uses a considerably thick film obtained by adding the necessary margin to the required film thickness of amorphous silicon in consideration of the etching depth and its variation in channel etching. . Therefore, there is a problem that the film formation time becomes long and the throughput is lowered.
【０００９】[0009]
【課題を解決するための手段】本発明の薄膜トランジス
タとその製造方法は、以下に示す特徴を持つ。 （１）絶縁基板上にゲート電極、ゲート絶縁膜、島状に
加工したアモルファスシリコン半導体層、オーミックコ
ンタクト層、ソース及びドレイン電極を順次積層、パタ
ーニングしチャネル部分にオーミックコンタクト層をエ
ッチング除去した後パシベーション膜を積層、パターニ
ングして形成される逆スタガー型チャネル堀込み構造薄
膜トランジスタにおいて、前記アモルファスシリコン半
導体層を複数の異なる膜質のアモルファスシリコン膜の
積層構造とする。 （２）前記の内容加え、前記アモルファスシリコン半導
体層のゲート絶縁膜に接する側のアモルファスシリコン
膜厚が５０ｎｍ以上である。 （３）高周波放電出力０．０１Ｗ／ｃｍ2 以下の低パワ
ー且つ成膜圧力７０Ｐａ以下且つＳｉＨ4 ／Ｈ2 流量比
１：１０以上の高水素希釈率条件のプラズマＣＶＤ法で
アモルファスシリコン膜を形成し、その上に高周波放電
出力０．０３Ｗ／ｃｍ2 以上の高パワー条件且つ成膜圧
力１２０Ｐａ以上且つＳｉＨ4 ／Ｈ2 流量比１：３以下
の低水素希釈率条件のプラズマＣＶＤ法でアモルファス
シリコン膜を積層して２層構造のアモルファスシリコン
半導体層を形成する。The thin film transistor and the manufacturing method thereof according to the present invention have the following features. (1) A gate electrode, a gate insulating film, an island-shaped amorphous silicon semiconductor layer, an ohmic contact layer, a source and drain electrode are sequentially laminated on an insulating substrate, patterned, and then the ohmic contact layer is removed by etching from the channel portion, followed by passivation. In an inverted stagger type channel engraving structure thin film transistor formed by stacking and patterning films, the amorphous silicon semiconductor layer has a stacked structure of a plurality of amorphous silicon films having different film qualities. (2) In addition to the above contents, the amorphous silicon film thickness of the amorphous silicon semiconductor layer on the side in contact with the gate insulating film is 50 nm or more. (3) Amorphous silicon film is formed by plasma CVD method under the conditions of high power of 0.01 W / cm 2 or less of high-frequency discharge, film forming pressure of 70 Pa or less and SiH 4 / H 2 flow ratio of 1:10 or more and high hydrogen dilution ratio. Amorphous silicon is then formed by plasma CVD under high power conditions with a high-frequency discharge output of 0.03 W / cm 2 or more, a film forming pressure of 120 Pa or more, and a SiH 4 / H 2 flow ratio of 1: 3 or less. The films are stacked to form an amorphous silicon semiconductor layer having a two-layer structure.
【００１０】[0010]
【作用】アモルファスシリコン半導体層を複層化し、チ
ャネル界面に接する層は良質のアモルファスシリコンを
十分時間をかけて成膜し、その上のチャネルエッチング
の堀込みマージンとなる層は高速に成膜して成膜時間を
短縮することにより、スループットを損なわずに特性の
良い薄膜トランジスタを作製できる。[Function] The amorphous silicon semiconductor layer is made into a multi-layer, and the layer in contact with the channel interface is formed by depositing good quality amorphous silicon for a sufficient time, and the layer overlying the channel etching margin is formed at high speed. By shortening the film formation time by this, a thin film transistor with excellent characteristics can be manufactured without impairing throughput.
【００１１】[0011]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例である薄膜トランジスタの
縦断面図である。The present invention will be described below with reference to the drawings. FIG. 1 is a vertical sectional view of a thin film transistor which is an embodiment of the present invention.
【００１２】厚さ約１ｍｍの低アルカリガラス基板１上
に金属クロム（１００ｎｍ）をスパッタ法で成膜しこれ
をフォトリソグラフィとウエットエッチングの方法によ
り所定のパターンに加工してゲート電極（配線）２を形
成する。A metal chromium (100 nm) film is formed on a low-alkali glass substrate 1 having a thickness of about 1 mm by a sputtering method, and this is processed into a predetermined pattern by photolithography and wet etching, and a gate electrode (wiring) 2 is formed. To form.
【００１３】次にプラズマＣＶＤ法によりゲート絶縁膜
用の窒化シリコン膜（５００ｎｍ）４、第１アモルファ
スシリコン膜（１００ｎｍ）３−ａ、第２アモルファス
シリコン膜（２００ｎｍ）３−ｂ、オーミックコンタク
ト層となるｎ型アモルファスシリコン膜（６０ｎｍ）７
を真空中で連続成膜する。この時、第１アモルファスシ
リコン膜３−ａの成膜条件はＳｉＮ4 ＝２０ＳＣＣＭ、
Ｈ2 ＝２００ＳＣＣＭ、圧力＝６０Ｐａ、高周波放電出
力＝０．０１Ｗ／ｃｍ2 、第２アモルファスシリコン膜
３−ｂの成膜条件はＳｉＨ4 ＝１００ＳＣＣＭ、Ｈ2 ＝
２００ＳＣＣＭ、圧力＝１００Ｐａ、高周波放電出力＝
０．０３Ｗ／ｃｍ2 とする。Next, a silicon nitride film (500 nm) 4 for a gate insulating film, a first amorphous silicon film (100 nm) 3-a, a second amorphous silicon film (200 nm) 3-b, and an ohmic contact layer are formed by plasma CVD. N-type amorphous silicon film (60 nm) 7
Is continuously formed in vacuum. At this time, the film formation conditions for the first amorphous silicon film 3-a are SiN 4 = 20 SCCM,
H 2 = 200 SCCM, pressure = 60 Pa, high frequency discharge output = 0.01 W / cm 2 , film forming conditions for the second amorphous silicon film 3-b are SiH 4 = 100 SCCM, H 2 =
200SCCM, pressure = 100Pa, high frequency discharge output =
It is set to 0.03 W / cm 2 .
【００１４】次に第１、第２アモルファスシリコン膜及
びｎ型アモルファスシリコン膜をフォトリソグラフィと
ドライエッチングの方法によりゲート電極２及びその他
必要な部分上に所定のパターンに加工してアイランド層
３を形成する。そして残った窒化シリコン膜の所定の位
置にをフォトリソグラフィとドライエッチングの方法に
より電極接続用のコンタクトホール（図示省略）を開け
てゲート絶縁層４を形成する。この上に電極材として金
属クロム膜（２００ｎｍ）をスパッタ法により成膜しフ
ォトリソグラフィとドライエッチングの方法により所定
のパターンに加工してソース電極５及びドレイン電極６
を形成する。Next, the first and second amorphous silicon films and the n-type amorphous silicon film are processed into a predetermined pattern on the gate electrode 2 and other necessary portions by a method of photolithography and dry etching to form an island layer 3. To do. Then, a contact hole (not shown) for electrode connection is opened at a predetermined position of the remaining silicon nitride film by a method of photolithography and dry etching to form a gate insulating layer 4. A metal chromium film (200 nm) as an electrode material is formed thereon by a sputtering method and processed into a predetermined pattern by photolithography and dry etching methods to form a source electrode 5 and a drain electrode 6.
To form.
【００１５】次にチャネル形成のため、ゲート電極上部
のアイランド層上に残ったｎ型アモルファスシリコン膜
７を除去するため、ソース電極及びドレイン電極をマス
クとしてドレインエッチング法によりｎ型アモルファス
シリコン膜と第２アモルファスシリコン膜を合せて約１
５０ｎｍ除去する。エッチングの堀込み深さは±５０ｎ
ｍ程度の分布を持つが、前述のアモルファスシリコン膜
厚の設定により残りのアモルファスシリコン膜厚はトラ
ンジスタの特性を維持するのに十分な厚みを残してい
る。ソース電極５及びドレイン電極６の下に残ったｎ型
アモルファスシリコン膜はオーミックコンタクト層７と
なる。Next, in order to form a channel, in order to remove the n-type amorphous silicon film 7 remaining on the island layer above the gate electrode, the n-type amorphous silicon film and the first n-type amorphous silicon film are formed by the drain etching method using the source electrode and the drain electrode as a mask. Approximately 1 including 2 amorphous silicon films
Remove 50 nm. Etching depth is ± 50n
Although it has a distribution of about m, the remaining amorphous silicon film thickness remains sufficient to maintain the characteristics of the transistor due to the setting of the amorphous silicon film thickness described above. The n-type amorphous silicon film remaining under the source electrode 5 and the drain electrode 6 becomes the ohmic contact layer 7.
【００１６】最後に堀込んだチャネルを保護するための
パシベーション膜８として窒化シリコン膜をプラズマＣ
ＶＤ法により成膜しその後に電極接続用のコンタクトホ
ール（図示省略）をフォトリソグラフィの方法により所
定の位置に形成してこの薄膜トランジスタは完成する。A silicon nitride film is used as plasma C as a passivation film 8 for protecting the finally dug channel.
The thin film transistor is completed by forming a film by the VD method and then forming a contact hole (not shown) for electrode connection at a predetermined position by a photolithography method.
【００１７】本実施例による薄膜トランジスタの動作特
性を図４に示す。本発明による薄膜トランジスタでは第
１アモルファスシリコン膜に良質の膜を用いた事により
従来例に比べて移動度の高い良好なトランジスタ特性を
示す。また、従来例におけるアモルファスシリコン膜の
成膜時間は約４５分かかるが本実施例では第１アモルフ
ァスシリコン膜の成膜時間が約１７分、第２アモルファ
スシリコン膜の成膜時間が約５分の合計２３分と大幅な
短絡が可能となる。The operating characteristics of the thin film transistor according to this embodiment are shown in FIG. Since the thin film transistor according to the present invention uses a good quality film as the first amorphous silicon film, it exhibits good transistor characteristics with higher mobility than the conventional example. Further, the film formation time of the amorphous silicon film in the conventional example takes about 45 minutes, but in this embodiment, the film formation time of the first amorphous silicon film is about 17 minutes and the film formation time of the second amorphous silicon film is about 5 minutes. A total of 23 minutes and a large short circuit is possible.
【００１８】本発明におけるその他の実施例を図面を参
照して説明する。図２は本発明の他の実施例である薄膜
トランジスタの縦断面図である。Another embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a vertical sectional view of a thin film transistor which is another embodiment of the present invention.
【００１９】厚さ約１ｍｍの低アルカリガラス基板１上
に金属クロム（１００ｎｍ）をスパッタ法で成膜しこれ
をフォトリソグラフイとウエットエッチングの方法によ
り所定のパターンに加工してゲート電極（配線）２を形
成する。Metal chromium (100 nm) is deposited on a low-alkali glass substrate 1 having a thickness of about 1 mm by a sputtering method, and this is processed into a predetermined pattern by photolithography and wet etching, and a gate electrode (wiring) is formed. Form 2.
【００２０】次にプラズマＣＶＤ法によりゲート絶縁膜
用の窒化シリコン膜（５００ｎｍ）４、第１アモルファ
スシリコン膜（１００ｎｍ）３−ａ、第２アモルファス
シリコン膜（２００ｎｍ）３−ｂ、ｎ型アモルファスシ
リコン膜（６０ｎｍ）７を真空中で連続性膜する。この
時、第１アモルファスシリコン膜の成膜条件はＳｉＨ4
＝２０ＳＣＣＭ、Ｈ2 ＝２００ＳＣＣＭ、圧力＝６０Ｐ
ａ、高周波放電出力＝０．０１Ｗ／ｃｍ2 、第２アモル
ファスシリコン膜の成膜条件はＳｉＨ4 ＝１００ＳＣＣ
Ｍ、Ｈ4 ＝２００ＳＣＣＭ、圧力＝１００Ｐａ、高周波
放電出力＝０．０３Ｗ／ｃｍ2 とする。Next, a silicon nitride film (500 nm) 4 for a gate insulating film, a first amorphous silicon film (100 nm) 3-a, a second amorphous silicon film (200 nm) 3-b, and an n-type amorphous silicon film are formed by a plasma CVD method. The film (60 nm) 7 is a continuous film in vacuum. At this time, the film formation conditions for the first amorphous silicon film are SiH 4
= 20 SCCM, H 2 = 200 SCCM, Pressure = 60P
a, high frequency discharge output = 0.01 W / cm 2 , deposition conditions for the second amorphous silicon film are SiH 4 = 100 SCC
M, H 4 = 200 SCCM, pressure = 100 Pa, high frequency discharge output = 0.03 W / cm 2 .
【００２１】次に第１、第２アモルファスシリコン膜及
びｎ型アモルファスシリコン膜をフォトリソグラフィと
ドライエッチングの方法によりゲート電極２及びその他
必要な部分上に所定のパターンに加工してアイランド層
３を形成する。そして残った窒化シリコン膜の所定の位
置にフォトリソグラフィとドライエッチングの方法によ
り電極接続用のコンタクトホール（図示省略）を開けて
ゲート絶縁層４を形成する。この上に電極材として金属
クロム膜（２００ｎｍ）をスパッタ法により成膜しフォ
トリソグラフィとドライエッチングの方法により所定の
パターンに加工してソース電極５及びドレイン電極６を
形成する。Next, the first and second amorphous silicon films and the n-type amorphous silicon film are processed into a predetermined pattern on the gate electrode 2 and other necessary portions by a method of photolithography and dry etching to form an island layer 3. To do. Then, a contact hole (not shown) for electrode connection is opened at a predetermined position of the remaining silicon nitride film by a method of photolithography and dry etching to form a gate insulating layer 4. A metal chromium film (200 nm) is formed thereon as an electrode material by a sputtering method and processed into a predetermined pattern by photolithography and dry etching methods to form the source electrode 5 and the drain electrode 6.
【００２２】次にチャネル形成のため、ゲート電極上部
のアイランド層上に残ったｎ型アモルファスシリコン膜
を除去するため、ソース電極５及びドレイン電極６をマ
スクとしてドライエッチング法によりｎ型アモルファス
シリコン膜と第２アモルファスシリコン膜を合せて約１
５０ｎｍ除去する。エッチングの堀込み深さは±５０ｎ
ｍ程度の分布を持つが前述のアモルファスシリコン膜厚
の設定により残りのアモルファスシリコン膜厚はトラン
ジスタの特性を維持するのに十分な厚みを残している。
ソース電極及びドレイン電極の下に残ったｎ型アモルフ
ァスシリコン膜はオーミックコンタクト層７となる。Next, in order to form a channel, in order to remove the n-type amorphous silicon film remaining on the island layer above the gate electrode, an n-type amorphous silicon film is formed by dry etching using the source electrode 5 and the drain electrode 6 as a mask. About 1 for the second amorphous silicon film
Remove 50 nm. Etching depth is ± 50n
Although it has a distribution of about m, the remaining amorphous silicon film thickness remains sufficient to maintain the characteristics of the transistor by setting the above-mentioned amorphous silicon film thickness.
The n-type amorphous silicon film left under the source electrode and the drain electrode becomes the ohmic contact layer 7.
【００２３】最後に堀込んだチャネルを保護するための
パシベーション膜８をつける。成膜はプラズマＣＶＤに
より行うが窒化シリコン膜成膜前にＨ2 ガスだけをソー
スガスとして圧力＝１００Ｐａ、高周波放電出力＝０．
０２Ｗ／ｃｍ2 の条件でプラズマ放電し、チャネルエッ
チング後のアモルファスシリコン表面１０を処理し連続
して真空中で窒化シリコン膜を成膜する。その後に電極
接続用のコンタクトホール（図示省略）をフォトリソグ
ラフィの方法により所定の位置に形成してこの薄膜トラ
ンジタは完成する。Finally, a passivation film 8 for protecting the dug channel is attached. The film formation is performed by plasma CVD, but before the silicon nitride film is formed, only H 2 gas is used as a source gas, the pressure is 100 Pa, the high frequency discharge output is 0.
Plasma discharge is performed under the condition of 02 W / cm 2 , and the amorphous silicon surface 10 after channel etching is processed to continuously form a silicon nitride film in a vacuum. After that, a contact hole (not shown) for electrode connection is formed at a predetermined position by a photolithography method to complete the thin film transistor.
【００２４】本実施例ではチャネルエッチングによるア
モルファスシリコン膜へのダメージが緩和されるため特
性安定性が向上するという効果がある。In the present embodiment, the damage to the amorphous silicon film due to channel etching is mitigated, so that the characteristic stability is improved.
【００２５】[0025]
【発明の効果】以上説明したように本発明は逆スタガー
型チャネル堀込み構造の薄膜トランジスタにおいてアモ
ルファスシリコン膜のアイランド層を膜質の良い第１ア
モルファスシリコン膜と成膜速度の速い第２アモルファ
スシリコン膜の複層構造とする事によりトランジスタ特
性とスループットの双方を向上させる効果を有する。As described above, according to the present invention, in the thin film transistor having the inverted stagger type channel engraving structure, the island layer of the amorphous silicon film is formed of the first amorphous silicon film of good film quality and the second amorphous silicon film of high film formation rate. The multi-layer structure has the effect of improving both transistor characteristics and throughput.
【図１】本発明の１実施例の縦断面図。FIG. 1 is a vertical sectional view of an embodiment of the present invention.
【図２】本発明の異なる実施例の縦断面図。FIG. 2 is a vertical sectional view of a different embodiment of the present invention.
【図３】従来技術による薄膜トランジスタの縦断面図。FIG. 3 is a vertical sectional view of a conventional thin film transistor.
【図４】本発明の効果を示す薄膜トランジスタのゲート
電圧−電流特性曲線図。FIG. 4 is a gate voltage-current characteristic curve diagram of a thin film transistor showing the effect of the present invention.
１ ガラス基板 ２ ゲート電極 ３−ａ 第１アモルファスシリコン層 ３−ｂ 第２アモルファスシリコン層 ３ アイランド層 ４ ゲート絶縁膜 ５ ソース電極 ６ ドレイン電極 ７ オーミックコンタクト層 ８ パシベーション膜 １０ 水素放電処理領域 1 Glass Substrate 2 Gate Electrode 3-a First Amorphous Silicon Layer 3-b Second Amorphous Silicon Layer 3 Island Layer 4 Gate Insulating Film 5 Source Electrode 6 Drain Electrode 7 Ohmic Contact Layer 8 Passivation Film 10 Hydrogen Discharge Treatment Area
Claims (3)
膜、島状に加工したアモルファスシリコン半導体層、オ
ーミックコンタクト層、ソース及びドレイン電極を順次
積層、パターニングしチャネル部分のオーミックコンタ
クト層をエッチング除去した後パシベーション膜を積
層、パターニングして形成される逆スタガー型チャネル
堀込み構造薄膜トランジスタにおいて、前記アモルファ
スシリコン半導体層を複数の異なる膜質のアモルファス
シリコン膜の積層構造とした事を特徴とする薄膜トラン
ジスタ。1. A gate electrode, a gate insulating film, an island-shaped amorphous silicon semiconductor layer, an ohmic contact layer, a source and drain electrode are sequentially laminated and patterned on an insulating substrate, and the ohmic contact layer in the channel portion is removed by etching. A reverse stagger type channel engraving thin film transistor formed by laminating and patterning a rear passivation film, wherein the amorphous silicon semiconductor layer has a laminated structure of a plurality of amorphous silicon films having different film qualities.
て、前記アモルファスシリコン半導体層のゲート絶縁膜
に接する側のアモルファスシリコン膜厚が５０ｎｍ以上
である事を特徴とする薄膜トランジスタ。2. The thin film transistor according to claim 1, wherein the amorphous silicon film thickness of the amorphous silicon semiconductor layer on the side in contact with the gate insulating film is 50 nm or more.
膜、島状に加工したアモルファスシリコン半導体層、オ
ーミックコンタクト層、ソース及びドレイン電極を順次
積層、パターニングしチャネル部分のオーミックコンタ
クト層をエッチング除去した後パシベーション膜を積
層、パターニングして逆スタガー型チャネル堀込み構造
薄膜トランジスタを製造する方法において、高周波放電
出力０．０１Ｗ／ｃｍ2 以下の低パワー且つ成膜圧力７
０Ｐａ以下且つＳｉＨ4 ／Ｈ2 流量比１：１０以上の高
水素希釈率条件のプラズマＣＶＤ法でアモルファスシリ
コン膜を形成し、その上に高周波放電出力０．０３Ｗ／
ｃｍ2 以上の高パワー条件且つ成膜圧力１２０Ｐａ以上
且つＳｉＨ4 ／Ｈ2 流量比１：３以下の低水素希釈率条
件のプラズマＣＶＤ法でアモルファスシリコン膜を積層
して２層構造の前記アモルファスシリコン半導体層を形
成する事を特徴とする薄膜トランジスタの製造方法。3. A gate insulating film 3 of a gate electrode, an island-shaped amorphous silicon semiconductor layer, an ohmic contact layer, a source and a drain electrode are sequentially laminated and patterned on an insulating substrate, and the ohmic contact layer of a channel portion is removed by etching. In a method of manufacturing a thin film transistor having an inverted staggered channel formation structure by laminating and patterning a post-passivation film, a low power with a high frequency discharge output of 0.01 W / cm 2 or less and a film forming pressure of 7
An amorphous silicon film is formed by a plasma CVD method under a high hydrogen dilution ratio condition of 0 Pa or less and a SiH 4 / H 2 flow rate ratio of 1:10 or more, and a high frequency discharge output of 0.03 W /
The amorphous silicon film having a two-layer structure is formed by laminating amorphous silicon films by a plasma CVD method under a high power condition of cm 2 or more and a film forming pressure of 120 Pa or more and a SiH 4 / H 2 flow rate ratio of 1: 3 or less. A method of manufacturing a thin film transistor, which comprises forming a semiconductor layer.
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|---|---|---|---|
| JP10720392A JP2924441B2 (en) | 1992-04-27 | 1992-04-27 | Thin film transistor and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10720392A JP2924441B2 (en) | 1992-04-27 | 1992-04-27 | Thin film transistor and method of manufacturing the same |
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| Publication Number | Publication Date |
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| JPH0677483A true JPH0677483A (en) | 1994-03-18 |
| JP2924441B2 JP2924441B2 (en) | 1999-07-26 |
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