JPH067690B2 - Still image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition image display device, and more particularly to a still-image display device that repeatedly displays the same high-definition image to obtain a still image.

[Background of the Invention]

In recent years, development of high-definition image processing technology for improving the image quality of color televisions has become popular.

For example, Achiha and Ishikura: Proposal of motion-adaptive high-definition signal conversion system of color TV signal, Television Society 19
As described in the paper published at the 1982 National Convention, high-quality YC separation (Y is a luminance signal and C is a color signal) is performed to remove cross color, dot interference, etc.
Techniques such as converting 525-line interlaced scanning into 525-line non-interlaced scanning (in the case of the NTSC system) to eliminate image disturbance such as line flicker have been developed.

Hereinafter, a device for converting an input video signal into a high-definition signal by performing such high-quality YC separation and converting the 525-line interlaced scan into a 525-line non-interlaced scan will be described. The device is referred to as a device, and a device in which a display device such as a high-definition display is connected to the high-definition signal conversion device is referred to as a high-definition image display device.

FIG. 2 shows a block diagram of a general high definition image display device.

In FIG. 2, the input composite video signal V is A / D
It is converted into a digital signal by the converter 1, and the YC separation circuit 2
Are separated into a luminance signal Y and a color signal C by.

Here, the YC separation will be described in some detail.

In the NTSC system, the luminance signal Y and the color signal C are superimposed on the composite video signal V, and between the luminance signal Y and the color signal C, (1) in the first frame and ((1) in the second frame). 2)
Have a relationship.

Y + C (1) Y-C (2) That is, the polarity of the color signal C is inverted for each frame. Therefore, when the image by the input composite video signal V is a still image, this is used to (1) and (2)
By adding and halving the luminance signal Y, (1)
The color signal C is separated from the composite video signal V by subtracting (2) from the above and halving. still,
For this, a 2-frame memory is required. The above relationships are shown in (3) and (4).

{(Y + C) + (Y−C)} × 1/2 = Y (3) {(Y + C) − (Y−C)} × 1/2 = C (4) On the other hand, (1) and (2 The relationship of) is also established between adjacent scanning lines in the same field. Therefore,
In the case of a moving image, this is utilized to perform the operations (3) and (4) between adjacent scanning lines in the same field to perform YC separation.

By separating the luminance signal Y and the color signal C as described above, mutual interference between the luminance signal Y and the color signal C can be eliminated, and the image quality can be improved.

The YC separation circuit 2 is composed of a frame memory used in the case of a still image and a line memory used in the case of a moving image, and switching between the still image and the moving image is performed depending on the degree of movement of the image. It is like this.

The YC separation has been described above.

The output from the YC separation circuit 2 that has been subjected to such YC separation is then applied to the RGB conversion circuit 3 as shown in FIG. 2, where R (red), G (green), B ( Converted to a blue signal. Then, these three signals are input to the scanning line interpolation circuit 4, where they are converted into signals for 525 non-interlaced scanning, then converted into analog signals by the D / A converter 5, and displayed on the display 6. To be done.

In the device shown in FIG. 2, the RGB conversion circuit 3 is composed of a digital circuit, but it may be composed of an analog circuit, in which case it is installed after the D / A converter 5. .

There are various fields of use for the high-definition image display device as described above. For example, one of them is an education system. In an education system, an image display device (such as a general television receiver) is often used for visual education, but in that case, the viewer often observes the image for a long time, and Flickers may cause eye fatigue. Therefore, if a high-definition image display device is used instead, flicker does not occur in the image, and even if it is viewed for a long time, the eyes are not fatigued and effective learning can be performed.
That is, the high-definition image display device is very suitable for visual education.

Now, when using a high-definition image display apparatus in such an education system, the following usage methods can be considered, for example.

That is, a plurality of high-definition image display devices are used, and still images transmitted from one signal source are received by the high-definition image display devices in a time-division manner, and the same content is efficiently learned by a large number of people. To do so. To this end, each high-definition image display device captures the transmitted still image video signal within a time allotted at a certain moment, and then captures another still image video signal again. , It is necessary to repeatedly display the same screen on the display by using the captured video signal (hereinafter referred to as freeze).

However, in the conventional high-definition image display device,
There was no such freeze function, and little attention was paid to the freeze function.

[Object of the Invention]

It is an object of the present invention to provide a still image display device capable of displaying a high definition image and having a freeze function.

[Outline of Invention]

As described above, in the high-definition image display device, when the received video signal is a still image, the video signals of the first frame and the second frame are necessary to perform YC separation. Therefore, in order to provide the high-definition image display device with a freeze function to be a still image display device, it is necessary to capture at least two frames of video signals at the time of capturing video signals.

In the present invention, in order to achieve the above-mentioned object, the following was done, taking this into consideration.

That is, the present invention receives a signal indicating a freeze input from the outside (hereinafter referred to as a freeze indication signal),
After receiving it, the video signals of 2 frames are taken into the frame memory from the received video signals of several frames,
Then, after that, by reading out the video signals for two frames fetched from the memory, writing them again, and circulating them, the same signals are repeatedly read and repeatedly displayed on the display as the same screen, and still images can be displayed by freeze. It is the one.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a circuit diagram showing an embodiment of the present invention.
That is, the present invention is applied to the 2-frame memory section used in the YC separation circuit of the high definition image display device.

In FIG. 1A, 13 switches and 14 are 2-frame memories for storing video signals for 2 frames.

When the switch 13 is connected to a ₃ as shown in FIG. 1 (A), the composite video signal V of the external still image that has been AD converted is obtained.
Is written in the two-frame memory 14 via the switch B. When connecting the switch 13 to the b _3, the output V _M which is read from the second frame memory 14 is written again returned to the input via a switch 13. Switching of the contacts of the switch 13 is performed by the freeze control signal FRZ.

The YC separation is performed by the above-described calculation between the first frame and the second frame using the output V _M read from the 2-frame memory 14.

Therefore, if the switch 13 switches from a ₃ to b ₃ at a certain moment, the video signals for two frames written in the two-frame memory 14 at that moment after that will be repeated from the two-frame memory 14. As a result of being read and output, the same signal is converted into a high-definition signal via each circuit in the subsequent stage and repeatedly displayed as the same screen on the display. That is, the freeze display is displayed.

FIG. 1 (B) is a circuit diagram showing a concrete circuit example of the switch 13 of FIG. 1 (A).

In FIG. 1 (B), 15 and 16 are AND circuits, 17 respectively.
Is an OR circuit, and 18 is an inverter.

In FIG. 1B, when the freeze control signal FRZ = 1, the composite video signal V passes through the AND circuit 15 and the OR circuit 17 and is written in the two-frame memory 14. Further, when the freeze control signal FRZ = 0, the output V _M of the second frame memory 14 is written into the second frame memory 14 through the AND circuit 16, OR circuit 17. That is, the freeze occurs when the freeze control signal FRZ = 0.

Next, the freeze control signal FRZ generating means will be described with reference to FIGS. 3 and 4. FIG. 3 is a circuit diagram showing a generating means for generating the freeze control signal FRZ of FIG. 1, and FIG. 4 is a timing chart showing essential signals of FIG.

In FIG. 3, 19, 20, 22, 23, and 24 are D-type flip-flops (hereinafter abbreviated as D-FF), and 21 is NA.
It is an ND circuit.

As shown in FIG. 3, first, the received freeze instruction signal TIMP from the outside is applied as the D ₁ input of the D-FF 19, and the horizontal synchronizing signal HSYNC is applied as the clock input CK of the D-FF 19 and 20. To do. Then DF
A signal having a waveform as shown in the timing chart of FIG. 4 (A) is output from each output Q ₁ , Q _{2 of} F19, ₂₀ . Therefore, the inverted output Q ₁ of the D-FF 19 and the output Q _{2 of the} D-FF ₂₀
When the signals from the above are input to the NAND circuit 21, a pulse signal RESET having a pulse width of 1H (63.5 μS) is obtained as the output.

On the other hand, a signal FV obtained by dividing the vertical synchronizing signal VSYNC by 1/2 is applied as each clock input CK of the D-FFs 22, 23, 24, and the above-mentioned pulse signal RESET is applied as each reset input CL. Also, D-FF
A logic 1 (high level) is applied to the D input of 22.

As shown in the timing chart of FIG. 4 (B), when the pulse signal RESET is applied to each reset input CL,
The output Q ₃ = Q ₄ = Q ₅ = 0. After that, the output Q ₃ becomes 1 at the first rising edge of the signal FV. Then, at the second rising edge of the signal FV, Q ₄ = 1 and at the third rising edge of the signal FV.
Q ₅ = 1. Therefore, as the freeze control signal FRZ With, that is, Then, when FRZ = 1, the composite video signal V from the outside is stored in the 2-frame memory 14 shown in FIG. 1 (A) or (B).
Is written and FRZ = 0, the frame memory 14
Output V _M from is returned to the input. Therefore, Q ₅ = F
When RZ = 0, the video signals for two frames shown by, in FIG. 4 (B), are repeatedly displayed, resulting in freeze display.

In FIG. 3, since the horizontal synchronizing signal HSYNC is applied as the clock input of the D-FFs 19 and 20, the pulse width of the freeze indicating signal TIMP needs to be wider than the pulse width (63.5 μS) of the horizontal synchronizing signal HSYNC. The second
In the high-definition image display device shown in the figure, as a sampling pulse for A / D conversion, a frequency four times the subcarrier frequency, that is, about 14.3 MHz is used. Therefore, the pulse width of the freeze instruction signal TIMP is 63.5μ.
If it is narrower than S and wider than 70 S (14.3 MHz period),
In FIG. 3, it is also possible to use this sampling pulse instead of the horizontal synchronizing signal HSYNC.

〔The invention's effect〕

According to the still image display device of the present invention, a still image transmitted from one signal source can be time-divisionally received by a large number of high-definition image display devices and can be freeze-displayed. The effect is that the content can be efficiently learned by a large number of people.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing an embodiment of the present invention, FIG.
1B is a circuit diagram showing a concrete circuit example of the switch shown in FIG. 1A, FIG. 2 is a block diagram showing a general high-definition image display device, and FIG. 3 is a freeze control signal shown in FIG. FIG. 4 is a timing chart of the main signal of FIG. DESCRIPTION OF SYMBOLS 1 ... A / D converter, 2 ... YC separation circuit, 3 ... RGB conversion circuit, 4 ... Scan line interpolation circuit, 5 ... D / A converter, 6 ... Display, 7 ... High-definition signal conversion device, 13 ... switch,
14 ... 2 frame memory, 15, 16 ... AND circuit, 17 ... OR
Circuit, 18 ... Inverter, 19, 20, 22, 23, 24 ... D flip-flop, 21 ... NAND circuit.

Claims (2)

[Claims] 1. A memory for storing an input video signal,
In a still image display device having a YC separation circuit for separating the video signal into a luminance signal and a chrominance signal, the still image display device has two frames and the first frame signal and the second frame signal stored in the memory. Still image characterized by further comprising means for further separating into luminance signal and chrominance signal, means for generating image stillness (hereinafter referred to as freeze), and means for reading from the stored memory and rewriting and circulating. Display device. 2. The still image display device according to claim 1, wherein the means for generating the freeze has a shift register and generates a freeze signal only for two frame periods, and a video signal of two frames. Still image display device characterized by capturing.