JPH0674972B2 - Pattern defect detector - Google Patents

Description

TECHNICAL FIELD The present invention relates to a technique for binarizing image information with high reproducibility and high accuracy. For example, a pattern formed on a semiconductor element such as an LSI wafer can be used. The present invention relates to a method and apparatus for automatically inspecting appearance.

[Conventional technology]

Integrated circuits such as LSI tend to be highly integrated and miniaturized.
In forming such a fine wiring pattern, the detection of defects is important in determining the quality of the formation.

Detecting defects is no longer possible at the stage of allocating a large number of personnel and performing visual inspection, and automation of defect detection is an urgent task.

Therefore, the image information of the semiconductor element surface obtained from an optical microscope or an electron microscope is converted into electrical information by an image pickup tube, an image pickup element, or the like, and then predetermined signal processing is performed to detect a defect. The device and method are open to the public. For example, JP-A-57-196377 and JP-A-58-4663.
No. 6, JP-A-57-34402.

The common and indispensable constituent elements of these technologies are as follows. By referring to the conventional device shown in FIG. 20, the pattern formed on the semiconductor chip 2 can be reproducibly converted into a two-dimensional pattern from a fixed position with good electrical characteristics. It is to convert into a signal.

The operation will be briefly described using a conventional device.

The linear image sensors 5a and 5b have a self-scanning function and detect a pattern one-dimensionally. And XY table 7
The two-dimensional pattern of the chip 2 is detected by moving the LSI wafer 1 in the direction perpendicular to the scanning of the linear image sensor. 4a, 4b is an objective lens that collects the illumination light 3a, 3b on the chip, and expands the pattern of the chip to form an image on the image sensor, the electrical signal from the image sensor is A / D converter 11a, Converted to digital signal by 11b. Furthermore, the digital signal is 2
The binarization circuits 12a and 12b convert the binary signals to reach the determination circuit 13.

In such a conventional device, it is ideal that the circuit patterns and the like detected by the image sensors 5a and 5b have no positional deviation with respect to the predetermined coordinates, but at least the image sensors 5a and 5b detect them. It is required that the circuit pattern at the location has no displacement.

However, in reality, it is inevitable that the input patterns will be displaced due to the accuracy of the XY table on which the inspection object is placed, the chip arrangement accuracy, and the thermal deformation of the optical and mechanical systems. The defect determination is performed by correcting the positional deviation between the input patterns.

[Problems to be solved by the invention]

The conventional technology has the following problems. That is, as shown in FIGS. 21 (a) and 21 (b), when there is a positional deviation (alignment error) between, for example, the patterns of the first layer and the second layer of the multilayer pattern to be studied, the alignment by the conventional technique is performed. After that, when the mismatch detection is performed, the result is as shown in FIG. 21 (c), and it is impossible to detect only the defect. That is, if an alignment error exists, a defect smaller than the interlayer alignment error cannot be detected by discriminating only the defect, even if it is a fatal defect. The interlayer alignment error is an unavoidable positional deviation when forming a pattern, and if mismatch detection is performed by the conventional method, it is covered by the interlayer alignment error, and it is impossible to detect fine defects. In addition, the pattern may have minute irregularities and width deviations, and it is necessary to allow these to detect only defects.

Furthermore, when capturing a two-dimensional pattern, the analog signal from the image sensor is sampled and A / D converted. However, no measure is taken against the quantization error due to sampling, and the same analog signal is An error occurred when sampling more than once.

An object of the present invention is to provide a visual inspection method and apparatus for a multilayer pattern suitable for automation.

More specifically, there is provided a method and apparatus for eliminating the above-mentioned problems of the prior art and capable of detecting with high accuracy even if there is an interlayer alignment error, minute unevenness or difference in pattern line width between two sets of multilayer patterns to be compared. Is to provide.

Another object of the present invention is to provide a method and apparatus for drastically reducing the occurrence of an error when the same analog signal input from the image sensor is sampled twice or more.

[Means for solving problems]

The above object is achieved by combining the following technical elements. That is, in the appearance inspection technique of a multilayer pattern, (1) a multilayer pattern having a small contrast is not binarized but is compared with an adjacent chip as a multi-valued shade.

(2) Positioning is performed for each layer to allow an interlayer alignment error, and two chips are compared one by one.

(3) Masking is performed by making the matched portions between the inspected chips into a dead zone (don't care), and inspecting serially (serially) layer by layer, and inspecting all layers.

(4) A window is set for the non-coincidence portion, and light and dark gradients are compared for a plurality of pixels in the window.

(5) Digitize the input dark and light analog signals,
Interpolation between unit pixels is performed, and comparison is performed between interpolated pixels.

[Action]

(1) Since the analog signal from the image sensor is directly sampled and digitized, and the interpolation results of the digitized pixel data are compared, a positional deviation of less than one pixel can be ignored and the accuracy of comparison is significantly improved.

(2) The two chips are aligned and compared for each layer, and the alignment and comparison are repeated for the non-matching portions, so that the defect can be determined by peeling the pattern one by one. As a result, no trouble occurs due to the interlayer alignment error. In addition, it is possible to detect only defects by overcoming minute unevenness of patterns and differences in line width.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. As a photoelectric converter for converting an optical image of a multilayer pattern into an electric signal, any of a linear image sensor, a TV camera and the like can be used, but in the present embodiment, a linear image sensor is used, and the linear image sensor itself is used. A two-dimensional pattern of an LSI wafer is detected by scanning and an XY table that moves in the direction perpendicular to it. FIG. 1 is a block diagram of a pattern visual inspection device. The output of the linear image sensor 5 is converted into a digital signal by the A / D converter 11 and input to the edge detection circuit 15a. The A / D converter output is also input to the pixel memory 14, and at the same time, the corresponding pattern of the adjacent chip stored in the pixel memory is read from the pixel memory and input to the edge detection circuit 15b. By using the pixel memory, the pattern of the adjacent chip can be compared and inspected by one image sensor. The edge detection circuits 15a and 15b detect the edges of the pattern.

The misregistration detection circuit 18 shifts the binary pattern output from the edge detection circuits 15a and 15b, counts the number of mismatched pixels at the shifted position, and detects the amount of mismatch between the two binary patterns. Two count values that minimize the amount of movement in two orthogonal directions are output.

Also, the A / D converted digital signal output of the linear image sensor 5 and the output of the pixel memory are delayed by delay circuits 19a and 19b. The delay time is determined by the number M (for example, 1024) of pixels of the linear image sensor and the number N (for example, 256) of image sensor self-scanning required for alignment, and each of the delay circuits 19a and 19b is composed of a shift register having a bit number of M × N. To be done.

The alignment circuit 20 performs alignment by shifting the outputs of the delay circuits 19a and 19b by the alignment circuit 20 so that the optimal alignment state determined by the displacement detection circuit 18, that is, the amount of mismatch is minimized. Then, the matching portion erasing circuit 21 compares the brightness of the detected pixels aligned with each other, and erases a substantially matching area.

The coincidence portion erasing circuit 21 outputs a "dark defect" candidate in which the A / D converter output is darker than the pixel memory output and a "bright defect" candidate in a bright area for the area where the brightness does not coincide, and outputs the gradient. Input to the comparison circuit 30. The gradient comparison circuit 30 compares the brightness gradients of these areas that have become inconsistent in the coincidence part erasing circuit 21, determines a defect, and outputs an inconsistency. In addition, the output of the coincidence portion erasing circuit 21 is output to the second stage through the positional deviation detection circuit 18 and the delay circuits 31a and 31b of the second and subsequent stages.
It is input to the coincidence portion erasing circuit 21 on and after the second stage.

The misregistration detection circuit 18 masks the EXOR of the outputs of the edge detection circuits 15a and 15b with the output of the matching section erasing circuit 21 in the previous stage, and the matching section erasing circuit 21 outputs the current matching section with the output of the matching section erasing circuit in the previous stage Mask the erase circuit output.

The above is the mismatch detection circuit for the pattern of one layer, and the circuits of the same configuration are serially connected by the number of pattern layers. Then, the output of the gradient comparison circuit 30 at the final stage is adopted as a true defect. FIG. 1 is intended for a multi-layer pattern composed of two layer patterns, and is composed of two sets of single-layer pattern mismatch detection circuits.
The delay circuits 31a and 31b are circuits that delay the same time as the delay circuits 19a and 19b, and have the same hardware configuration.

Further, when the one-layer pattern or the two-layer pattern having no interlayer alignment error in the configuration of FIG. 1 is to be inspected, the mismatch of the outputs of the first-stage gradient comparison circuit is adopted as a defect.

Next, the details of each part will be described.

Referring to FIG. 2 (a), the edge detection circuits 15a, 15 of FIG.
A configuration example that can be used as b will be described. In the figure, reference numeral 150 is a three-stage shift register that receives, for example, an 8-bit digital video signal from the A / D converter 11 or the image memory 14, and a first-stage and a third-stage adder 151
The outputs of the second stage are supplied to the gain-2 amplifiers 152, respectively. The output of the adder 151 and the output of the amplifier 152 are the subtractor 15
3 and the difference signal output thereof is binarized in the binarization circuit 154, and the positional deviation detection circuit 18 is used as an edge detection signal.
Is supplied to. Shift register 150, adder 151, amplifier 15
The 2 and the subtractor 153 form a “1, −2,1” operator.

FIG. 2 (b) shows an edge detection circuit for detecting edges in eight directions of vertical, horizontal, and diagonal. The output of the A / D converter 11 or the pixel memory 14 is added to the 3 × 3 cutout circuit 24, and the edge is added. The operation is performed by four edge operators OP1 to OP4. Each edge operator may be the same as illustrated in Figure 2 (a). The output of operators OP1 to OP4 is a binarization circuit.
It is binarized by 154-1 to 154-4 and is all supplied to the OR circuit 25. The output of the circuit 25 is the shift registers 181a, 180a or the shift register 182a (the third
Figure) added.

Third configuration example used as the positional deviation detection circuit 18 in FIG.
Shown in the figure. From the output of the binarization circuit 154, 7 × 7 pixels composed of shift registers 180a to 180f for delaying the A / D conversion output of the linear image sensor 5 by one scanning circle and shift registers 181a to 181g of linear-in / parallel-out (other Example: 7x with 2D local memory of 9x9 pixels)
Cut out 7 pixels. On the other hand, the output of the other binarization circuit 154 is delayed by using the same shift registers 182a to 182c and 183 to synchronize the output with the central position of the local memory.

The output of the shift register 183 and the local memory bit output are E
The XOR circuits 184a to 184n take an exclusive OR to detect the number of mismatched pixels. However, a masking circuit 189 is provided between the EXOR circuit 184 and the counter 185 described below in the misregistration detection circuit of the second and subsequent stages, which causes a mismatch in the matching portion erasing circuit 21 (FIG. 1) of the preceding stage. The number of mismatched pixels is detected only for the area. The counters 185a to 185n count the number of unmatched pixels. Counter 185a-185n
Is cleared to zero every N scans of the linear image sensor, and the value is read out immediately before that, the number of mismatched pixels in the area of M pixels × N scans can be known. Since each bit output of the local memory is shifted for each pixel in the range of ± 3 pixels in the XY direction (two directions orthogonal to each other) with respect to the output of the shift register 183, the counters 185a to 185n have XY values. The number of mismatched pixels in each shift amount when the pixel input pattern by the direction is shifted is counted. Therefore, by checking which counter has the minimum value, the shift amount in the X and Y directions that minimizes the number of non-matching pixels can be found, and optimum alignment can be performed for each layer.

The minimum value detection circuit 186 (for example, composed of a comparison circuit) reads out the values of the counters 185a to 185n, selects the counter having the minimum value, and shifts 188 in the linear image sensor scanning direction (Y direction) and the right angle. The shift amount 187 in the direction (X direction) is output.

FIG. 4 shows a structural example used as the alignment circuit 20 of FIG. In the selection circuit 201, the delay circuit 19a and the shift registers 200a to 200 for delaying one scan by the shift amount 187.
The optimum shift position is selected from the output of f and input to the shift register 202. In addition, in the selection circuit 203, the shift amount 188
The optimum shift position in the scanning direction is selected by. Therefore, the local memory at the shift position where the mismatch amount is minimized is extracted from the output of the selection circuit 203.

On the other hand, by using the shift registers 204a to 204c and the shift register 205 which delay the output of the delay circuit 19b by one scanning, the pixel of the local memory at the position delayed by the same amount as the output of the shift register 183 of FIG. Extract. In this state, the pixel output of the local memory output from the selection circuit 203 is at the optimum shift position without displacement with respect to the pixel output of the local memory output from the shift register 205.

The coincidence portion erasing circuit 21 in FIG. 1 is a circuit for binarizing the difference from the output of the alignment circuit 20, and FIG. 5 shows an example of its configuration. The difference between the aligned pattern signals is subtracted 210
Generated by the threshold value −th ₀
If the _{value is} greater than -th ₀ , there is substantially no match and there is no defect, so a dead signal (don't care signal) is output. Similarly, the binarization circuit 212b binarizes with a threshold value th ₀ , and if it is smaller than th ₀ , there is substantially no defect and there is no defect signal.
n't care signal) is output. If they do not match, the former is a “dark defect” candidate and the latter is a “bright defect candidate”. However, in the coincidence part erasing circuit of the second and subsequent stages, the binarizing circuit 212
Masking circuits 214a and 214b are provided after a and 212b, and a region which is determined to be matched by the matching section erasing circuit in the preceding stage is insensitive (don't car) regardless of the outputs of the binarizing circuits 212a and 212b.
e).

FIG. 6 shows a detailed block diagram of the gradient comparison circuit 30 of FIG. 1, and FIG. 7 shows a concrete configuration example used as the gradient comparison circuit 30. In FIG. 6, a digital signal 300 aligned by taking the logical sum of the dark defect candidate 303, the bright defect candidate 303, which is the output of the coincidence portion erasing circuit by the logical sum circuit 32,
Obtain a binarization circuit for the absolute value of the difference of 301. From the detected defect candidates, the 3 × 3 window processing circuit 33 removes defect candidates with less than 3 pixels. The output of the window processing circuit 33 is
The amount of mismatch between the signals 300 and 301 is large, and the number of pixels is 3 × 3 pixels or more. Then signal 30 for these defect candidates.
The in-window gradient of 0,301 is obtained by the gradient detection circuits 34,35. By comparing the thus obtained gradients with each other by the comparison circuit 36, when the gradients are significantly different, it is detected as a defect.

Next, a configuration example that can be used for each unit in FIG. 6 will be described with reference to FIG. 3 × 3 composed of shift registers 330 and 331 for delaying one scan of the linear image sensor and serial-in / parallel-out shift register 332.
The AND circuit 335 is enabled by the pixel cutout circuit and the AND circuit 334 if the difference in brightness of the pixels in the 3 × 3 window is at least th ₀ (binarization threshold value in FIG. 5). )
, Otherwise disable. on the other hand,
The 3 × 3 pixel cutout circuit configured by the shift registers 340 and 341 and the serial-in / parallel-out shift register 342 cuts out 3 × 3 pixels from the signals 300 and 301 in synchronization with the AND circuit output 335. AND circuit output 335 outputs signals 300, 30
If the absolute value of the difference of 1 extends over 3 × 3 pixels and is equal to or greater than th _0, it is possible to enable the clipping circuit for 3 × 3 pixels. Extract the brightness from the 3x3 pixel clipping circuit,
Input to the subtractor 343 to detect the gradient (brightness gradient). The detected slope is compared with the slopes corresponding to the signals 300 and 301 by the comparison circuit 36, and is detected as a defect when the slopes are significantly different. The inside of the comparison circuit 36 is composed of a subtractor and a converter.

An example of the gradient is shown in FIGS. 8 (a) and 8 (b). Letting each pixel of the 3 × 3 pixel cutout circuit be A, B, ..., I, a gradient table consisting of a list of differences as shown in FIG. 8B can be created. If the values in the gradient tables are compared and there is even one significant difference between the signals 300 and 301, then there is a defect that causes the signals 300 and 301 to differ.

Another example of the gradient can be shown by a gradient table as shown in FIG. If the values in the gradient tables are compared and the values do not substantially match between the signals 300 and 301, then there is a defect that has caused the signals 300 and 301 to differ. The comparison of the gradient tables is performed as follows.

Δ1 = | (A-2E + I)-(A'-2E '+ I') | Δ2 = | (B-2E + H)-(B'-2E '+ H') | Δ3 = | (C-2E + G)-(C ' −2E ′ + G ′) | Δ4 = | (D−2E + F) − (D′−2E ′ + F ′) | If min (Δ1, Δ2, Δ3, Δ4) th ₀ …… determines whether a defect exists. To do. Where A '
Dashes such as ~ I 'indicate that the pixel signal is the signal 301, and A to I indicate that it is the pixel signal of the signal 300. The formula does not consider it as a defect if even one slope (second derivative) takes a value between the signals 300 and 301, and tolerates this, and conversely, does not take even one slope value. If so, it is determined that there is a defect.

The formula can also be written as

However Here, ∩ represents AND.

Of course, the equation can also be applied to the gradient table FIG. 8 (b). In this case, Δ1 = | (B−H) − (B′−H ′) | Δ2 = | (D−F) − (D′−F ′) | Δ3 = | (G−C) − (G′−) C ′) | Δ4 = | (I−A) − (I′−A ′) |

Another example of the gradient is shown in interpolation (interpolation) between pixels in FIG. As shown in the figure, a new pixel AE is created by interpolating the pixel E and the pixel A. Similarly, pixels BE, CE, ..., DE are created. Defect determination is performed using these pixels. That is, Δ1 = | E-E '| Δ2 = | AE-E' | Δ3 = | EB-E '| Δ4 = | CE-E' | Δ5 = | FE-E '| Δ6 = | IE-E' | Δ7 = | HE-E '| Δ8 = | GE-E' | Δ9 = | DE-E '| min (Δ1, Δ2, ..., Δ9) th ₀ ...... Here, pixel interpolation is performed as follows, for example. To do.

AE = (A + B + D + E) / 4 CE = (B + C + EzF) / 4 IE = (E + F + H + I) / 4 GE = (D + E + G + H) / 4 BE = (B + E) / 2 FE = (F + E) / 2 HE = (H + E) / 2 DE According to the equation = (D + E) / 2, it is possible to allow a sampling error by the image sensor 5 and the A / D converter 11 in FIG.

As shown in FIG. 8 (e), the value obtained by the image signal is the brightness sampled and digitized, and is the pixel D, E, F ... Therefore, the brightness information of the position between the pixels D and E is lost. And even if the same wafer is imaged by the same detection system at the sampling point,
The sampling points of the second sampling are different from those of the first sampling. Therefore, as shown in FIG. 8 (e), the first sampling point is marked with a circle and the second sampling point is marked with a cross. That is, An error within a pixel will occur. As described above, the sampling timing is slightly deviated, so that even if the image signals are aligned by the positional deviation detection circuit 18 and the alignment circuit 20 in FIG. 1, the sampling time interval T (pixel interval)
In principle, a displacement of less than 1/2 is inevitable. Therefore, when the pixel E ′ of the signal 300 and the pixel E of the signal 301 are aligned and compared, if E ′ is further compared with the interpolated pixels DE and FE, the alignment can be correctly performed in units of less than one pixel (sub-vixel). Therefore, according to the formula, the defect determination can be performed in a state in which the alignment error caused by the sampling is completely eliminated, and the reliability of the inspection can be significantly improved.

Gradient detection circuits 34, 35 shown in FIG.
An example of the structure (Fig. 6) is shown in Fig. 9 (a). The figure is 3 ×
The brightness gradient of 3 pixels is compared within a range in which 2 pixels around the corresponding point on the corresponding pattern are enlarged. In the figure, for example, the brightness gradients in the shaded areas are compared, but it is assumed that local alignment is performed by searching for the closest brightness gradient within a range of 7 × 7 pixels. By comparing the gradient values, it is determined whether or not there is a defect. Reference numerals 351 and 354 are shift registers, and other members may be the same as those in FIG. 7.

Further, as a special case of FIG. 9 (a), a window 351,
Each 354 has 1 x 1 pixel and 3 x 3 pixels, and the window 351
If the brightness of the pixel inside is close to the brightness within the range of 3 × 3 pixels in the window 354, it is considered that the local alignment is performed at that time, and the brightness is compared to determine whether it is a defect. It can also be determined.

This indicates that the present invention can be applied to a 1 × 1 pixel window when detecting a minute defect, and the brightness gradient defined by the 3 × 3 pixel window is applied to a 1 × 1 pixel window. It corresponds to the example.

FIG. 9 (b) shows the configuration of a gradient detection circuit using the interpolation gradient of FIG. 8 (d). In the figure, an interpolation pixel is obtained by an integration circuit, and the absolute value of the difference between the interpolation pixels AE to DE and E and the pixel E'corresponding to E is also detected. Then, the minimum value is detected from the absolute value of these differences, and this minimum value is binarized by the binarization circuit.

FIG. 10 shows an example in which the gradient comparison is performed on the non-coincidence regions obtained by binarizing with different threshold values, for example, th ₁ . In FIG. 6, the slope comparison is performed on the non-coincidence region detected by the coincidence part erasing circuit 21 of FIG. That is, the difference between the signals 300 and 301 is binarized by the threshold value th ₀ , and the logical sum of the obtained dark defect candidate and the bright defect candidate is calculated. Good. The aligned signals 300 and 301 (here, 8 bits) are input to the subtractor 311, and the EXOR circuit 312 detects the absolute value of the difference between 300 and 301. The absolute value of the difference is calculated by the comparator 320.
It is binarized by the threshold value th ₁ and input to the window processing circuit 33.

In FIG. 10, the absolute value of the difference between the two signals 300 and 301 is binarized by the binarization circuit 320, but as shown in FIG.
3 × composed of a shift register 321 and a serial-in / parallel-out shift register 322 from the absolute value of the difference of 1 ×
3 × 3 by 3 pixel cutout circuit and adder circuit 323
The sum of the absolute values of the differences in the brightness of the pixels may be calculated and binarized by the comparator 324.

The configuration example for realizing FIG. 1 has been specifically described above. Among these, the misregistration detection circuit 18 and the coincidence portion erasing circuit 21 are masking circuits 189 (FIG. 3) in the first and second stages.
And 214 (Fig. 5). These are outputs from 21 in the masking circuit 189 (dark defect candidate 302).
In 214, the outputs from 31a and 31b can also be realized by forcibly setting the outputs of the first stage to Low.

In the position shift detection circuit of FIG. 3, 7 × 7 pixels were cut out by a two-dimensional local memory and used for position shift detection. In general, this may be n × n pixels, and may be determined based on the positional deviation state of the detected image and the magnitude of interlayer alignment error.

Next, how the multi-layer pattern is actually inspected according to the present invention will be described in detail.

When comparing two chips close to each other, FIG. 12 (a),
As shown in (b), two-layer patterns f ₂ and g composed of corresponding first-layer patterns and second-layer patterns on two chips.
₂ is detected. There is an interlayer alignment error between the patterns f ₂ and g ₂ . The alignment circuit 20 in FIG. 1 aligns the first layer patterns with each other to obtain FIG. 12 (c).

Next, the coincidence portion erasing circuit 21 erases the area having the same brightness, that is, the first layer pattern. This first layer pattern erasing is performed for the detection pattern f ₂ . No change is made to the detection pattern g ₂ . Then, as shown in FIG. 12D, the first layer pattern in the pattern f ₂ is erased. The second layer pattern is also partially erased. After the first layer pattern is aligned, the erased area is masked by a masking circuit as a dead zone, and a part of the erased second layer pattern is detected as a mismatch when the second layer pattern is aligned. avoid. Therefore, in the case of FIG. 12 (d), the portions other than the solid line are masked. Then, these patterns and the detection pattern g ₂ are set by the alignment circuit 20 and the coincidence part erasing circuit 21 in the second stage.
(Fig. 12 (e)) is aligned and the remaining second layer pattern is inspected. As a result, only defects can be detected as shown in FIG.

In this way, alignment is performed for each layer pattern that constitutes the multilayer pattern, and by comparing the brightness and erasing the matching area serially by the number of layer patterns, it is possible to detect only defects. It will be possible.

Next, the operation of the coincidence section erasing circuit 21 will be described in more detail with reference to FIGS. 13 and 14. Figure 13 (a), (b) is 2
It is an example of the multilevel signal waveform of the multilayer patterns f ₃ and g ₃ of one semiconductor IG structure. When this is aligned and superimposed (positioning will be described later with reference to FIGS. 15 and 16) and displayed, the state shown in FIG. 13 (c) is obtained. For example, first a defect erases the dark since f ₃ -g _3> -th ₀ if f ₃ from the normal portion
Figure 3 (d) is obtained. Here, the shaded portion represents a region that satisfies f ₃ −g ₃ > −th ₀ , and is a dead zone (don't care) because it is considered that f ₃ and g ₃ substantially match. th ₀ is a threshold value for determining whether the patterns f and g match.
It can be seen from FIG. 13 (d) that no defect was present in the first layer pattern. However, the second layer pattern cannot be erased because the alignment is incomplete due to an interlayer alignment error.

Next, when FIG. 14 (a) (same as FIG. 13 (d)) and FIG. 14 (b) (same as FIG. 13 (b)) are aligned and displayed in superposition, the second layer pattern Alignment is done and it becomes FIG. 14 (c). When the determination of f ₃ −g ₃ > −th ₀ is made again, a mismatch occurs between the first layer patterns, but the mismatch is masked by the masking circuit 214a of FIG.
Only the desired defect is detected as shown in FIG. Thirteenth
Figure, has been described as a dark defect candidates example in Figure 14, f ₃ -
It is also possible to determine g ₃ <th ₀ , which is executed by the binarizing circuit 212b and the masking circuit 214b in FIG. Such defect candidates are extracted from the pattern f ₃ to g ₃ in the.

Next, using FIG. 15 and FIG. 16, the edge detection circuit 15a,
The operation of 15b and the positional deviation detection circuit 18 (see FIG. 1 for both) will be described. FIGS. 15A and 15D show patterns f ₄ and
This is the signal waveform of g ₄ . These signal waveforms are shown in Fig. 2 (a).
Circuit by indicated by | -2 | becomes Applying operator, dark low level of only edges can be detected, FIG. 15 (b), (e) to obtain a binary binarization threshold th ₃ in this The darkest point on the edge of the pattern when converted to "1",
Other than that can be set to “0”, as shown in FIG.
Obtain (f). Therefore, the alignment can be performed by the pattern matching method using the binarized patterns representing these edge patterns. The misregistration detection circuit of FIG. 3 realizes this, and the binarized edge pattern is f
_{If we say e} , g _e , Then, S (u, v) is measured, and the amount of u, v that minimizes S (u, v) is obtained. However, like the coincidence portion erasing circuit 21, the shaded portions shown in FIGS. 13 and 14 are masked by the masking circuits 189a to 189a in FIG. 3, and the coincidence portion erasing circuit 21 up to the preceding stage does not coincide. S (u, v) is calculated only for the region where Here, (i, j) represents the coordinates of the pixel of the pattern.

Since the patterns f ₄ and g ₄ are originally two-dimensional signals, the 16th pattern
An operator is used to detect edges of a pattern having a two-dimensional spread as shown in the figure. This can be realized by the circuit configuration shown in FIG.

Next, how the gradient comparison circuit 30 extracts only true defects from defect candidates will be described with reference to FIGS. 17 to 19. In FIGS. 17 and 18, when the corresponding multilayer patterns f ₅ and g ₅ on the two chips are aligned (FIG. 17 (a)), the matching portion erasing circuit 21 takes the difference in brightness ( First
17 (b)), where the absolute value of the brightness difference is larger than the binarization threshold th ₀ , the following is obtained. That is, when the inter-layer alignment error is small, when the fine irregularities of the pattern are present, or when the line width of the pattern is slightly different depending on the chip, as shown in FIG. 17 (c), the original pattern f ₅ , The brightness gradient of g ₅ tends to have almost the same value, or there is no big difference even if they do not have the same value. However, when these are large, the brightness gradient (c) of the patterns f ₅ and g ₅ has completely different values, as shown in FIGS. 18 (a) to 18 (c).

Interlayer alignment errors, pattern irregularities, and differences in line width must be detected as defects if they are larger than a certain reference value, but must be regarded as normal if they are smaller than a certain reference value. Of these, the magnitude of the inter-layer alignment error can be judged from the outputs u and v of the misregistration detection circuit 18 of FIG. 1, and the inter-layer alignment error can be tolerated by repeating the alignment and erasing the coincident portion for each layer. .

It will be shown below that the unevenness in the pattern and the difference in the line width can be tolerated by the gradient comparison circuit 30. As shown in Figure 19, the pattern
When f ₆ and g ₆ are aligned, the alignment may not be complete due to the minute unevenness of the pattern (or the difference in line width),
There is a one-pixel alignment error as shown in FIG. 19 (b), a two-pixel alignment error as shown in FIG. 19 (c), and a three-pixel alignment error as shown in FIG. 19 (d). At this time, a 3 × 3 window is applied by the window processing circuit 33 shown in FIG. 6 to a region having a large amount of mismatch.

Although this window is two-dimensional, for convenience of explanation, it will be described below in one dimension. With this window, a mismatch defect having a size of 3 × 3 pixels is detected. In the case of FIG. 19B, there is no problem because the amount of pattern mismatch is small. 19th
In the case of FIG. 6C, the amount of mismatch of the illustrated pixels becomes large and the pixel becomes a defect candidate. Focusing on the shape of the area surrounded by the curve, a 3 × 3 window is applied to this defect candidate, and the gradient detection circuits 34 and 35 shown in FIG.
When the brightness gradients of the two patterns are obtained and the brightness gradients are compared by the comparison circuit 36, it is found that they are almost the same, and therefore there is a small local displacement. In the case of FIG. 19 (d), the mismatch amount of the pixels shown in the figure becomes large and the pixel becomes a defect candidate. It can be seen that the brightness gradients within the 3 × 3 window have slightly different values, and the positional deviation is larger than in the case of FIG. 19 (c). By the value of this gradient,
You can judge whether it is defective.

As described above, according to the embodiment shown in FIG. 1, only defects can be reliably detected regardless of the interlayer alignment error, the minute unevenness of the pattern, and the minute dimensional difference of the line width.

It should be noted that FIG. 1 is intended for a multi-layer pattern consisting of two layer patterns, and is constituted by two sets of single-layer pattern mismatch detection circuits. However, actually, even in the case of a multi-layer pattern, the interlayer alignment error does not exist in all the layer patterns, and the defect determination can be performed by serially connecting the number of mismatch detection circuits equal to or less than the number of layers. Needless to say, the pattern can be inspected further.

Further, in the explanation of FIG. 12, it is assumed that the alignment is performed from the first layer pattern, but it is actually impossible to select whether the alignment is performed from the first layer pattern or the second layer pattern. Due to the restriction that the number of non-matching pixels in the edge image is minimized, the alignment should be performed from the layer pattern having the thick edge, but either order may be given first on the basis of the defect determination principle.

Further, although the comparison inspection is realized by one image sensor and the image memory in FIG. 1, it goes without saying that the present invention can be applied to an apparatus for performing the comparison inspection using two image sensors as shown in FIG. .

〔The invention's effect〕

According to the present invention, it becomes possible to detect a defect from an inspection target having a low contrast. Specifically, it is possible to detect only defects regardless of the error of interlayer alignment, the minute unevenness of the pattern, and the minute difference of the line width. Therefore, it can contribute to the automation of the pattern inspection.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 (a).
2 is a diagram showing a configuration example of the edge detection circuit of FIG. 1, and FIG. 2 (b) is a configuration example of a circuit for detecting edges in eight directions configured using the edge detection circuit of FIG. 2 (a). Showing the figure,
FIG. 3 is a diagram showing a configuration example of the position shift detection circuit of FIG. 1, FIG. 4 is a diagram showing a configuration example of the alignment circuit of FIG. 1, and FIG. FIG. 6 is a diagram showing a configuration example of the circuit, FIG. 6 is a detailed block diagram of the gradient comparison circuit of FIG. 1, FIG. 7 is a diagram showing a configuration example of the gradient comparison circuit of FIG. 1, and FIG. ) Is a diagram showing a detection window of 3 pixels × 3 pixels, FIG. 8 (b) is a diagram showing a gradient table composed of the difference of 2 pixels, and FIG. 8 (c) is a component of the second derivative using 3 pixels. 8D shows a gradient table, FIG. 8D shows interpolation using a value obtained by interpolating between two pixels as a detection window, and FIG. 8E shows an error of less than one pixel due to the difference in sampling. Fig. 9 (a) shows Fig. 8 (d).
6 is a diagram showing a configuration example of the gradient detection circuit of FIG. 6 not using the interpolation gradient of FIG. 6, and FIG. 9 (b) is a configuration example of the gradient detection circuit of FIG. 6 using the interpolation gradient of FIG. 8 (d). FIG. 10, FIG. 10 is a view showing a part of FIG. 5 for obtaining a mismatch area by binarizing with different thresholds, FIG. 11 is a view showing another configuration example corresponding to FIG. 10, Figure 12 shows the comparison procedure of multilayer patterns 1
A diagram showing an example, (a) shows the diagram showing a detection pattern f ₂ which is one subject of comparison, (b) is a diagram showing a detection pattern g ₂ is the other object of comparison, (c) is The figure which shows the result of having performed mutual alignment of the pattern of the 1st layer by the alignment circuit of FIG. 1, the figure which shows the result of erasing the area | region where (a) corresponded, (e) is description. FIG. 13 is a diagram showing the same pattern as (b) drawn for the sake of convenience, FIG. 13 (f) is a diagram showing the result of aligning the patterns (d) and (c) of the second layer, and FIG. a row of comparison procedure of the multi-layer pattern a diagram illustrating using a multi-level signal waveforms, (a) shows a signal waveform f ₃ of the detection pattern which is one subject of comparison, (b)
Is a diagram showing the signal waveform g ₃ of the detection pattern which is the other target of the comparison, (c) is a diagram showing the result of alignment of the first layer pattern, and (d) is the matching portion of the first layer pattern. Figure 14 shows the result of erasing, and Figure 14 shows the comparison procedure of multilayer patterns.
It is a figure which shows an example using a multilevel signal waveform, (a) is a 1st figure.
Similar to FIG. 13 (d), a diagram showing the result of erasing the coincident portion of the first layer pattern, (b) similar to FIG. 13 (b), the signal waveform g ₃ of the detection pattern which is the other target of comparison. Showing the figure,
(C) is a diagram showing the result of aligning the second layer pattern, (d) is a diagram showing the result of detecting only defects because the masking circuit masks the mismatch, and FIG. 15 is a diagram showing the edge detection procedure. FIGS. 3A and 3B are diagrams showing an example, FIGS. 5A and 5D are diagrams showing signal waveforms f ₄ and g ₄ of a detection pattern which is one of the comparison targets and the other, respectively, and FIGS. FIGS. 16 (c) and 16 (f) are diagrams showing the result of applying the edge detection operator, respectively, and FIGS. 16 (c) and 16 (f) are the results of binarizing using the binarization threshold. FIG. 17 is a diagram showing an example in which an acceptable mismatch pattern is processed by the gradient comparison circuit of FIG. 1, and FIG. 17A is a diagram showing two multilayers to be compared. shows the results of alignment of the pattern in the signal waveform _{f 5, g 5, (b} ) the first Shows the result of taking the absolute value of the difference between a match portion erase circuits (a), (c) is a diagram showing a signal waveform f ₅ and g ₅ each slope of (a), FIG. 18 not acceptable FIG. 6 is a diagram showing an example in which a mismatch pattern is processed by the gradient comparison circuit of FIG. 1, in which (a) shows a signal waveform obtained by aligning two multilayer patterns to be compared.
f ₅ and g ₅ are shown, (b) is a diagram showing the result of taking the absolute value of the difference of (a) in the coincidence part erasing circuit of FIG. 1, (c) is the signal waveform f ₅ of (a) And FIG. 19 are graphs showing inclinations of g ₅ respectively, and FIG. 19 is a graph showing that the gradient comparison circuit of FIG. 1 can tolerate the unevenness of the pattern and the difference in the line width. FIG. 6B is a plan view of two patterns, FIG. 9B is a diagram showing signal waveforms f ₆ and g ₆ when there is a 1-pixel alignment error, and FIG. 8C is a signal when there is a 2-pixel alignment error. FIG. 2D is a diagram showing waveforms f ₆ and g ₆ , FIG. 2D is a diagram showing signal waveforms f ₆ and g ₆ when there is an alignment error of three pixels,
FIG. 0 is a diagram showing an outline of an apparatus for comparison using two image sensors, and FIG. 21 shows that the defect detection accuracy decreases when the comparison target having an alignment error is aligned by the conventional technique. a diagram showing, (a) is a plan view of a multi-layer pattern f ₁ which is one subject of comparison, (b) is a plan view of a multilayer pattern g ₁ which is the other object of comparison, (c) the second FIG. 6 is a diagram showing the result of aligning layer patterns with each other. 5 ... Image sensor, 11 ... A / D converter, 14 ... Pixel memory, 18 ... Misregistration detection circuit, 21 ... Matching section erasing circuit, 30 ... Gradient comparison circuit.

Front page continuation (72) Inventor Makidaira Tan 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Pref., Institute of Industrial Science, Hitachi, Ltd. (56) Reference JP-A-61-212708 (JP, A) JP-A-61-151410 (JP, A) JP-A-59-159005 (JP, A) JP-B 1-60766 (JP, B2) JP-B 3-45762 (JP, B2) JP-B 4-53253 (JP, B2) JP-B 61-4174 (JP, B2)

Claims (5)

[Claims] 1. A sample having a plurality of circuit patterns formed so as to be the same and consisting of a plurality of superposed layers perpendicular to the pattern surface on a two-dimensional plane along the pattern surface. In a pattern defect detection device for detecting a defect of the circuit pattern by inputting image signals of portions corresponding to each other of the two circuit patterns and performing positional deviation detection, alignment and comparison, the image signal is converted. A misregistration detection circuit that detects the edge of the pattern from the obtained multivalued digital signal, inputs the binarized signal, and outputs the misregistration amount; and
A pattern defect detection device having at least two sets of circuits for performing alignment based on the amount of displacement after delaying the digital signal. 2. With respect to a sample having a plurality of circuit patterns formed to be the same, the image signals of the portions corresponding to the two circuit patterns are input to perform the positional deviation detection, the positional alignment and the comparison. In the pattern defect detecting device for detecting a defect of the circuit pattern, a circuit for detecting the edge of the pattern from a multi-valued digital signal obtained by converting the image signal and binarizing the detected edge, A pattern defect detection device having an edge detection circuit having a circuit configuration in which an operator for causing the edge to appear is applied to a digital signal. 3. A sample having a plurality of circuit patterns formed so as to be identical to each other is input with image signals of portions of the two circuit patterns corresponding to each other to perform misregistration detection, alignment and comparison. In the pattern defect detecting device for detecting the defect of the circuit pattern, the multi-valued digital signal obtained by converting the image signal is delayed for alignment, and then the two circuit patterns are mutually A pattern defect detection apparatus having a circuit for taking an absolute value of a difference between corresponding pixels, taking a logical sum in a region where the absolute values are compared, and then binarizing it. 4. A sample having a plurality of circuit patterns formed so as to be identical to each other is inputted with image signals of portions of the two circuit patterns corresponding to each other, to perform positional deviation detection, alignment and comparison. In the pattern defect detecting device for detecting the defect of the circuit pattern, a signal obtained by binarizing the edge of the pattern detected from the multi-valued digital signal obtained by converting the image signal is inputted, and the position A displacement detection circuit that outputs a displacement amount, a circuit that delays a multi-valued digital signal obtained by converting the image signal, and then performs alignment based on the displacement amount, Pattern having a circuit for inputting a digital signal of a value and a signal obtained by binarizing the digital signal and interpolating and comparing the vicinity of pixels corresponding to each other of the two circuit patterns Recessed detection device. 5. With respect to a sample having a plurality of circuit patterns formed to be the same, image signals of portions of the two circuit patterns corresponding to each other are input to perform misregistration detection, alignment and comparison. In the pattern defect detecting device for detecting the defect of the circuit pattern, a signal obtained by binarizing the edge of the pattern detected from the multi-valued digital signal obtained by converting the image signal is inputted, and the position A displacement detection circuit that outputs a displacement amount, a circuit that delays a multi-valued digital signal obtained by converting the image signal, and then performs alignment based on the displacement amount, Pattern defect having a circuit for inputting a digital signal of a value and a signal obtained by binarizing the digital signal and comparing the gradients in the vicinity of pixels corresponding to each other of the two circuit patterns. Detection device.