JPH0669829A - Receiver made into ic - Google Patents

Abstract

PURPOSE:To improve local oscillation signal leak characteristics and second- order and third-order distortion characteristics by making this receiver into an IC while using a GaAS FET, and composing a tuner circuit of a balanced circuit. CONSTITUTION:The tuner circuit is composed of three IC of an RF amplification IC 502, mixer IC 504 and demodulation IC 505 and the RF amplification IC, and the mixer IC are composed of GaAs IC having satisfactory distortion characteristics. An image signal pressing filter 503 is arranged between the RF amplification IC 502 and the mixer IC 504, and an intermediate frequency filter 513 are arranged between the mixer IC 504 and the demodulation IC 505. The entire circuit is composed of the balanced circuit. On the other hand, gain control is performed by an RF AGC circuit 507 and an IF AGC circuit 510 in the mixer IC 504, and by delay circuits 527 and 528 the gain control is performed first from the IF AGC 510. Thus, the tuner circuit improving the distortion characteristics, oscillation signal leak characteristics and S/N characteristics can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC receiver including a television tuner which receives a received high frequency signal and outputs a baseband signal. More specifically, VHF band and UHF band terrestrial television signals (including CATV signals) transmitted using the AM modulation system, and satellite broadcast signals (BS signals and CS signals transmitted using the FM modulation system). The present invention relates to an IC receiver that includes a tuner circuit that selectively receives a signal (including a signal) and converts it into an intermediate frequency signal and outputs the intermediate frequency signal. The television signal may be referred to as a TV signal hereinafter.

[0002]

2. Description of the Related Art A tuner circuit of a conventional satellite broadcasting receiver is disclosed in magazines of Sharp Technical Report No. 45 (June 1990) p.
As shown in 80 to p82, the intermediate frequency circuit and the demodulation circuit are integrated into an IC, but the input high frequency circuit is composed of discrete components. In addition, the signal transmission between the circuits is performed in the unbalanced signal format.

AM-modulated VHF band and UHF
Band TV signals (including CATV signals) and FM-modulated SHF band satellite broadcast signals are down-converted 1
When a general receiving system receives a GHz band intermediate frequency signal, each broadcast wave signal has a different frequency band, so that different tuner circuits are required, the configuration becomes complicated, and its operation is not easy. . Therefore, for example, as one of the means for solving these problems, as a receiving device using the same tuner circuit for a TV signal and a BS signal, Japanese Patent Application Laid-Open No. 57-3
As described in Japanese Unexamined Patent Publication No. 9628, there is known a circuit device which converts a BS signal into a frequency of an empty channel in a UHF band or a VHF band, and causes the TV signal tuner circuit to receive the frequency-converted BS signal together with a TV signal. There is.

[0004]

In the prior art, since the circuit section for processing the input high frequency signal is composed of discrete parts and the signal transmission is performed in the unbalanced signal format, the local oscillation signal leakage characteristic, There is a problem that it is difficult to secure the second-order and third-order distortion characteristics. Further, there is a problem that the number of parts is large and the circuit becomes complicated.
A first object of the present invention is to provide local oscillation signal leakage characteristics, secondary,
An object of the present invention is to provide an IC receiver including a tuner circuit having excellent third-order distortion characteristics.

Further, in the prior art, since the BS signal is down-converted into the TV signal frequency band and received by the TV tuner circuit together with the TV signal, the band is set to about 20 MHz for the TV in order to pass the TV signal. Since the BS signal having a wide band of 27 MHz passes through the filter in the tuner circuit, the BS signal is deteriorated, and as a result, the demodulation characteristic of the BS signal is deteriorated.

As an application example of the tuner circuit,
For example, a BS signal is converted into a frequency of an empty channel in the UHF band or the VHF band, and the frequency-converted BS signal and T
When a V signal (including a CATV signal) is transmitted by the same cable and distributed to a plurality of TV tuner circuits, an oscillation signal from another tuner circuit leaks in one tuner circuit, and the leak signal leaks. There is a problem in that the oscillation signal overlaps with the frequency-converted BS signal band (that is, the TV signal band in the UHF band or the VHF band) to cause interference.

A second object of the present invention is to solve the above problems and to provide a terrestrial TV signal (CATV) in the VHF band and the UHF band.
(Including signals) and BS or CS signals,
As a receiving device that outputs an intermediate frequency signal of a terrestrial TV signal when receiving a terrestrial TV signal and outputs an intermediate frequency signal of a BS or CS when receiving a BS signal or a CS signal and demodulates it, GaAs having excellent high frequency characteristics and third-order distortion characteristics (Gallium arsenide) FET (field effect transistor) or Si
IC using (silicon) bipolar transistor
It is an object of the present invention to provide an integrated circuit (IC) receiving device that has a simple configuration, a simple circuit configuration, excellent operability, and a small amount of unnecessary radiation from a signal input terminal.

A third object of the present invention is to provide automatic gain control (A
One or a plurality of GC) circuits are arranged before and after the frequency conversion circuit, and these AGC circuits are controlled in a specific relation to the intensity of the input signal.
It is an object of the present invention to provide an IC type receiver capable of facilitating the operation setting of the GC circuit.

A fourth object of the present invention is to provide the above-mentioned IC-equipped receiver equipped with a plurality of second intermediate frequency band pass filters (for example, SAW filters) for receiving BS signals and CS signals having different signal bands. It is an object of the present invention to provide an IC receiver in which the gain control amount of the AGC circuit is not constant because the insertion loss of the second intermediate frequency bandpass filter is different, and the deterioration of the reception characteristics can be improved.

[0010]

In order to achieve the above first object, the high frequency circuit portion of the tuner circuit is provided with a GaAs FET.
Was made into an IC. At this time, the IC is made into two chips, an RF amplification IC and an AGC mixer circuit IC, and an image suppression variable tuning filter is arranged between these two chips. With this configuration, a tuner circuit having excellent third-order distortion characteristics and a small number of parts can be obtained. Further, all circuits including the above-mentioned IC are configured by balanced circuits, and the coupling between circuits is also coupled by balanced signals. With this configuration, a tuner circuit having excellent second-order distortion characteristics and local oscillation signal leakage characteristics can be obtained.

In order to achieve the above-mentioned second to fourth objects, in the present invention, a frequency conversion circuit used for receiving a terrestrial TV signal and for receiving a BS signal or a CS signal is also used, and when receiving a terrestrial TV signal and a BS. When the signal or the CS signal is received, the terrestrial TV intermediate frequency signal and the BS or CS intermediate frequency signal are switched and output.
At this time, at least the frequency conversion circuit, the intermediate frequency amplification circuit, and the oscillation amplification circuit are I
By converting to C, it is possible to obtain an IC receiver which is excellent in high frequency characteristics and third-order interference distortion characteristics.

Further, in order to suppress unnecessary radiation to the input terminal of the local oscillation signal and the power supply circuit and second-order distortion or even-order distortion generated in the frequency conversion circuit, each circuit constituting the receiving device is of a balanced type. Then, the circuits are coupled by balanced transmission. Further, in order to facilitate the operation setting of the AGC circuit, a voltage limiter circuit or a DC amplification circuit and a voltage limiter circuit are arranged between the gain variable circuit and the control circuit which form the AGC circuit.

Further, in order to improve the deterioration of the reception performance due to the second intermediate frequency bandpass filters having different insertion losses,
A gain variable circuit that operates according to the insertion loss of the filter is arranged between the frequency conversion circuit and the second intermediate frequency bandpass filter. Alternatively, the second intermediate frequency bandpass filter and the amplifier circuit are arranged in the same package or integrally formed.

[0014]

In terms of achieving the first object, GaAsF
ET has excellent high-frequency characteristics, and since the current-voltage characteristics exhibit secondary characteristics, it is possible to obtain a tuner device that is excellent in high-frequency characteristics and strong against third-order distortion interference by forming an IC using a GaAs FET. . Furthermore, the balanced circuit
It is characterized by canceling even-order distortion components and canceling in-phase unwanted radiation input from current, ground, etc. Therefore, by configuring a tuner circuit with this balanced circuit, a tuner circuit that is strong against second-order distortion interference and leaking of unwanted radiation such as a local oscillation signal can be obtained.

The following is a description regarding the achievement of the second to fourth objects. The GaAs FET is superior to the Si bipolar transistor in high frequency characteristics and strain characteristics. Therefore, a circuit for processing a high frequency signal, that is, a frequency conversion circuit is made into an IC by using a GaAs FET, so that a distortion characteristic is excellent and a wide band reception signal from a VHF band terrestrial TV signal to a BS or CS signal is processed. Therefore, a system (reception device) capable of selectively receiving a terrestrial TV signal, a CATV signal, a BS signal and a CS signal with a single tuner circuit can be configured.

By making each circuit a balanced type and coupling the circuits by balanced transmission, even-order distortion components generated in each circuit cancel each other out. Also, with respect to unnecessary radiation such as a local oscillation signal to the power supply wiring and the ground wiring, the interference due to the unnecessary radiation is small due to the in-phase signal suppression. This makes it possible to construct a system (reception device) that is excellent in suppressing second-order distortion and has a small leakage of unwanted radiation such as a local oscillation signal.

The voltage limiter circuit arranged between the variable gain circuit and the control circuit constituting the AGC circuit changes up to the set voltage of the gain control voltage from the control circuit, but does not change it higher or lower. Works like
Further, the DC amplification circuit and the voltage limiter circuit can arbitrarily set the change sensitivity of the gain control voltage from the control circuit and the fixed voltage. As a result, the operation start points and the sensitivities of the AGC circuits arranged before and after the frequency conversion circuit can be arbitrarily selected with the same gain control voltage.

The variable gain circuit provided between the frequency conversion circuit and the plurality of second intermediate frequency band pass filters having different pass bands corresponds to the second intermediate frequency band pass filter corresponding to the switching signal of the second intermediate frequency band pass filter. It works to cancel the insertion loss of the pass filter. As a result, the gain of the tuner circuit does not fluctuate, so that the gain control amount of the AGC circuit becomes constant and the reception characteristics are not deteriorated. Further, in a circuit element in which a plurality of second intermediate frequency bandpass filters having different pass bands and an amplifying circuit are arranged or integrally configured in the same package, the gain of the amplifying circuit causes the insertion loss of the plurality of second intermediate frequency bandpass filters. Selected to be the same. As a result, the circuit element becomes a second intermediate frequency bandpass filter having the same insertion loss and different pass bands,
In the tuner circuit using this circuit element, the overall gain does not change even if the pass band of the circuit element is changed.
The gain control amount of the C circuit is also constant, and the deterioration of reception characteristics is eliminated.

[0019]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 1 is a block diagram showing an embodiment for achieving the first object of the present invention. This is a block diagram of a tuner circuit that selects a desired signal from the high frequency signal input from the terminal 501, demodulates it further, and outputs a baseband signal from the terminal 506. The high frequency signal input from the terminal 501 is The signal is converted into a balanced signal by the RF amplification IC 502, and is mixed through the image signal suppression filter 503.
It is input to C504. Mixer IC504 is RFAG
C circuit 507, mixer circuit 508, transmission circuit 509, I
A resonance circuit 5 for oscillation, which is composed of a FAGC 510.
11 is arranged outside the mixer IC 504, and the oscillation circuit 5
09 is connected. The balanced signal input to the mixer IC 504 is gain-controlled by the RFAGC circuit 507, mixed with the oscillation signal from the oscillation circuit 509 by the mixer circuit 508, converted into an intermediate frequency signal, and further gain-controlled by the IFAGC circuit 510. After that, the mixer IC 504 outputs the balanced signal.

The balanced signal output from the mixer IC 504 is passed through the intermediate frequency filter 513 to the demodulation IC 50.
It is input to 5 as a balanced signal. In the demodulation IC 505, the baseband signal is output from the output terminal 506 via the intermediate frequency amplifier 514 and the FM demodulation circuit 515. The FM demodulation circuit 515 outputs an automatic gain control voltage (hereinafter, AGC voltage) and an automatic frequency control voltage (hereinafter, AFC voltage), and the AGC voltage is RFAG in the mixer IC 504.
The delay circuit 52 is added to the C circuit 507 and the IFAGC circuit 510.
7, the gain control is performed before the IFAGC circuit 510, and the AFC voltage is applied to the oscillation resonance circuit 511 to control the oscillation frequency.

According to this embodiment, the tuner circuit is composed of the RF amplification IC 502, the mixer IC 504, and the demodulation IC 505.
The RF amplification IC and the mixer IC are composed of GaAs ICs having excellent distortion characteristics, the image signal suppression filter 503 and the intermediate frequency filter 513 are arranged between the ICs, and the whole circuit is composed of a balanced circuit. As a result, a tuner circuit excellent in distortion characteristics, oscillation signal leakage characteristics, and the like can be obtained. In addition, the gain control is performed by the RFA in the mixer IC504.
The tuner circuit having good S / N characteristics can be obtained by performing the gain control in the GC circuit 507 and the IFAGC circuit 510 and by performing the gain control first in the delay circuits 527 and 528 from the IFAGC circuit 510.

FIG. 2 shows a second embodiment for achieving the first object. This is a block diagram of a tuner circuit as in the first embodiment. A high frequency signal input from a terminal 501 is converted into a balanced signal by an RF amplification IC 502, and a mixer IC 504 is passed through an image signal suppression filter 503.
Entered in. The mixer IC 504 is an RF AGC circuit 5
07, a mixer circuit 508, an oscillation circuit 509, and an IF amplification circuit 526. An oscillation resonance circuit 511 is arranged outside the mixer IC 504 and connected to the oscillation circuit 509. The oscillation frequency of the oscillation circuit 509 is changed by applying the tuning voltage output from the tuning circuit 512 to the resonance circuit 511 to select the desired signal.

The balanced signal input to the mixer IC 504 is gain-controlled by the RFAGC circuit 507 and mixed with the oscillation signal from the oscillation circuit 509 by the mixer circuit 508,
After being converted into an intermediate frequency signal and amplified by the IF amplifier circuit 526, it is output as a balanced signal from the mixer IC 504.
The balanced signal output from the mixer IC 504 is input to the demodulation IC 505 as a balanced signal via the intermediate frequency filter 513. In the demodulation IC 505, the IFAGC circuit 5
25, the baseband signal is output from the output terminal 506 via the demodulation circuit 515. The AGC voltage output from the demodulation circuit 515 is the RFAGC in the mixer IC 504.
Circuit 507 and IFAGC circuit 525 in demodulation IC 505
To the IFA via the delay circuits 257 and 259.
The gain control is applied prior to the GC circuit 525, while the ACF voltage is applied to the oscillation resonance circuit 511,
Performs oscillation frequency control.

According to this embodiment, the tuner circuit is composed of three ICs of the RF amplification IC 502, the mixer 504, and the demodulation IC 505. The RF amplification IC and the mixer IC are GaAs ICs having excellent distortion characteristics, and an image is formed between the ICs. By disposing the signal suppression filter 503 and the intermediate frequency filter 513, and by configuring the entire circuit with a balanced circuit, distortion characteristics,
A tuner circuit having excellent oscillation signal leakage characteristics can be obtained. In addition, the gain control is performed by the RFAGC in the mixer IC504.
Circuit 507 and IFAGC circuit 525 in demodulation IC 505
The gain control is performed by the delay circuits 527 and 529 before the IFAGC circuit 525, and the baseband signal is output from the output terminal 506. The AGC voltage output from the demodulation circuit 515 is the RFAGC in the mixer IC 504.
Circuit 507 and IFAGC circuit 52 in demodulation IC 505
5 is applied via the delay circuits 527 and 529 to the IF
The AGC circuit 525 and the RF AGC circuit 527 are configured to perform gain control in this order, while the AFC voltage is applied to the oscillation resonance circuit 511 to control the oscillation frequency.

According to this embodiment, the tuner circuit is composed of the RF amplification IC 502, the mixer IC 504, and the demodulation IC 505.
It is composed of two ICs, the RF amplification IC and the mixer IC are GaAs ICs having excellent distortion characteristics, and the image signal suppression filter 503 and the intermediate frequency filter 513 are arranged between the ICs.
In addition, by configuring all circuits with balanced circuits, it is possible to obtain a tuner circuit having excellent distortion characteristics, oscillation signal leakage characteristics, and the like. In addition, the gain control is performed by the RFAGC in the mixer IC504.
Circuit 507, IFAGC circuit 525 in demodulation IC 505
By performing gain control in the order of the IFAGC circuit 525 and the RFAGC circuit 507 by the delay circuits 527 and 529, a tuner circuit having a good S / N characteristic can be obtained.

FIG. 3 shows a third embodiment for achieving the first object. Similar to the first embodiment, this is a block diagram of a tuner circuit. A high frequency signal input from a terminal 501 is converted into a balanced signal by an RF amplification IC 502 and input to a mixer IC 504 via an image signal suppression filter 503. . The mixer IC 504 is an RF AGC circuit 50.
7, a mixer circuit 508, an oscillation circuit 509, and an IFAGC circuit 510. An oscillation resonance circuit 511 is arranged outside the mixer IC 504 and connected to the oscillation circuit 509. A tuning circuit 512 is connected to the resonance circuit 511,
Select the desired signal.

The balanced signal input to the mixer IC 504 is gain-controlled by RFAGC times and 507, and is mixed with the oscillation signal from the oscillation circuit 509 by the mixer circuit 508,
After being converted into an intermediate frequency signal and gain-controlled by the IFAGC circuit 510, it is output as a balanced signal from the mixer IC 504. The balanced signal output from the mixer IC 504 is input to the demodulation IC 505 as a balanced signal via the intermediate frequency filter 513. In the demodulation IC 505, a tuner circuit having excellent characteristics can be obtained via the IFAGC circuit 525 and the demodulation circuit 515. The gain control is performed by the RFA in the mixer 504.
GC circuit 507, IFAGC circuit 510, demodulation IC 50
5, the IFAGC circuit 525 in FIG.
In 528 and 529, the gain control is performed in the order of the IFAGC circuit 525, the IFAGC circuit 510, and the RFAGC circuit 507. The AFC voltage output from the demodulation circuit 515 is applied to the oscillation resonance circuit 511 to control the oscillation frequency.

Various embodiments for achieving the second to fourth objects of the present invention will be described below. FIG. 4 is a block diagram showing such an embodiment of the present invention. 100 is an input terminal for a terrestrial TV broadcasting signal in the VHF band, 101 is an input terminal for a terrestrial TV broadcasting signal in the UHF band, 102 is an input terminal for a first intermediate frequency signal of BS or CS (down-converted 1 GHz signal), 1a to 1c are input filters, 2a to
2c, 6, 8 and 13a, 13b are high frequency amplifier circuits, 3a
3c is a variable tuning filter, 4 is a first switching circuit, 5 is a one-chip integrated portion, 7 is a frequency conversion circuit, 9 is a local oscillation signal amplification circuit, 10 is an intermediate frequency filter, and 11 is a second
Switching circuit, 12a and 12b are intermediate frequency band pass filters, 14a and 14b are demodulation and gain control circuits, and 15 is a third
Switching circuits, 16a to 16c variable oscillation circuits, 17 channel selection control circuits, 50 AGC control voltage switching circuits, 103 terrestrial TV broadcast signal demodulation output terminals, and 104 BS or CS demodulation output terminals. 5 is a semi-insulating substrate of GaAs, for example.

The VHF band signal, the UHF band signal, and the first intermediate frequency signal of BS or CS input to the input terminals 100, 101 and 102 respectively are input filters 1a to 1c.
The band is selected in a wide band by the high frequency amplifier circuit 2a ...
Amplified by 2c, unnecessary wave signals such as image interference signals are removed by the variable tuning filters 3a to 3c, input to the first switching circuit 4, selectively output to the high frequency amplification circuit 6 by the tuning control circuit 17, and the frequency The conversion circuit 7 frequency-converts the intermediate frequency of the terrestrial TV or the second intermediate frequency of BS or CS, and the second switching circuit 11
According to the respective intermediate frequency band pass filters 12a
To 12b are selectively output by the channel selection control circuit 17, further amplified by the high frequency amplifier circuits 13a and 13b, and the intermediate frequency signals are demodulated by the respective demodulation circuits 14a and 14b.

In the first operation mode, the tuning control circuit 17 converts the output signal from the variable tuning filter 3a into the terrestrial TV intermediate frequency signal by using the oscillation signal from the variable oscillation circuit 16a, and then the second terrestrial TV intermediate frequency signal. In the operation mode, the output signal from the variable tuning filter 3b is converted into the terrestrial TV intermediate frequency signal by using the oscillation signal from the variable oscillation circuit 16b,
In the third operation mode, the switching circuits 4, 15 and the like are arranged so that the output signal from the variable tuning filter 3c is converted into the second intermediate frequency signal of BS or CS by using the oscillation signal from the variable oscillation circuit 16c. The anti-resonance state of the intermediate frequency filter 10 in the first and second operation modes to the terrestrial TV intermediate frequency and in the third operation mode to the second intermediate frequency of BS or CS. To control.

In the first operation mode, the tuning control circuit 17 turns on only the power supply to the high frequency amplifier circuits 2a and 13a, the variable oscillation circuit 16a and the demodulation circuit 14a, and in the second operation mode. , High frequency amplifier circuits 2b and 13a, variable oscillation circuit 16b, and demodulation circuit 14a
In the third operation mode, only the power supply to the high frequency amplifier circuits 2c and 13b, the variable oscillating circuit 16c and the demodulation circuit 14b is controlled to be on, and the AGC switching circuit 50 is controlled to the on state. Is the first
In the second operation mode, the gain control voltage of the demodulation circuit 14a (gain control voltage determined by the level of the signal input to the demodulation circuit 14a) is applied to the gain control terminals of the high frequency amplification circuits 6 and 8, and In the operation mode No. 3, the gain control voltage of the demodulation circuit 14b is applied to the gain control terminals of the high frequency amplifier circuits 6 and 8.

In this circuit, an input filter 1, a high frequency amplifier circuit 2, a variable tuning filter 3, a switching circuit 4, a high frequency amplifier circuit 6, a frequency conversion circuit 7, a high frequency amplifier circuit 8, an intermediate frequency filter 10, a switching circuit 11 and an intermediate circuit. Each circuit of the frequency band pass filter 12, the high frequency amplifier circuit 13, and the demodulation circuit 14 is composed of a balanced type circuit, and the circuits are coupled by balanced transmission, and the unbalanced output of the variable oscillation circuit 16 is unbalanced by the switching circuit 15. Balance-balance conversion is performed, and the local oscillation signal amplifier circuit 9 and the frequency conversion circuit 7 are coupled by balanced transmission.

Generally, terrestrial TV signals, BS or CS
Input signal is transmitted coaxially and becomes an unbalanced input. In the present invention, the unbalanced-balanced conversion of the input signal is performed by the input filter 1.
It is done in. According to this embodiment, since the unbalanced-balanced conversion of the input signal also serves as the function of the input filter, it is not necessary to provide a new unbalanced-balanced conversion circuit, and the circuit can be downsized. In addition, since the unbalanced side can be grounded directly, for example, the series inductance of the capacitor may cause insufficient grounding as compared with the conversion method in which one side of the base input of the differential amplifier circuit is grounded by the capacitor, and the circuit becomes unstable. There is no.

FIG. 5 shows an input filter 1 used in the present invention.
This is a configuration example of a and 1b, which is a variable tuning type. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. 19 and 25, 26 and 27 are capacitors, 18a and 18b are electromagnetically coupled coils, and 20 and 2
Reference numerals 1 and 24 are resistors, and 22 and 23 are variable capacitance diodes.

The unbalanced signal input from the input terminal 100 or 101 is converted into a balanced signal by the coils 18a and 18b and applied to the balanced input terminals of the high frequency amplifier circuits 2a and 2b in the next stage. Also, the variable tuning filter 3 is
Mainly composed of the coil 18b, the capacitor 19, and the variable capacitance diodes 22 and 23, the tuning voltage V _T is applied to the terminal 2
05, the capacitances of the variable capacitance diodes 22 and 23 are changed to obtain a desired tuning frequency. According to this embodiment,
As described above, since one side of the unbalanced side coil 18a can be directly grounded, the parasitic inductance component of the capacitor does not provide sufficient grounding and the conversion characteristics deteriorate as compared with the method of grounding one side of the input of the differential amplifier circuit with a capacitor. There is no such thing.

FIG. 6 shows an input filter 1c used in the present invention.
This is a configuration example of a variable tuning type. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. The operating frequency of the input filter 1c is about 1
GHz to about 2 GHz, which is higher than the terrestrial TV signal. Therefore, for the coil 18 shown in FIG. 5, the resonance frequency is increased by using 25a and 25b which are single-strand lines, strip lines, or microstrip lines.

FIG. 7 shows an example of the configuration of the variable tuning filters 3a and 3b used in the present invention. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. 26, 27 and 33 are capacitors, 29, 30 and 32
And 41, 40 and 34 are resistors, 28a, 28b and 31a,
Reference numeral 31b is a variable capacitance diode, 35 is an amplifier circuit for a buffer, and 37a and 37b are electromagnetically coupled coils.
The pass band is the capacitor 33 and the variable capacitance diode 28.
a, 28b, the coil 37a, the capacitor 33, the variable capacitance diodes 31a, 31b, and the coil 37b are determined by the parallel resonance system, and are transmitted to the output side by the coupling of the coils 37a, 37b.

The tuning voltage is applied to the terminal 206 to change the capacitances of the variable capacitance diodes 28a and 28b to obtain a desired pass band. Since the resonance system is arranged at the input and output with respect to the input filter of FIG. 5, the band becomes narrow and the selectivity of the band increases. The resistors 29, 30, 32, 34 are for bias feedback of the variable capacitance diodes 28a, 28b and 31a, 31b, and are arranged symmetrically so as not to disturb the balance of the resonance system. According to the present embodiment, the balanced output of the high frequency amplifier circuit 2a or 2b can be selected and transmitted to the amplifier circuit 35 of the next stage without deterioration.

FIG. 8 shows an example of the configuration of the variable tuning filter 3c used in the present invention. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. The operating frequency of this variable tuning filter is approximately 1 GHz to 2 GHz.
z, which has a higher frequency than the terrestrial TV signal. Therefore,
Coupling lines 40a and 40b formed of a single-line line, a strip line, a microstrip line, or the like are used for the coils 37a and 37b shown in (3) to increase the resonance frequency. In addition, the variable capacitance diode 28a,
Bias feedback resistors 28b, 31a and 31b are connected to the middle points of the coupling lines 40a and 40b.

FIG. 9 is a block diagram showing another embodiment of the present invention. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. In this embodiment, the gain control is performed by the high frequency amplifier circuits 2a, 2b, 2c and 13a,
13b. Due to the gain control circuit output in the demodulation circuit 14a, in the first operation mode, the high frequency amplifier circuits 2a and 13a, and in the second operation mode,
The high frequency amplifier circuits 2b and 13a perform gain control. Third
In the operation mode, the high frequency amplifier circuits 2c and 13b perform gain control by the output of the gain control circuit in the demodulation circuit 14b.

FIG. 10 is a block diagram showing still another embodiment of the present invention. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. In the present embodiment, the second intermediate frequency band pass filters 12b and 12c of BS or CS having different bandwidths are used. The bandpass filters 12b and 12c are, for example, the same center frequency and have a bandwidth of 27 MHz for BS and 32 for CS.
Different from MHz, the output of the high frequency amplification circuit 8 is selectively input by the second switching circuit 11 and transmitted to the high frequency amplification circuit 13b. Further, the gain of the high frequency amplifier circuit 8 is changed in conjunction with the second switching circuit 11.

When the outputs of the band pass filters having different bandwidths are demodulated by the same demodulation circuit, the insertion loss of the band pass filters, for example, in the surface acoustic wave filter (SAW filter), the insertion loss increases as the bandwidth becomes wider. That is, the bandwidth is about 20 dB at 27 MHz, whereas it is about 30 dB at 32 MHz. Therefore, in order to obtain the same receiver performance in both bandwidths, the gain control amount of the AGC is increased by the insertion loss. It was difficult because it changed. According to the invention, the bandpass filters 12b, 12c
Since the difference in the insertion loss of the high frequency amplifier circuit 8 can be compensated by changing the gain of the high frequency amplifier circuit 8 in conjunction with the switching circuit 11,
It is possible to reduce the fluctuation of the receiver performance due to the change of the gain control amount of C.

FIG. 11 is a block diagram showing another embodiment of the present invention. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. In this embodiment, the variable tuning type input filters shown in FIGS. 5 and 6 of the above-described embodiment are used as the input filters 1a and 1b, and the gain control is performed by using the high frequency amplifier circuits 2a, 2b, 6 and 8 and 13a. , 1
3b and voltage control circuits 51a, 51b and 52a, 52b at the gain control circuit outputs in the demodulation circuits 14a, 14b.

The output of the gain control circuit in the demodulation circuit 14a causes the high frequency amplifier circuits 2a and 1 to operate in the first operation mode.
In the second operation mode of 3a, the high frequency amplifier circuits 2b and 13a perform gain control. In the third operation mode, the gain control circuit output in the demodulation circuit 14b interlocks with the high frequency amplification circuits 6 and 13b and the second switching circuit 11 to control the gain of the high frequency amplification circuit 8. Voltage control circuit 5
1a, 51b and 52a, 52b are demodulation circuits 14a, 14
When the control voltage output of the gain control circuit in b is input, an output (k> 0) times the input is generated until the control voltage exceeds a preset reference voltage, and when the reference voltage is exceeded, a specific voltage is output. It is equipped with a means for generating.

FIG. 12 is a diagram for explaining an operation example of the gain control and voltage control circuits 51a, 51b, 52a and 52b of this embodiment. Here, the variable gain high frequency amplifier circuits 2a and 2b arranged on the input side of the frequency conversion circuit 7 of FIG.
And 6 are the first AGC, and the variable gain high-frequency amplifier circuits 13a and 13b arranged on the output side of the frequency conversion circuit 7 are the second
Called AGC.

FIG. 12A shows the demodulation circuits 14a and 14a.
The gain control amount of each high frequency amplifier circuit with respect to the gain control voltage generated by b is shown. Regarding the gain control characteristic peculiar to the high frequency amplifier circuit, the gain control amount linearly decreases from 50 dB to 0 dB as the gain control voltage increases from 0 to 5V. In contrast, the first
Generally, the AGC and the second AGC are the first AA and the second AGC in order to prevent deterioration of the noise characteristic of the receiver when receiving a weak input signal.
In the region where the input signal is large, the gain control is performed by the first AGC in order to prevent deterioration of the distortion characteristics of the frequency conversion circuit 7, so that the first AGC has a slower operating point than the second AGC and the second AGC is present. An operation is performed in which the gain control amount is fixed and a total characteristic shown in the figure is obtained.

In order to generate each of the above voltages from the same gain control voltage, in the present embodiment, the gain control voltage lines from the demodulation circuits 14a and 14b are provided, and for the second AGC, the characteristic shown in FIG. On the other hand, in order to obtain the characteristic shown in FIG. 3C, a voltage control circuit composed of a k times DC amplification circuit and a voltage limiter is provided.

In order to obtain the characteristic shown in FIG. 12B, the voltage control circuits 15a and 15b are provided with a voltage limiter which is, for example, (k = 1) times, which is not lower than the set voltage.
5b is for obtaining the characteristics of (c) of FIG. 12 (k> 1).
The voltage limiter that obtains the maximum gain voltage at the doubled and the set voltage is arranged. According to the present embodiment, even if the gain control characteristic of the variable gain high frequency amplifier circuit does not match the gain control voltage characteristic obtained from the demodulation circuit, it suffices to change the setting of the voltage control circuit. Can be done easily.

FIG. 13 is a block diagram showing another embodiment of the present invention. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. The present embodiment is an example using band-pass filters 12d and 12e in which a surface acoustic wave (SAW) band-pass filter and a high-frequency amplifier circuit are arranged in the same package or integrally formed on the same substrate. The band pass filters 12d and 12e of this embodiment.
Compensates for the large insertion loss of the surface acoustic wave (SAW) bandpass filter and the different insertion loss due to the difference in bandwidth, and the gain of the built-in high-frequency amplifier circuit compensates for these insertion losses. .

Reference numerals 54a, 54b and 54c are high frequency amplifier circuits, 56a, 56b and 57a, 57b and 58 are electrodes of a surface acoustic wave (SAW) band pass filter, and 53 is a switching control circuit for switching control of the band pass filters 12d and 12e. is there. The bandpass filter 12e is an integrated surface acoustic wave (SAW) filter having two different bandwidths, and the electrodes 57a and 58 and the electrodes 57b and 58 form bandpass filters, respectively. High frequency amplifier circuit 54
The power supply of a, 54b, and 54c is controlled by the control signal of the channel selection control circuit 17 and the switching control circuit 53 to be turned on and off.

In the first and second operation modes, the power of the high frequency amplifier circuit 54a is turned on, and in the third operation mode, the power is turned on.
The power source 4b or 54c is selectively turned on. According to the present invention, since the insertion loss of the band pass filter can be made constant even if the bands are different, the band pass filter 12
Even if d and 12e are switched, the gain variation of the tuner circuit does not occur, the gain control amount of the AGC can be made constant, and the characteristic deterioration of the receiver can be prevented.

FIG. 14 is a circuit diagram showing still another embodiment of the present invention. In the figure, the same functional blocks or elements as in the previous figures are given the same numbers. In this embodiment, the first switching circuit 11 and the high frequency amplifier circuit 6,
8, local oscillation signal amplifier circuit 9, frequency conversion circuit 7, and third
This is an example in which the switching circuit 15 is integrated into a single chip.

60a-60c and 75a-75c and 77a
77a and 73c are buffer amplifier circuits, and 61a to 61c and 62a to 62c and 65a to 65f and 68a to 68c and 7.
6a to 76c are FETs, 63, 64 and 67a, 67b and 70 are current sources, and 74 is a buffer amplifier circuit 60a to 60c.
Power control circuit 78 for turning on / off the FETs 76a to 76c
OFF control circuit, 72 is a capacitor, 80, 81 and 82
Is a power supply control circuit for turning on / off the variable oscillation circuits 16a to 16c, and 66 and 69a to 69c and 71 are resistors. F
In the ETs 61a to 61c and the FETs 62a to 62c, the balanced outputs of the buffer amplifier circuits 60a to 60c are connected to the gates, the sources are connected to each other, and the current sources 63 and 6 are connected.
4 is grounded, each source is input to the high frequency amplifier circuit 6 in the next stage, and the drain forms a source follower connected to the power supply.

In the FETs 65a to 65f, the gate of the FET 65a and the gate of the FET 65d are connected to each other.
The gate of b and the gate of FET65c are connected,
Source of FET 65a and Source of FET 65b and FET 65e
The drain of is connected, and the source of FET65c and the FET
The source of 65d and the drain of FET 65f are connected,
The drain of the FET 65a and the drain of the FET 65c are connected to each other and to the intermediate frequency filter 10,
The drain of 65b and the drain of the FET 65d are connected to the intermediate frequency filter 10, the source of the FET 65e is grounded via the current source 67a, the source of the FET 65f is grounded via the current source 67b, and the source of the FET 65e and the FET 65f are grounded. The sources are connected by a resistor 66.

The gates of the FETs 65e and 65f are
The balanced outputs of the high-frequency amplifier circuit 6 are respectively input to the FE
FET65b and gate connection point of T65a and FET65d
The balanced output of the local oscillation signal amplification circuit 9 is input to the gate connection points of the FET 65c and the FET 65c, respectively, and the FET 65a and the FE are connected.
Drain connection point of T65c and FET65b and FET65
The drain connection points of d are respectively input to the high frequency amplifier circuit 8 to form a balanced mixer (DBM).

For the FETs 68a-68c,
The gate of 68a is connected to the variable oscillation circuit 16 via the resistor 69a.
connected to the output of a and the gate of FET 68b is a resistor 69
connected to the output of the variable oscillating circuit 16b via
The gate of T68c is connected to the variable oscillation circuit 1 via the resistor 69c.
6c, the sources of the FETs 68a to 68c are connected to each other, are grounded via the current source 70, and are input to the buffer amplifier circuit 73, and the local oscillation signal amplifier circuit 9 is connected.
Is also input to one side of.

The other input of the local oscillation amplifier circuit 9 is grounded via a capacitor 72, and both inputs are connected by a resistor 71. The outputs of the high-frequency amplifier circuit 8 are input to the buffer amplifier circuits 75a to 75c, and the outputs are input to the buffer amplifier circuits 77a to 77c, respectively, and the buffer amplifier circuits 75a to 75c and the buffer amplifier circuits 77a to 77c are input.
FET 76a is provided between the balanced transmission lines at the connection point of
~ 76c are connected to the drain and source, the gate is connected to the second switching circuit 78, the output of the buffer amplifier circuit 77a is connected to the input electrode 56a of the band pass filter 12a, the output of the buffer amplifier circuit 77b is band pass. The output of the buffer amplifier circuit 77c is connected to the input electrode 57a of the filter 12d and the output of the buffer amplifier circuit 77c is input to the input electrode 57 of the band pass filter 12d.
connected to b.

The output of the buffer amplifier circuit 73 is input to the tuning control circuit 17. In the first operation mode, the power supply of the buffer amplifier circuit 60a is turned on by the control signal of the power supply control circuit 74, and the output of the variable tuning filter 3a is F.
It is input to the high frequency amplifier circuit 6 via the ETs 61a and 62a, the control signal of the tuning control circuit 17 and the power supply control circuit 80.
Causes the variable oscillation circuit 16a to be turned on, the oscillation output is input to the local oscillation amplification circuit 9 via the FET 68a, and the frequency is converted by the balanced mixer composed of the FETs 65a to 65f, and the conversion output is amplified by the high frequency amplification circuit 8 and the buffer amplification. The tuning control circuit 17 and the control circuit 7 are connected via the circuit 75a.
8, the FET 76a is turned off (the source and the drain are in a high impedance state), and the other FETs 76b and 76c are turned on (the source and the drain are in a short-circuited state) and are input to the buffer amplifier circuit 77a.

In the second operation mode, the output of the variable tuning filter 3b is supplied to the high frequency amplifier circuit 6 via the FETs 61b and 62b while the buffer amplifier circuit 60b is powered on.
To the local oscillation amplification circuit 9 through the FET 68b while the power source of the variable oscillation circuit 16b is turned on by the power supply control circuit 81, and is amplified and output.
The frequency is converted by the frequency conversion circuit composed of T65a to 65f, and the converted output is input to the buffer amplification circuit 77a through the high frequency amplification circuit 8 and the buffer amplification circuit 75a while the FET 76a is in the OFF state.

In the third operation mode, the output of the variable tuning filter 3c is input to the high frequency amplifying circuit 6 via the FETs 61c and 62c while the power supply of the buffer amplifying circuit 60c is ON, amplified and output, and the output of the variable oscillating circuit 16c. When the power supply is turned on by the power supply control circuit 82, it is input to the local oscillation amplification circuit 9 via the FET 68c and amplified and output.
The frequency is converted by the frequency conversion circuit consisting of a to 65f,
The converted output is the high frequency amplifier circuit 8 and the buffer amplifier circuit 75b.
Alternatively, through 75c, FET76b or FET7
Buffer amplifier circuit 77b or 7 when 6c is OFF
7c is input.

According to this embodiment, since the main part of the tuner circuit is integrated into a one-chip IC, it is effective in downsizing, and the input / output of the main part is connected by balanced transmission, so that the inside and outside of the IC are connected. It is possible to reduce deterioration at the connection point with and to reduce unnecessary wave leakage from the inside of the IC to the outside. In the above-described embodiment of the present invention, F
By using ET as the secondary electron transfer FET (commonly called HEMT: high electron mobility transistor) having a gate length of 0.5 to 1.0 μm, the performance can be further improved with respect to noise figure and gain.

[0062]

According to the present invention, the high frequency circuit portion of the tuner circuit is provided with a GaA excellent in high frequency characteristics and third-order distortion characteristics.
By using the sFET and using the two-chip configuration of the RF amplification IC and the AGC mixer IC, a small tuner circuit having excellent third-order distortion characteristics and a small number of parts can be obtained. Furthermore, by constructing and connecting a tuner circuit with a balanced circuit that does not transmit in-phase components and even-order distortion components, the tuner circuit is resistant to secondary distortion and is also resistant to leakage of unwanted radiation such as local oscillation signals. Is obtained.

According to the present invention, the following effects can be expected. By using a GaAs FET that is excellent in high frequency characteristics and distortion characteristics as an IC for the frequency conversion circuit, excellent third-order distortion interference characteristics and VH
A system capable of processing a wideband reception signal from an F band terrestrial TV signal to a BS or CS signal and capable of selectively receiving a terrestrial TV signal, a CATV signal, a BS and a CS signal with a single tuner circuit. (Reception device) can be configured.

Further, by making each circuit constituting the receiving device a balanced type and coupling the circuits by balanced transmission, even-order distortion components generated in each circuit are canceled out from each other, and power supply wiring and ground wiring are also provided. The effect that a system (reception device) with small unwanted radiation leakage such as local oscillation can be configured because the interference is suppressed by the in-phase signal suppression to unwanted radiation such as local oscillation signal to the There is.

By arranging the voltage limiter circuit or the DC amplification and voltage limiter circuit between the variable gain circuit and the control circuit of the AGC circuit, the operation starting point of the AGC circuit and its sensitivity can be arbitrarily set at the same gain control voltage. There is an effect that you can choose. By providing a variable gain circuit between the frequency conversion circuit and the plurality of second intermediate frequency bandpass filters having different pass bands, and operating so as to cancel the difference in insertion loss of the filter according to switching of the filter,
It has the effect of preventing the deterioration of the noise figure of the receiver. Also,
By arranging the second intermediate frequency bandpass filter and the amplifying circuit in the same package or integrally forming them, the circuit can be downsized, and variations in the insertion loss of the filter due to different bands are eliminated, thereby reducing the noise of the receiver. It has the effect of preventing the deterioration of the index.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing still another embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of an input filter used in the present invention.

FIG. 6 is a circuit diagram showing another configuration example of the input filter used in the present invention.

FIG. 7 is a circuit diagram showing a configuration example of a variable tuning filter used in the present invention.

FIG. 8 is a circuit diagram showing another configuration example of the variable tuning filter used in the present invention.

FIG. 9 is a block diagram showing still another embodiment of the present invention.

FIG. 10 is a block diagram showing still another embodiment of the present invention.

FIG. 11 is a block diagram showing still another embodiment of the present invention.

FIG. 12 is a characteristic diagram for explaining the operation of the AGC in the embodiment of the present invention.

FIG. 13 is a block diagram showing another embodiment of the present invention.

FIG. 14 is a circuit diagram showing a specific example of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input filter, 2, 6, 8, 9, 13 ... High frequency amplification circuit, 3 ... Variable tuning filter, 10 ... Intermediate frequency filter, 12 ... Band pass filter, 16 ... Variable local oscillation circuit, 17 ... Tuning control circuit , 50 ... AGC switching circuit, 50
1 ... Input terminal, 502 ... RF amplification IC, 504 ... Mixer IC, 505 ... Demodulation IC

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaoru Iden, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (72) Masatoshi Ohsaw 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hiritsu Video Engineering Co., Ltd.

Claims (15)

[Claims] 1. A high frequency signal input terminal (501), a first IC (502) as an amplifier circuit for amplifying and outputting a high frequency signal input from the input terminal, and the first IC.
The first output signal is input to remove unnecessary signals and output
Filter (503), a first gain control circuit (507) for controlling the gain of the high frequency signal from the first filter, and a gain-controlled high frequency signal from the first gain control circuit at an intermediate frequency. A mixer circuit (508) for converting and outputting a signal, and an oscillating circuit (50) for supplying an oscillating signal for frequency conversion to the mixer circuit.
9) and a second gain control circuit (510) for controlling the gain of the intermediate frequency signal from the mixer circuit, and a second IC (504) at least internally, and a second IC in the second IC. An intermediate frequency filter (513) to which the intermediate frequency signal from the gain control circuit is input, an intermediate frequency amplification circuit (514) to which the intermediate frequency signal from the intermediate frequency filter is input and amplifies and outputs, and the intermediate frequency amplification A demodulation circuit (515) for receiving an amplified output from the circuit and demodulating and outputting the demodulated circuit; and a third IC (505) having at least a built-in circuit, the first IC (502) and the first filter (50
3), the second IC (504), the intermediate frequency filter (513), and the third IC (505) are coupled to each other by a balanced transmission path. . 2. A high-frequency signal input terminal (501), a first IC (502) as an amplifier circuit for amplifying and outputting a high-frequency signal input from the input terminal, and the first IC.
The first output signal is input to remove unnecessary signals and output
Filter (503), a second IC (504) which receives the high frequency signal from the first filter and converts the high frequency signal into an intermediate frequency signal and outputs the intermediate frequency signal, and the intermediate frequency signal from the second IC. Intermediate frequency filter (513) and a third IC (505) that receives the intermediate frequency signal from the intermediate frequency filter, demodulates it, and outputs it as a baseband signal
And the second IC (504) is connected to the first filter (5).
03), a first gain control circuit (507) for controlling the gain of the high frequency signal, and a mixer circuit for converting the gain-controlled high frequency signal from the first gain control circuit to an intermediate frequency signal and outputting it. 508), an oscillation circuit (509) for supplying an oscillation signal for frequency conversion to the mixer circuit, and a second gain control circuit (510) for controlling the gain of the intermediate frequency signal from the mixer circuit. A built-in third IC (505) includes an intermediate frequency amplifier circuit (514) that receives and amplifies and outputs an intermediate frequency signal from the intermediate frequency filter (513), and an amplifier from the intermediate frequency amplifier circuit. A demodulation circuit (515) that receives an output, demodulates it, and outputs it, is built-in, and the first IC (502) and the first filter (50) are included.
3), the second IC (504), the intermediate frequency filter (513), and the third IC (505) are coupled to each other by a balanced transmission path. . 3. A high frequency signal input terminal (501), a first IC (502) as an amplifier circuit for amplifying and outputting a high frequency signal input from the input terminal, and the first IC.
The first output signal is input to remove unnecessary signals and output
Filter (503), a second IC (504) which receives the high frequency signal from the first filter and converts the high frequency signal into an intermediate frequency signal and outputs the intermediate frequency signal, and the intermediate frequency signal from the second IC. Intermediate frequency filter (513) and a third IC (505) that receives the intermediate frequency signal from the intermediate frequency filter, demodulates it, and outputs it as a baseband signal
And the second IC (504) is connected to the first filter (5).
03), a first gain control circuit (507) for controlling the gain of the high frequency signal, and a mixer circuit for converting the gain-controlled high frequency signal from the first gain control circuit to an intermediate frequency signal and outputting it. 508), an oscillation circuit (509) for supplying an oscillation signal for frequency conversion to the mixer circuit, and a second gain control circuit (510) for controlling the gain of the intermediate frequency signal from the mixer circuit. A third gain control circuit (525) built therein, wherein the third IC (505) receives the intermediate frequency signal from the intermediate frequency filter (513), controls the gain of the intermediate frequency signal, and outputs the third gain control circuit (525); A demodulation circuit (515) for inputting and demodulating a gain-controlled output from the circuit, and outputting the demodulated circuit. The first IC (502) and the first filter (50).
3), the second IC (504), the intermediate frequency filter (513), and the third IC (505) are coupled to each other by a balanced transmission path. . 4. A receiving apparatus capable of selectively receiving a terrestrial television signal (including a CATV signal) in the VHF band and the UHF band and a satellite broadcast signal (including a BS signal and a CS signal) in the SHF band. , A first input terminal (100) to which a terrestrial television signal in the VHF band is input, and a first high frequency amplifier circuit (amplifies and outputs the television signal input via the first input terminal). 2a), a first variable tuning circuit (3a) for selecting a band by inputting a signal amplified by the first high frequency amplifier circuit, a first variable oscillation circuit (16a), and a UHF band terrestrial television. A second input terminal (101) to which a television signal is input; a second high frequency amplifier circuit (2b) that amplifies and outputs a television signal input via the second input terminal; 2 high frequency amplifier circuit A second variable tuning circuit (3b) for inputting a more amplified signal to select a band, a second variable oscillating circuit (16b), and a third for inputting a satellite broadcasting signal down-converted to 1 GHz band. Input terminal (102), a third high frequency amplifier circuit (2c) for amplifying and outputting the satellite broadcast signal input through the third input terminal, and the third high frequency amplifier circuit The third variable tuning circuit (3c) for selecting the band by inputting the received signal, and the third variable oscillation circuit (1
6c), and the first, second and third variable tuning circuits (3a, 3)
b, 3c), a first switching circuit (4) for selecting and outputting one, and a fourth high-frequency amplifier circuit (6) for inputting, amplifying and outputting the output from the first switching circuit. ), And the first, second and third oscillator circuits (16a, 16a).
b, 16c), a second switching circuit (15) for selecting and outputting one, and a fifth amplifying circuit (9) for inputting, amplifying and outputting the output from the second switching circuit. And GaAsFE for performing frequency conversion on the output signal from the fourth high frequency amplifier circuit (6) using the output signal from the fifth amplifier circuit (9) and outputting it as an intermediate frequency signal.
A frequency conversion circuit (7) composed of T, and a sixth amplification circuit (8) for amplifying and outputting the output from the frequency conversion circuit.
A first band pass filter (12a) that passes only the intermediate frequency signal of the terrestrial television signal; and a seventh amplifier circuit (13a) that amplifies and outputs the output of the first band pass filter, A first demodulation circuit (14a) for receiving the output of the seventh amplifier circuit and demodulating and outputting the same; and a first demodulation circuit for generating a first gain control voltage determined by a signal level input to the first demodulation circuit. 1 gain control circuit (14a)
A second band pass filter (12b) for passing only the intermediate frequency signal of the satellite broadcast signal; and an eighth amplifier circuit (13b) for amplifying and outputting the output of the second band pass filter.
A second demodulation circuit (14b) for receiving the output of the eighth amplifier circuit and demodulating and outputting the second output; and generating a second gain control voltage determined by the signal level input to the second demodulator circuit. A second gain control circuit (14b), and outputs of the sixth amplifier circuit (8) to the first bandpass filter (12a) and the second bandpass filter (12).
b) The third switching circuit (1
1) and in the first operation mode, the first variable tuning circuit (3a) is operated to cause the first switching circuit (4) to select its output, and the first variable tuning circuit (4a) is selected. Oscillation circuit (16
a) is operated to output the output from the second switching circuit (1
5) and controls the third switching circuit (11) to direct its output to the first demodulation circuit (14a) and, when in the second operation mode, the second operation mode. The variable tuning circuit (3b) is operated to cause the output to be selected by the first switching circuit (4), and the second variable oscillation circuit (16b) is operated to output the output to the second switching. A circuit (15) is selected and the third switching circuit (11) is controlled to output the output thereof to the first demodulation circuit (1).
4a), and when in the third operation mode, the third variable tuning circuit (3c) is operated to cause the first switching circuit (4) to select its output, and 3 variable oscillating circuit (16c) is operated to cause the second switching circuit (15) to select its output, and the third switching circuit (11) is controlled to output the output to the second demodulation. Channel selection control circuit (17) directed to the circuit (14b)
And a signal transmission path between the circuits is a balanced transmission path, and the fourth high frequency amplification circuit (6), the sixth amplification circuit (8) and the frequency conversion circuit (7) are An integrated IC receiver characterized by being integrated on at least the same semi-insulating semiconductor substrate. 5. The integrated receiver according to claim 4, wherein the amplification gains of the fourth high-frequency amplifier circuit (6) and the sixth amplifier circuit (8) are variably controlled according to the received signal level. An IC receiver comprising the means (50, 14a, 14b) for performing. 6. The integrated receiver according to claim 4, wherein when in the first operation mode and the second operation mode, the first gain control circuit (14a) generates a first signal. When the gain control voltage is used to perform variable gain control of the first high frequency amplifier circuit (2a), the second high frequency amplifier circuit (2b) and the seventh amplifier circuit (13a), and when in the third operation mode. , The second gain control circuit (14
The second high-frequency amplifier circuit (2c) and the eighth amplifier circuit (13b) are controlled by the second gain control voltage generated in (b).
Characterized by performing variable gain control of
Receiver. 7. The integrated receiver according to claim 4, further comprising means for variably controlling the gain of the sixth amplifier circuit (8), and when in the third operation mode, the sixth receiver circuit is provided. The gain of the amplifier circuit (8) is variably controlled, and the third high-frequency amplifier circuit (2c) and the eighth amplifier circuit are controlled by the second gain control voltage generated by the second gain control circuit (14b). (13b) The variable gain control is carried out, wherein the IC receiver is characterized. 8. The integrated receiver according to claim 4, wherein the first gain control circuit (14a) generates a first signal when in the first operation mode and the second operation mode. The variable gain control of the first high frequency amplification circuit (2a), the second high frequency amplification circuit (2b) and the seventh amplification circuit (13a) is performed by the gain control voltage, and when in the third operation mode, The second gain control circuit (14b)
The variable gain control of the fourth high frequency amplifier circuit (6) and the eighth amplifier circuit (13b) is performed by the second gain control voltage generated by the IC receiver. 9. A receiving device capable of selectively receiving a terrestrial television signal (including a CATV signal) in the VHF band and the UHF band and a satellite broadcast signal (including a BS signal and a CS signal) in the SHF band. , A first input terminal (100) to which a terrestrial television signal in the VHF band is input, and a first high frequency amplifier circuit (amplifies and outputs the television signal input via the first input terminal). 2a), a first variable tuning circuit (3a) for selecting a band by inputting a signal amplified by the first high frequency amplifier circuit, a first variable oscillation circuit (16a), and a UHF band terrestrial television. A second input terminal (101) to which a television signal is input; a second high frequency amplifier circuit (2b) that amplifies and outputs a television signal input via the second input terminal; 2 high frequency amplifier circuit A second variable tuning circuit (3b) for inputting a more amplified signal to select a band, a second variable oscillating circuit (16b), and a third for inputting a satellite broadcasting signal down-converted to 1 GHz band. Input terminal (102), a third high frequency amplifier circuit (2c) for amplifying and outputting the satellite broadcast signal input through the third input terminal, and the third high frequency amplifier circuit The third variable tuning circuit (3c) for selecting the band by inputting the received signal, and the third variable oscillation circuit (1
6c), and the first, second and third variable tuning circuits (3a, 3)
b, 3c), a first switching circuit (4) for selecting and outputting one, and a fourth high-frequency amplifier circuit (6) for inputting, amplifying and outputting the output from the first switching circuit. ), And the first, second and third oscillator circuits (16a, 16a).
b, 16c), a second switching circuit (15) for selecting and outputting one, and a fifth amplifying circuit (9) for inputting, amplifying and outputting the output from the second switching circuit. And GaAsFE for performing frequency conversion on the output signal from the fourth high frequency amplifier circuit (6) using the output signal from the fifth amplifier circuit (9) and outputting it as an intermediate frequency signal.
A frequency conversion circuit (7) composed of T, and a sixth amplification circuit (8) for amplifying and outputting the output from the frequency conversion circuit.
A first band pass filter (12a) that passes only the intermediate frequency signal of the terrestrial television signal; and a seventh amplifier circuit (13a) that amplifies and outputs the output of the first band pass filter, A first demodulation circuit (14a) for receiving the output of the seventh amplifier circuit and demodulating and outputting the same; and a first demodulation circuit for generating a first gain control voltage determined by a signal level input to the first demodulation circuit. 1 gain control circuit (14a)
A second band pass filter (12b) that passes only the intermediate frequency signal of the BS signal, a third band pass filter (12c) that passes only the intermediate frequency signal of the CS signal, and the second or third An amplifier circuit (13b) that amplifies and outputs the output of the band-pass filter of No. 1, and a second demodulation circuit (14) that demodulates and outputs the output of the eighth amplifier circuit.
b), a second gain control circuit (14b) for generating a second gain control voltage determined by the signal level input to the second demodulation circuit, and an output of the sixth amplification circuit (8). The first band-pass filter (12a) and the second band-pass filter (12)
b) and a third band-pass filter (12c), and a third switching circuit (11) for switching and supplying the first band-pass filter (12c) and the first variable tuning circuit (3a) when in the first operation mode. ) Is operated to cause the first switching circuit (4) to select its output, and the first variable oscillation circuit (16)
a) is operated to output the output from the second switching circuit (1
5) and controls the third switching circuit (11) to direct its output to the first demodulation circuit (14a) and, when in the second operation mode, the second operation mode. The variable tuning circuit (3b) is operated to cause the output to be selected by the first switching circuit (4), and the second variable oscillation circuit (16b) is operated to output the output to the second switching. A circuit (15) is selected and the third switching circuit (11) is controlled to output the output thereof to the first demodulation circuit (1).
4a), and when in the third operation mode, the third variable tuning circuit (3c) is operated to cause the first switching circuit (4) to select its output, and 3 variable oscillating circuit (16c) is operated to select the output by the second switching circuit (15), and the third switching circuit (11) is controlled to output the output in the second band. The second band pass filter (12b) is directed to the second demodulation circuit (14b) through a pass filter (12b) or a third band pass filter (12c).
A channel selection control circuit (17) that variably controls the gain of the sixth amplifier circuit (8) in an interlocked manner depending on whether it is through a third band pass filter (12c) or a third band pass filter (12c). The signal transmission path between the circuits is a balanced transmission path, and the fourth high frequency amplification circuit (6), the sixth amplification circuit (8) and the frequency conversion circuit (7) have at least the same semi-insulating property. An integrated IC receiver characterized by being integrated on a semiconductor substrate. 10. A receiving device capable of selectively receiving a terrestrial television signal (including a CATV signal) in the VHF band and the UHF band and a satellite broadcast signal (including a BS signal and a CS signal) in the SHF band. , A first input terminal (100) to which a terrestrial television signal in the VHF band is input, and a first high frequency amplifier circuit (amplifies and outputs the television signal input via the first input terminal). 2a), a first variable tuning circuit (3a) for selecting a band by inputting a signal amplified by the first high frequency amplifier circuit, a first variable oscillation circuit (16a), and a UHF band terrestrial television. A second input terminal (101) to which a television signal is input; a second high frequency amplifier circuit (2b) that amplifies and outputs a television signal input via the second input terminal; 2 high frequency amplification times A second variable tuning circuit (3b) for inputting a signal amplified by the signal to select a band, a second variable oscillating circuit (16b), and a third broadcasting signal for down-converting to 1 GHz band. Input terminal (102), a third high frequency amplifier circuit (2c) for amplifying and outputting the satellite broadcast signal input through the third input terminal, and the third high frequency amplifier circuit The third variable tuning circuit (3c) for selecting the band by inputting the received signal, and the third variable oscillation circuit (1
6c), and the first, second and third variable tuning circuits (3a, 3)
b, 3c), a first switching circuit (4) for selecting and outputting one, and a fourth high-frequency amplifier circuit (6) for inputting, amplifying and outputting the output from the first switching circuit. ), And the first, second and third oscillator circuits (16a, 16a).
b, 16c), a second switching circuit (15) for selecting and outputting one, and a fifth amplifying circuit (9) for inputting, amplifying and outputting the output from the second switching circuit. And GaAsFE for performing frequency conversion on the output signal from the fourth high frequency amplifier circuit (6) using the output signal from the fifth amplifier circuit (9) and outputting it as an intermediate frequency signal.
A frequency conversion circuit (7) composed of T, and a sixth amplification circuit (8) for amplifying and outputting the output from the frequency conversion circuit.
A first band pass filter (12a) that passes only the intermediate frequency signal of the terrestrial television signal; and a seventh amplifier circuit (13a) that amplifies and outputs the output of the first band pass filter, A first demodulation circuit (14a) for receiving the output of the seventh amplifier circuit and demodulating and outputting the same; and a first demodulation circuit for generating a first gain control voltage determined by a signal level input to the first demodulation circuit. 1 gain control circuit (14a)
A second band pass filter (12b) that passes only the intermediate frequency signal of the BS signal, a third band pass filter (12c) that passes only the intermediate frequency signal of the CS signal, and the second or third An amplifier circuit (13b) that amplifies and outputs the output of the band-pass filter of No. 1, and a second demodulation circuit (14) that demodulates and outputs the output of the eighth amplifier circuit.
b), a second gain control circuit (14b) for generating a second gain control voltage determined by the signal level input to the second demodulation circuit, and an output of the sixth amplification circuit (8). The first band-pass filter (12a) and the second band-pass filter (12)
b) and a third band-pass filter (12c), and a third switching circuit (11) for switching and supplying the first band-pass filter (12c) and the first variable tuning circuit (3a) when in the first operation mode. ) Is operated to cause the first switching circuit (4) to select its output, and the first variable oscillation circuit (16)
a) is operated to output the output from the second switching circuit (1
5) and controls the third switching circuit (11) to direct its output to the first demodulation circuit (14a) and, when in the second operation mode, the second operation mode. The variable tuning circuit (3b) is operated to cause the output to be selected by the first switching circuit (4), and the second variable oscillation circuit (16b) is operated to output the output to the second switching. A circuit (15) is selected and the third switching circuit (11) is controlled to output the output thereof to the first demodulation circuit (1).
4a), and when in the third operation mode, the third variable tuning circuit (3c) is operated to cause the first switching circuit (4) to select its output, and 3 variable oscillating circuit (16c) is operated to select the output by the second switching circuit (15), and the third switching circuit (11) is controlled to output the output in the second band. The second band pass filter (12b) is directed to the second demodulation circuit (14b) through a pass filter (12b) or a third band pass filter (12c).
A channel selection control circuit (17) that variably controls the gain of the sixth amplification circuit (8) in an interlocked manner depending on whether the first bandpass filter (12c) or the third bandpass filter (12c). The first gain control voltage from the gain control circuit (14a) is input and the seventh amplification circuit (1
First voltage control circuit (51a) for controlling the gain of 3a)
And a first gain control voltage from the first gain control circuit (14a) is input, and the respective gains of the first high frequency amplification circuit (2a) and the second high frequency amplification circuit (2b) are correspondingly changed. A second voltage control circuit (52a) for controlling and a second gain control voltage from the second gain control circuit (14b) are input and the eighth amplification circuit (1
Third voltage control circuit (51b) for controlling the gain of 3b)
And a fourth voltage control circuit (5) which receives the second gain control voltage from the second gain control circuit (14b) and controls the gain of the fourth high frequency amplifier circuit (6) in accordance with the second gain control voltage.
2b), and the signal transmission line between the circuits is a balanced transmission line, and further the fourth high frequency amplification circuit (6), the sixth amplification circuit (8) and the frequency conversion circuit (7). And IC are integrated on at least the same semi-insulating semiconductor substrate. 11. The integrated receiver according to claim 10, wherein the first voltage control circuit (51a) and the third voltage control circuit (51b) have a predetermined constant gain control voltage to be input. Until the limit is reached, a constant control voltage is output regardless of the input gain control voltage, and when the limit is exceeded, the control voltage is output in proportion to the input gain control voltage. The second voltage control circuit (52a) and the fourth voltage control circuit (52b) output a control voltage proportional to the gain control voltage until the input gain control voltage reaches a predetermined fixed limit, An IC receiver, which has a characteristic of outputting a constant control voltage regardless of an input gain control voltage when the constant limit is exceeded. 12. The I according to claim 9, 10, or 11.
In the C receiver, the second bandpass filter (12b) and the third bandpass filter (12c) are arranged in the same package.
Receiver. 13. The I according to claim 9, 10, or 11.
In the C-type receiving apparatus, the first to third band-pass filters (12a, 12b, 12c) each include an amplifier circuit for compensating for each insertion loss. apparatus. 14. The integrated receiver according to claim 10, wherein a first input filter (1a) is provided between the first input terminal (100) and the first high-frequency amplifier circuit (2a).
And a second input filter (1) between the second input terminal (101) and the second high frequency amplifier circuit (2b).
b), a third input filter (1c) is connected between the third input terminal (102) and the third high-frequency amplifier circuit (2c), and each of the first to third inputs is connected. Among the filters, at least the first and second input filters are variable tuning filters. 15. The integrated circuit receiver according to any one of claims 4 to 13, wherein the semi-insulating semiconductor substrate is made of GaAs, and each of the FETs constitutes each circuit.
Is an HEMT (high electron mobility transistor) having a gate length of 0.5 to 1.0 μm.