JPH0669470A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0669470A JPH0669470A JP21926592A JP21926592A JPH0669470A JP H0669470 A JPH0669470 A JP H0669470A JP 21926592 A JP21926592 A JP 21926592A JP 21926592 A JP21926592 A JP 21926592A JP H0669470 A JPH0669470 A JP H0669470A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- resistance layer
- substrate
- array
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000003491 array Methods 0.000 claims abstract 3
- 238000000034 method Methods 0.000 abstract description 10
- 230000010354 integration Effects 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置に関し、特
にマスタースライス方式のＬＳＩのマスター構造に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a master structure of a master slice type LSI.
【０００２】[0002]
【従来の技術】図４に従来のマスタースライス方式のＬ
ＳＩのマスター基板（マスター構造）を示す。基板上に
Ｐ型拡散領域１、Ｎ型拡散領域２がそれぞれアレイ状に
配列されて形成されている。また、ポリシリコン材料等
からなるゲート電極３がＰ型拡散領域１、Ｎ型拡散領域
２と交互にアレイ状に形成されている。2. Description of the Related Art FIG. 4 shows a conventional master slice type L
1 shows a master substrate (master structure) of SI. A P-type diffusion region 1 and an N-type diffusion region 2 are arranged and formed in an array on a substrate. Further, gate electrodes 3 made of a polysilicon material or the like are alternately formed with P-type diffusion regions 1 and N-type diffusion regions 2 in an array.
【０００３】このように構成されたマスター基板に対
し、スライス工程においてＡｌ配線を施して回路を構成
する。In the slicing process, Al wiring is applied to the master substrate thus constructed to form a circuit.
【０００４】[0004]
【発明が解決しようとする課題】従来のマスター基板は
以上のように構成されていたため、抵抗素子が必要な場
合にはＰ型拡散領域１やＮ型拡散領域２における拡散抵
抗を用いていた。しかし拡散抵抗を用いると、トランジ
スタに必要とされる拡散領域とは別に、余分にこれらの
拡散領域が必要となり、結果として回路の集積度が低下
するという問題があった。Since the conventional master substrate is constructed as described above, the diffusion resistance in the P-type diffusion region 1 and the N-type diffusion region 2 is used when the resistance element is required. However, if the diffusion resistance is used, there is a problem in that these diffusion regions are additionally required in addition to the diffusion region required for the transistor, and as a result, the degree of integration of the circuit is reduced.
【０００５】これは更にセルサイズの増大を許し、次段
のセルとの配線が長くなってクロックラインの付加容量
が増大してしまう等の問題点をも招来してしまう。This further allows the cell size to be increased, leading to the problem that the wiring to the cell in the next stage becomes long and the additional capacitance of the clock line increases.
【０００６】この発明は上記のような問題点を解消する
ためになされたもので、マスタースライス方式ＬＳＩに
おいて、抵抗素子が必要な場合でも回路の集積度を低下
させない半導体装置を得ることを目的とする。The present invention has been made in order to solve the above problems, and an object thereof is to obtain a semiconductor device in a master slice type LSI which does not reduce the degree of circuit integration even when a resistance element is required. To do.
【０００７】[0007]
【課題を解決するための手段】この発明にかかる半導体
装置は、基板と、基板上に形成され、それぞれが第１及
び第２の導電型を有する第１及び第２の半導体領域のそ
れぞれの配列と、第１の半導体領域の配列と同列に前記
第１の半導体領域と交互に形成された第１のゲート電極
の配列と、第２の半導体領域の配列と同列に前記第２の
半導体領域と交互に形成された第２のゲート電極の配列
と、第１及び第２の半導体領域の配列とも第１及び第２
のゲート電極の配列とも隔離して前記基板上に形成され
た抵抗層と、を備える。According to another aspect of the present invention, there is provided a semiconductor device, in which a substrate and an array of first and second semiconductor regions formed on the substrate and having first and second conductivity types, respectively, are arranged. An array of first gate electrodes alternately formed with the first semiconductor regions in the same column as the array of the first semiconductor regions, and a second semiconductor region in the same column as the array of the second semiconductor regions. The arrangement of the second gate electrodes and the arrangement of the first and second semiconductor regions which are alternately formed are the first and the second.
And a resistance layer formed on the substrate separately from the arrangement of the gate electrodes.
【０００８】望ましくは抵抗層は、第１の半導体領域の
配列と第２の半導体領域の配列との間の領域に形成され
る。Preferably, the resistance layer is formed in a region between the first semiconductor region array and the second semiconductor region array.
【０００９】また望ましくは、抵抗層は複数設けられ
る。Also, preferably, a plurality of resistance layers are provided.
【００１０】[0010]
【作用】この発明における抵抗層は、スライス工程にお
ける配線によって抵抗素子として用いられる。The resistance layer in the present invention is used as a resistance element by wiring in the slicing process.
【００１１】抵抗層を第１の半導体領域の配列と第２の
半導体領域の配列との間の領域に形成することにより、
集積度の低下は招来しない。By forming the resistive layer in a region between the first semiconductor region array and the second semiconductor region array,
There is no reduction in the degree of integration.
【００１２】抵抗層を複数設けることによってこれらを
直列に、あるいは並列に接続して所望の抵抗値の抵抗素
子を得ることができる。By providing a plurality of resistance layers, these can be connected in series or in parallel to obtain a resistance element having a desired resistance value.
【００１３】[0013]
【実施例】実施例１．以下、この発明の一実施例であ
る、マスター基板について図１をもって説明する。図４
に示した従来の場合と同様に、基板上にＰ型拡散領域
１、Ｎ型拡散領域２がそれぞれアレイ状に配列されて形
成されている。また、ポリシリコン材料等からなるゲー
ト電極３がＰ型拡散領域１、Ｎ型拡散領域２と交互にア
レイ状に形成されている。EXAMPLES Example 1. A master substrate, which is an embodiment of the present invention, will be described below with reference to FIG. Figure 4
Similar to the conventional case shown in (1), the P-type diffusion regions 1 and the N-type diffusion regions 2 are formed in an array on the substrate. Further, gate electrodes 3 made of a polysilicon material or the like are alternately formed with P-type diffusion regions 1 and N-type diffusion regions 2 in an array.
【００１４】Ｐ型拡散領域１の配列とＮ型拡散領域２の
配列との間の領域に複数の抵抗層４が形成されている。
ここではゲート電極４つに１つの割合で設けられてい
る。抵抗層４はマスター工程で形成されるが、ゲート電
極３と別途に形成することはもちろん、これと同じ材
料、同じ工程で形成することもできる。A plurality of resistance layers 4 are formed in a region between the arrangement of the P type diffusion regions 1 and the arrangement of the N type diffusion regions 2.
Here, one gate electrode is provided for every four gate electrodes. Although the resistance layer 4 is formed in the master process, it may be formed separately from the gate electrode 3 or may be formed by the same material and the same process as the gate electrode 3.
【００１５】図２に、抵抗素子を必要とする回路として
レシオラッチ回路を示す。この回路は、帰還抵抗として
抵抗素子５が必要となる。このレシオラッチ回路は、図
１に示されたマスター基板にスライス工程を施すことに
よって実現される。FIG. 2 shows a ratio latch circuit as a circuit requiring a resistance element. This circuit requires the resistance element 5 as a feedback resistance. This ratio latch circuit is realized by subjecting the master substrate shown in FIG. 1 to a slicing process.
【００１６】図３に、スライス工程によってＰ型拡散領
域１、Ｎ型拡散領域２、ゲート電極３、抵抗層４の間に
配線を施して図２に示されたレシオラッチ回路を実現す
る様子を示す。図中、黒い四角形はバイアホール等にお
ける接続を示す。配線６，７はそれぞれＶＤＤ電位、Ｇ
ＮＤ電位を供給する。具体的には、まずインバータ等の
マクロセルを配置したあと、全体の回路規模ができるだ
け小さくなるように抵抗層４についてのスライス配線が
施される。FIG. 3 shows how the ratio latch circuit shown in FIG. 2 is realized by providing wiring between the P-type diffusion region 1, the N-type diffusion region 2, the gate electrode 3 and the resistance layer 4 by the slicing process. . In the figure, black squares indicate connections in via holes and the like. Wiring 6 and 7 are VDD potential and G, respectively
Supply ND potential. Specifically, first, after arranging macro cells such as inverters, slice wiring for the resistance layer 4 is performed so that the overall circuit scale becomes as small as possible.
【００１７】上記のレシオラッチ回路に限られず、フリ
ップフロップ、スキャンレジスタ等の抵抗素子を必要と
する回路においてももちろんこの発明は適用できる。The present invention is not limited to the above ratio latch circuit, but can be applied to a circuit requiring a resistance element such as a flip-flop and a scan register.
【００１８】実施例２．なお、上記実施例では抵抗層４
はゲート電極４つに１つの割合で設けられているが、他
の割合であってもよい。また、長さの異なる抵抗層をマ
スター基板上に形成して、値の異なる抵抗素子を得るこ
ともできる。更には、複数の抵抗層を直列あるいは並列
に接続して、所望の抵抗値の抵抗素子を得ることもでき
る。Example 2. In addition, in the above embodiment, the resistance layer 4
Is provided for every four gate electrodes, but other ratios may be used. Further, it is also possible to form resistance elements having different values by forming resistance layers having different lengths on the master substrate. Furthermore, a plurality of resistance layers can be connected in series or in parallel to obtain a resistance element having a desired resistance value.
【００１９】[0019]
【発明の効果】以上に説明したように、この発明によれ
ばマスタースライス方式ＬＳＩのマスター基板上に抵抗
層を設けたので、ラッチ、フリップフロップ、スキャン
レジスタ等の抵抗素子を必要とする回路を構成する場合
においても拡散領域の拡散抵抗を用いる必要がなく、集
積度の高い半導体装置が得られる。As described above, according to the present invention, since the resistance layer is provided on the master substrate of the master slice type LSI, a circuit that requires a resistance element such as a latch, a flip-flop, or a scan register is provided. Even in the case of the configuration, it is not necessary to use the diffusion resistance of the diffusion region, and a semiconductor device with high integration can be obtained.
【００２０】更に、セルの増大が回避できるので、セル
間の配線が短くなり、配線容量を低減することもでき
る。Further, since it is possible to avoid the increase of cells, the wiring between cells can be shortened and the wiring capacity can be reduced.
【図１】この発明の一実施例にかかるマスター基板の構
造を示す平面図である。FIG. 1 is a plan view showing a structure of a master substrate according to an embodiment of the present invention.
【図２】レシオラッチ回路の回路図である。FIG. 2 is a circuit diagram of a ratio latch circuit.
【図３】マスター基板にスライス工程を施して実現され
たレシオラッチ回路の構成を示す平面図である。FIG. 3 is a plan view showing a configuration of a ratio latch circuit realized by subjecting a master substrate to a slicing process.
【図４】従来のマスター基板の構造を示す平面図であ
る。FIG. 4 is a plan view showing a structure of a conventional master substrate.
１ Ｐ型拡散領域 ２ Ｎ型拡散領域 ３ ゲート電極 ４ 抵抗層 1 P-type diffusion region 2 N-type diffusion region 3 Gate electrode 4 Resistance layer
Claims (3)
型を有する第１及び第２の半導体領域のそれぞれの配列
と、 前記第１の半導体領域の配列と同列に前記第１の半導体
領域と交互に形成された第１のゲート電極の配列と、 前記第２の半導体領域の配列と同列に前記第２の半導体
領域と交互に形成された第２のゲート電極の配列と、 前記第１及び第２の半導体領域の配列とも前記第１及び
第２のゲート電極の配列とも隔離して前記基板上に形成
された抵抗層と、 を備える半導体装置。1. A substrate, a respective array of first and second semiconductor regions formed on the substrate, each having first and second conductivity types, and an array of the first semiconductor regions. Arrangement of first gate electrodes formed alternately with the first semiconductor regions in the same row, and second gates formed alternately with the second semiconductor areas in the same row as the arrangement of the second semiconductor regions A semiconductor device comprising: an array of electrodes; and a resistance layer formed on the substrate so as to be isolated from the arrays of the first and second semiconductor regions and the arrays of the first and second gate electrodes.
配列と前記第２の半導体領域の配列との間の領域に形成
された請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the resistance layer is formed in a region between the arrangement of the first semiconductor regions and the arrangement of the second semiconductor regions.
記載の半導体装置。3. The resistance layer is provided in plurality.
The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21926592A JPH0669470A (en) | 1992-08-18 | 1992-08-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21926592A JPH0669470A (en) | 1992-08-18 | 1992-08-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0669470A true JPH0669470A (en) | 1994-03-11 |
Family
ID=16732823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21926592A Pending JPH0669470A (en) | 1992-08-18 | 1992-08-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669470A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012124510A (en) * | 2007-08-02 | 2012-06-28 | Tela Innovations Inc | Integrated circuit device |
-
1992
- 1992-08-18 JP JP21926592A patent/JPH0669470A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012124510A (en) * | 2007-08-02 | 2012-06-28 | Tela Innovations Inc | Integrated circuit device |
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