JPH0668914B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention relates to a memory device, and more particularly to a dual port constant speed recall semiconductor memory device used for graphic storage applications.

[Prior Art] With the advent of low-cost semiconductor storage devices, modern computer and microcomputer organizations are now able to use bit-map video displays to output data from their organizations. I'm running. As is well known, the bit map display requires a storage device capable of storing at least one binary number (bit) for each pixel of the display device. Additional bits stored for each pixel can be used by the computer system, such as multicolored images,
And the ability to provide composite images, such as background and foreground images with textual information overlaid on background graphics. Also, the use of bit map storage allows the stored image to be easily generated and modulated through data processing operations.

Present day display devices are often raster-scan, in which the electron gun performs horizontal line tracing across the display screen to produce a display pattern. In order for the raster-scanned image to be displayed continuously on the video screen, it must be refreshed at periodic intervals. For a cathode ray tube image display, the typical refresh rate is 1 / 60th of a second because the refresh action performed at this rate is not perceptible to the human user of the tissue. However, as the number of pixels displayed on the screen increases to improve the resolution of the displayed image, more and more bits must be retrieved from the bit map storage during the refresh interval. If the bit map storage has only a single input and output port, the percentage of that time that the data processor can call from the bit map storage over time as long as the refresh interval is constant. Decreases with the pixel size of the display. In addition, more bits must be output during a certain time period, so the speed of the storage device must be increased.

A multi-port constant-speed call storage device has been developed, and by this device, high-speed output of data to a video display device and improvement of callability of stored contents to a data processing device can be achieved. In order to achieve this, the multi-port storage device has a first port for constant speed call and update of storage by the data processing device of the computer system and independently of the first port and asynchronously with it. It has a second port for serially outputting the stored content to the video display device, thereby allowing the stored content to be recalled during the output of data to the video display terminal. An example of multiple port constant velocity storage is
Described in US Pat. No. 4,562,435 (issued December 31, 1987), US Pat. No. 4,639,890 (issued January 27, 1987), and US Pat. No. 4,636,986 (issued January 13, 1987) , All of these patents are assigned to Texas Instruments Limited Liability Company.

The multi-port constant velocity call store described in U.S. Pat. No. 4,636,986 has four input / output terminals and four serial call input / output terminals, so that a single storage device is like four storage arrays. appear. This makes it possible to read and write four data at a time using a single address value by means of a single constant speed call and also for the purpose of data communication with a video display device a quad serial. Enables output.
For example, in a monochromatic display device, therefore, an external parallel serial register can receive four serial output bits and move them to the video display device at a display refresh rate. The buffer provided by this external parallel serial register allows the storage register to move at a speed of 1 / n of the video display device (n being the number of serial outputs received by the external parallel serial register), and the semiconductor Further reduce the demand for storage speed.

In addition, the use of quadruples provides enhanced image display capabilities. For example, quadruple organization is useful for multicolor display because the four bits associated with each address can be associated with one normal pixel ("pixel") of the display. Such a configuration stores a binary code representation of up to 16 colors for each corresponding pixel of the video display device. These four
Another use of one bit is to use one of the bits to represent the text, the remaining three bits to represent the eight bit color code for the graphic background, and the quad store is:
Therefore, it facilitates the overlay of text messages on graphic images.

Referring to FIG. 10, a dual buffer display storage device is shown. In such a memory device, while the marched display information is stored in one frame buffer memory device, another buffer memory device supplies its contents to the display device.
The central processing unit 250 outputs the data output to the demultiplexing unit 252.
Connected to the latter, the latter being shown schematically to supply data to groups of storage surfaces 254A and 254B, each of these groups having bit map data for N bit storage surfaces.
The storage plane groups 254A and 254B use the data output from the multiplex converter 256.
, Which in turn supplies output to the display device 258. The control lines SEL and SEL _- signals are logical complements of each other and control the selection of demultiplexer 252 and demultiplexer 256, respectively, thereby causing storage plane group 254A to enter through demultiplexer 252. Memory surface group 25 for the selected time
4B is selected for output through multiplexer 256 (or vice versa). During operation, one of the storage surface groups 254 provides display output to the display device 258 and during this time the central processing unit 250 provides input to the other storage surface group 254. After the display has been completed, the line SEL and SEL _- is Kawari placed to the opposite data state, so that the upper storage plane group inverse relationship
254 receives data from central processing unit 250 and provides the data to display device 258.

In such applications, it is often advantageous to clear or write specific data to a large number of storage locations within one of the storage surfaces. In configurations where one of the storage surfaces carries, for example, text information, it is advantageous to clear the text message without disturbing the other storage surfaces associated with the same pixel. If a constant speed call to each of the storage locations is required to write the desired "clear" data to each of the called locations, such an operation would consume a very large number of storage cycles during which Other actions to display storage are locked out.

In the double-buffered storage device of FIG. 10, clearing the contents of some of the selected surfaces in the storage surface group 254 prior to supplying the updated data to the storage surface group 254 to which the data is to be supplied. Is normally running. By this,
Since the background color information remains undisturbed in the unselected planes of this storage surface group, the central storage device 250 can only supply the storage surface group 254 with the data necessary to draw the display image. However, if a constant velocity recall of each note in the storage plane is required for the clearing operation, the clearing and drawing operations in one of the storage surface groups 254 selected to receive the data will be performed by the other storage surface group. The time required for clearing is subtracted from the time available for drawing because it is fixed by the time it takes to supply to the data display 258.

[Problems to be Solved by the Invention] Accordingly, an object of the present invention is to provide a dual mode having a selection mode in which a large number of storage cells are forced to be placed in a preselected data state in a single storage cycle. To provide a port storage device.

Another object of the present invention is to provide a dual port storage device having such an aspect that a large number of storage cells are organized in an overall column of storage cells.

It is a further object of the invention that the storage device is organized to connect to a plurality of parallel inputs and a selected one of these inputs.
It is an object of the present invention to provide a dual port memory device in which such a row write operation to a memory cell associated with a memory cell is prohibited during a write cycle.

Yet another object of the present invention is to have such an aspect, and further to have a data register containing a data state that is forced into a storage cell in a selected row during a given write cycle. To provide a dual port storage device.

Yet another object of the invention is to provide such capability with a single capacitor and transistor associated with multiple columns in a storage cell, thereby minimizing the silicon area required to incorporate the invention. Is to turn into.

Other objects and advantages of the present invention will be apparent to those skilled in the art from the detailed description of the embodiments of the present invention given below with reference to the accompanying drawings.

[Means for Solving the Problems] The present invention is incorporated in a constant-speed call storage device having a storage array organized in rows and columns, and a plurality of storage cells in a selected row are simultaneously set to the same data state. It has a special operation mode to be written. A capacitor is provided, the capacitor being of sufficient size to store sufficient charge to negate the readout of the readout amplifier in the storage device. The decoded data input signal selects whether this capacitor should be connected to the bit line to which the selected storage cell is connected or to the dummy line to which the dummy cell is connected. As a result of this capacitor being precharged to ground potential, when connected to the dummy cell's bit line, the bit line will be read by the read amplifier regardless of the data stored in the selected storage cell. The selected cell is discharged to a potential that reads "1". Conversely, when this capacitor is connected to the bit line of the selected storage cell, that bit line will be read by the read amplifier regardless of the stored contents of the selected storage cell.
The memory cell is discharged to a potential at which "0" is read. During the restore operation of the read amplifier, the selected storage cell is written with the data state read by the read amplifier, which in effect "writes" the data provided to it by this capacitor. . A constant speed call store is also a multiple I / O store with write mask capability and is therefore in a select array (ie, associated with a selected one of the multiple I / O stores). The memory cells that are to be stored are not disturbed during a row write operation performed on memory cells in other arrays.
An input data register may be provided to store the top write data, or a data input terminal of the storage device may be required to selectively connect an additional capacitor to the data bit line or the data complement bit line. A data signal can also be provided.

EXAMPLE Referring to FIG. 1, there is shown a functional block diagram of a dual port storage device 1 constructed in accordance with the present invention and including improved write mask features. Similar to the storage device of the aforementioned U.S. Pat. No. 4,636,986, which is incorporated herein by reference, this dual port storage device is provided on
In addition to receiving an address signal through A8, line the clock signal RAS _-, CAS _- through and SCLK, the line write enable signal WE _- receive, and a serial output enable signal on line SOE _-, a transfer enable signal line TR . Note that due to the built-in write mask feature, only single column address strobe line CAS signals are received and utilized by dual port store 1. The dual-port storage device 1 has eight constant-speed call input / output data D0 to D7 instead of four as in the input / output terminals of the storage device of US Pat. No. 4,636,986. The invention is, of course, applicable to either of these configurations, or to other configurations of dual port storage. Therefore, the dual port storage device 1 has 8
Two sequences 2, each of which, in this example,
It has a storage capacity of 128K bits organized into 512 and 256 lines. Therefore, the dual port storage device 1 of FIG. 1 includes a storage capacity of 1M bits. Associated with each array 2 is a read amplifier bank 4, which contains 256 read amplifiers as is well known in the read art to restore and write data to and from the dynamic storage cells of array 2. .

Looking at the serial side of the dual port storage device 1, US Pat.
A transfer gate 6 is connected to each of the bit lines in array 2, as in the dual port storage device of 636,986,
Transfer data from array 2 to data register 8 or vice versa. In this example, data register 8
Is a 256-bit register, thus 256 bits of data are transferred by each bank of transfer gates 6. That is, in each transfer cycle, 20
48 bits are transferred. Series logic circuit 14, a serial clock signal on line SCLK, the serial output enable signal on line SOE, and the transfer signal line TR _- receives signals from the through, and a constant speed access memory (RAM) logic circuit 16, This allows the transfer of data at the proper time, as in the storage device of US Pat. No. 4,636,986.

The toggle counter / detector 22 includes a counter and detector that selects the bit in each of the data registers 8 where serial I / O is about to be initiated. Accordingly, toggle counter / detector 22 receives the latch column address signal from RAM logic circuit 16 via line 21 and is described in US Pat. No. 4,636,98.
Select the serial position where the serial input or output should be initiated, as is the case with the No. 6 storage device. The serial logic circuit 14 is
It controls the toggle counter / detector 22 to load the latch column address value during the transfer cycle and the line as described above.
A signal is sent to the toggle counter / detector 22 during each cycle of the clock signal via SCLK, which causes the count value in the toggle counter / detector 22 to be incremented during each series cycle. The toggle counter / detector 22 provides the decoded value stored in that counter to each of the pointers 10, one such pointer being associated with each of the data registers 8. . The contents of the data register 8 are not allowed to have their internal shifts during each cycle as in the memory device in U.S. Pat. Increments with each cycle of the clock signal via line SCLK which increments the contents of the counter in toggle counter / detector 22. The bit contents in each of the data registers 8 pointed to by the associated one of the pointers 10 are sent to the serial I / O buffers 12 for I / O purposes, and these serial I / O buffers 12 are stored. Each of the devices is associated with each of the eight arrays 2 and data registers 8. The serial I / O buffer 12 communicates data between the associated serial I / O terminals SD0 through SD7 and its associated register 8 bit pointed to by the interface 10. The signal through line SOE is
As described above, the serial logic circuit 14 is instructed whether the serial operation is write or read, and the serial logic circuit 14 controls the serial input / output buffer memory device 12 accordingly. Serial I / O is therefore functionally similar to that in the case of the storage device of U.S. Pat.No. 4,636,986, except that the serial register function is an unshifted data Bits achieved by register 8 and within this register are selected through an incrementing manner.

At the constant speed caller, the RAM logic circuit 16 performs address latching and decoding, as would be done in the memory of U.S. Pat. No. 4,636,986, and therefore the line RA
S _- the row address strobe signal and the line CAS _- receipt of the column address strobe signals, respectively, and receive signals from the address lines A0 A8. Address terminals A0 to A8
The row address value appearing above is latched by the column address strobe signal on line RAS _-- and sent to X-decoder 18 via line 19 so that X-decoder 18 is latched on line 19. A row within each of array 2 may be selected in response to a row address value. Similarly, address lines A0 through A7
The column address value that appears above (the column address signal that appears on terminal A8 is not necessary to select one of the 256 columns) is
RAM in response to the column address strobe signal of _- line CAS
It is latched by the logic circuit 16, and the latch column address value is
Y decoder 20 from RAM logic circuit 16 via one of lines 21
, Each of the eight arrays has a Y-decoder associated with it.
Have one of twenty. Therefore, each of the Y decoders 20
The desired bit line in its associated array 2 and corresponding to the latch column address value can be connected to its associated I / O buffer 24.

In addition to the functions described in U.S. Pat. No. 4,636,986, dual port storage 1 has additional control functions over the constant velocity call data input function, such additional control being a special function logic. It is carried out by the circuit 30. Each of the eight input / output buffer memory devices 24 is connected to the data terminals D0 to D7 by the multiplexer 26. For constant speed call purposes, the output of the I / O buffer store 24 is received by the output drive circuit 31 and thereby connected to the data terminals D0 through D7. Output driver circuit 31 takes the configuration of any one of a number of known construction, and line TRG under the control of the RAM logic circuit 16 _- is made possible by connexion used for the external signal via.
For writing purposes, of course, the output drive circuit 31 is RAM
It is prohibited by the logic circuit 16 to prevent data collision.

Line WTCL from special function logic 30 during write cycle
R controls the multiplexer 26, either the data value appearing on the data terminals D0 to D7 or the contents of the color register 50 in the special function logic circuit 30 depending on the function selected by the user. Is selected and sent to the input / output buffer storage device 24 via the line 27. Special function logic circuit 30 can also control write mask features similar to those described above for the storage device of US Pat. No. 4,636,986.
However, the special function logic circuit 30 is operable to store the write mask value in the write mask register 34, which allows the write mask value to operate for multiple cycles and therefore the write mask value. The value is reproducible in a number of cycles since it was first loaded and after the intervention cycle of maskless constant velocity paging. The contents of write mask register 34, or the unmasked write signal, is sent to I / O buffer 24 by special function logic 30 via line WCLK, as described below, if desired. .

Here, the configuration and function of the special function logic circuit 30 will be described with reference to FIG. The special function logic circuit 30 provides a line RAS _- row address strobe signal that transitions from a high to a low logic value in the same manner as the row and column address signals on address terminals A0 through A8 are latched. a line CAS _- including latch for storing in association with each of the column address strobe signal various input values to the logic circuit. A special function signal is externally supplied to the dual port storage device 1 through the line SF, and the D-type latch 32
And 34 D inputs. The clock input of latch 32 is the line RAS 'clock signal which is the clock pulse generated by the RAM logic circuit 16 and delayed from the line RAS _- row address strobe signal, and the clock input of latch 34 is also the RAM logic. It is by connexion generated in the circuit 16 line CAS _- line CA which is delayed from the column address strobe signal
It is a clock signal which is the clock pulse of S '. Special functional logic circuit 30 further this latch includes a latch 36 line TR to the D input _- receive by connexion external transfer signal to be connected to, and line RA at its clock input
Receive S'clock signal. Latch 38, line WE _- receiving an external write enable signal through, and line RA
Clock controlled by the S'clock signal.

The data input signals on data terminals D0 through D7 are similar to the signals discussed above in latches in special function logic circuit 30.
40 is latched by the line RAS _- row address strobe signal. Therefore, the latch 40, in order to store the eight data signals from the data terminals D0 to D7,
It contains eight data bits, each of which is clocked by line RAS '. The output of latch 40 is connected to one input of multiplexer / converter 58, the output of the latter is connected to the input of 8-bit writemask register 54, and eight input / output buffers corresponding to the contents of writemask register 54. One of the storage devices 24 will be enabled for constant speed call write operations. Write mask register 54
The output of is connected to the first input of the multiplexer 60 and the other input of the latter is connected to the power supply Vdd, where, of course, each of the inputs of the multiplexer 60 is With eight parallel bits, mux converter 60 receives an eight bit parallel output of write mask register 54 or an all eight "1" bit value generated by power supply Vdd. The multiplexer / converter 60 uses the combinational logic circuit 44 to enable the line SELM.
Controlled via SK. Line SELMSK is set to a high logic value by combinatorial logic 44 when the contents of write mask register 54 seeks to generate a signal on eight lines WCLKS, each WCLK of line WCLKS being an input / output buffer. twenty four
Associated with a high logic value on line WCLK causes its associated I / O buffer 24 to write the value on one line of that line 27 to the selected memory location in array 2. Due to the low logic value of the line WCLKS from the combinational logic circuit 44, the multiplexer 60 causes the power supply Vdd to be supplied to its output,
This causes all I / O buffers 24 to indicate that a write operation should be performed, regardless of the contents of write mask register 54. Note that multiplexer 60 is also controlled by the output of AND gate 59, which receives at its input the line W'clock signal and line WEN write enable signal from combinational logic circuit 44. To receive. The output of AND gate 59 gates the supply of the selected input of multiplexer 58 to line WCLK, so that the available signal on line WCLK is input / output buffered at the proper time during the cycle. The device 24, and consequently the enable signal, is not supplied during the read cycle.

The data input signals on the data terminals D0 to D7 are stored in the 8-bit latch 42 in response to the line W'clock signal.
This clock signal, as discussed below, the line CAS transitions to a low logic value _- in accordance with the logic condition is satisfied between and WE signals
Generated by RAM logic circuit 16. The output of the latch 42 is connected to the input of the 8-bit color register 50, the input of the data multiplex converter 26, and the second input of the multiplex converter 58. The output of the color register 50 is connected to the other input of the data multiplex converter 26. Color register 50
The output of the latch 42 causes the combinational logic circuit 44 to
It is loaded when generating a high logic value on LDCLR, which causes eight I / O buffers 24 during subsequent write cycles.
The color register is selected as the data source during this write cycle by storing a predetermined data pattern to be supplied to the color register. As apparent from FIGS. 1 and 2, the multiplexer / demultiplexer 26 responds to the control signal on the line WTCLR from the combinational logic circuit 44 in the special function circuit 30 in response to the input via the line 27. Color register 50 to supply output buffer 24
, Or the output of the latch 42. The high logic value on line WTCLR also causes the contents of this color register 50 to be provided on line 27. As mentioned above,
Output drive circuit 31 supplies the value on line 27 to data terminals D0 through D7 during the read cycle.

The output of latch 42 is also provided to the second input of mux and converter 58, as described above, to provide an alternative method of loading write mask register 54. As will be described in more detail below, combinational logic circuit 44 responds to a user selecting one of two modes of operation for loading write mask register 54 in response to a high logic signal. A value signal will be generated on line LDMSK. The contents of latch 40 _{- (-} storing values of by the connexion latch been lines D0 from D7 line WE) (line RAS by connexion stores latched value from the terminal D0 D7 to) or the contents of the latch 42 If any of these are desired, the combinational logic circuit 44 will control the supply of the selected latch content to the writemask register 54 via line SLE40, and this register will be high. For logical signal, latch 40
The output of latch 42 is selected when the signal is a low logic value signal.

Combinatorial logic circuit 44 generates a signal on line FW to enable the selected row write aspect, as described in more detail below. In addition, for the purposes of the selected row write mode, the contents of write mask register 54 are provided by special function logic circuit 30 on line FWM to transmit the write mask information for the selected row write mode, and the color register. The contents of 50 are also supplied on the line FWD. As will be described below, the dual port constant velocity call storage device 1 of the present embodiment.
In the selected row write mode incorporated in, the data is written by not using the write line, but by invalidating the read operation by the read amplifier 4 instead. Therefore, the information used for this operation is preferably handled independently of the write cycle timing.

Referring to FIG. 3a, the generation of the line RAS 'clock signal is shown. The circuit shown in FIG. 3a is similar to that of FIG.
It exists in the RAM logic circuit 16. The line RAS _- row address strobe signal generated external to the dual port storage device 1 is inverted by the negation element 110 and, after being delayed by the delay stage 102 to the desired delay, the line RAS referenced above. ′
Generate a signal. Additional inversion by negator 104, line RAS _- generates a 'clock signal, about to be discussed below for this. If additional delayed version of the signal is used to thoroughly dual port memory device 1 for a variety of control functions _- it should be noted that, of course, necessary delay, and in fact, the line RAS 'and RAS' For example, it can easily be caused by the delay of ordinary technology. Line RAS ′
And RAS _- 'signal, of course, also in the RAM logic circuit 16 in a similar manner, or may also be generated cowpea in connexion number of ways well known and the person skilled in the art.

FIG. 3b shows the generation of the line W'clock signal in the RAM logic circuit 16, that is, the line W'clock signal as used in the circuit of FIG. Line WE _- receives the enable signal generated externally, this signal is Yotsute gated NOR gate 106, the other input of this gate line RAS _- is connected to the '. Line WE _- Write enable signal is line RAS _- the output of the NOR gate 106 to take the high level only when that occurs in the active period is connected to a first input of NAND gate 108, the latter another input line CAS ' It is connected to the. As mentioned above, the signal on line CAS 'is delayed and inverted into the form of line CAS _- column address strobe signal. The output of the NAND gate 108 is a NOR gate
When both the output of 106 and the line CAS 'have a high logic value, that is, depending on the establishment of the logic condition between the line WE _- and CAS _- signals, it takes a low logic value. Through the desired delay by delay stage 110 and inversion by negator 112, the line W'clock signal utilized in the circuit of FIG. 2 is generated.

As discussed generally above, combinational logic circuit 44 produces various control signals on lines 33, 35, 37, 39, respectively, in response to the states of latches 32, 34, 36, 38. These control signals control the dual port storage device 1 to perform its various modes of operation. Table 1 is a truth table for various special aspects of dual port storage device 1, some of which will be described in detail below.

As discussed above, the line WTCL control signal is a combinational logic circuit.
Generated by 44 causes the data multiplexer / converter 26 to apply the result to the input / output buffer 24 which selects between the contents of the color register 50 and the output of the latch 42. The line LDCLR signal is the signal generated by combinational logic circuit 44 which causes color register 50 to be loaded with the contents of latch 42. The line LDMSK signal is sent to the writemask register 54 in a signal generated by the combinational logic circuit 44, which in response to the state of line SEL40 controlling the operation of the multiplexer / conversion device 58, The contents of latch 42 cause write mask register 54 to be loaded with any of the contents of latch 40. Supplying the contents of the write mask register 54 to the line ECLK is the line SELMSK from the combinational logic circuit 44.
Enabled depending on the logic state of the. Accordingly, combinatorial logic circuit 44 includes the logic necessary to generate the appropriate control signals responsive to the inputs provided to it, which will be described with reference to FIG.

Combinational logic circuit 44 receives the outputs of latches 32, 34, 36, 38 via lines 33, 35, 37, 39, respectively, and, in addition, receives line RAS 'and W'signals as described above. The construction and operation of combinational logic circuit 44 will be described herein accordingly as it enables each of the special features listed in Table 1.

As mentioned above, the write mask register 54 is
Or the content of the latch 42 is loaded. Since the latch 42 is loaded in response to the line W'signal caused by the establishment of the logical condition between the line CAS _- and WE _- signals, the write mask.
The register 54 can be loaded not only in various ways, but also at various times during a cycle, which means that the user of the dual port storage device 1 can be loaded. Improve flexibility.

Combinatorial logic circuit 44 further includes an AND gate 137 for the purpose of generating a signal on line FW to enable the selected row write mode described in detail below. AND gate 137
Is the line 33, 39, 37 (line 37 is also line 39 is inverted by the NOT circuit 135 is inverted by the NOT circuit 116) receives, as a result, the row address strobe line RAS _- signal high from a low logic value An active logic state is generated on line FW at the output of AND gate 137 in response to the logic low on lines TR _- and WE- _and the logic high on line SF during the transition to.

Referring to FIG. 5a, there is shown the timing diagram for loading the write mask register from latch 40, i.e. during the first part of the cycle. Table 1 shows
As shown in Figure 5a, writemask register 54
There line WE _- with and SF signal is logic low, and the signal TR _- is at logic high, line RAS _- when performs a transition to a low logic value from the high, to be loaded early Shows.
At this time, the values on data terminals D0 to D7 are (line RAS '
(In response to the signal) the latch 40 is loaded and the lines SF, T
The R and WE _- signals are stored in latches 32, 36 and 38, respectively. The outputs on lines 33, 37, 39 of latches 32, 36, 38, respectively, are connected to the inputs of NAND gate 118 (the signals on lines 33, 37 are inverted by negating elements 114, 116). Was but connexion, the output of NAND gate 118, line WE _- transitions to a low logic value when the latched state is in a high logic value _- and latched state of the SF is and line TR when a low logic value. This provides a low logic value to one input of NOR gate 120 which has its other input controlled by the line RAS 'clock signal which is desired by negative delay stage 122. 2 to produce logic, and during the transition of the line RAS 'delayed clock signal from a low to a high logic value, the output of NOR gate 120 transitions to a high logic value and the multiplexer / demultiplexer of FIG. Generate a high logic value on line SEL40 to 58, latch 4
Indicates that an output of 0 should be selected. Line SEEL40
Is also connected to one input of the OR gate 124, the line LDM
Generates a high logical value on SK. The line LDMSK line is connected to the write mask register 54, and the transition from the low to the high logical value causes the write mask register 54 to be multiplexed.
It should be loaded with an output value of 58, which in the illustrated case is the content of the latch 40. This action causes the writemask register 54 to be loaded during the first part of the store cycle.

Line TR _-, WE _- and SF is the line RAS _- upon transition to a low logic value, after being stored in the respective latch, line TR _-, WE _-
And SF are in a "don't care" state for the purpose of loading the write mask register 54 and can transition to another logic value. However, following the load hook of the write mask register 54, either the read or write, line WE _- and TR _- (U.S. Patent No. 4,636,986
As the storage device No., line TR to act as constant velocity call output enable signal _- depending on), it is by connexion performed dual-port memory device 1. Figure 5a shows the write mask
It illustrates the relative likelihood of a write cycle occurring after loading register 54 (the user's interest in performing a write operation is evidenced by the load of write mask register 54). As shown in FIG. 5a, row address value, i.e., the line RAS _- state from the address line A0 A8 during the transition of the write mask register 54 is received during a time being loaded, also , Row address decoding and selection is performed by the RAM logic circuit 16 and the X-decoder 18 in the well-known constant speed call manner. The column address value appears on address terminals A0 through A7 in association with the line CAS _- address strobe signal, as shown in Figure 5a.

Table 1, line CAS _- value data or color register received from the data terminals D0 on D7 line SF at the time of transition
It is shown that which of the contents of 50 is the data to be written in the array 2 is determined. As shown in Figure 2, latch 34 is line CAS _- loaded with the value of the clock signal signal in response to SF, the clock signal is delayed and inverted signal related line CAS signals. Line 35 from the output of latch 34 is NOR (after being inverted by negator 125).
Connected to one input of gate 126. AND gate 127
Receives the output of NAND gate 118 at one of its inputs, the latter, as described above, the writemask register.
It is at a low logic value while 54 is loaded, which of course controls the output of AND gate 127 to a low logic value, which output is provided to the other input of NOR gate 126. If line CA
S _- If the value of the line SF at the transition of the signal is a logic value "1", and the line to a high logic value output of NOR gate 126 WTCL
Will be generated in R. Also if the line CAS _- if the transition time of the line SF is a logical value "0", a low logic value line WTCLR
Will be generated in. Line WTCLR is connected to the control input of line data multiplexer 26 which supplies the contents of color register 50 to line 27 in response to line WTCLR being at a high logic value and signal WTCLR being a low logic value. At the time of latch 4
The contents of 2 are supplied to the line 27. Thus, combinational logic 44 is operable to select the data source in the same memory cycle as that load of write mask register 54, the selection circuit CAS _- line at the time of transition Responds to the value of SF.

Lines 33, 37, 39 are also connected to AND gate 128, which precedes line 33 by inverting its signal by negator 114. It was but connexion, line RAS _- line WE at the time of transition _- as long as the value has been made to the logical value "0", the output of AND gate 128 is at a logic value "0". The output of the AND gate 128 is connected to the line SELMSK through the NOT element 130, which line is connected to the control input of the multiplexer 160. High logic value of channel SELMSK the write mask register 54 during the cycle line RAS _- since it is loaded in response to a transition of the signal, the line of the contents of the write mask register 54 to the output buffer unit 24
Indicates what should be selected to generate the signal on WCLK. Furthermore, the lines 33, 37, 39 are also connected to the inputs of the AND gate 132 without being inverted and the AND gate 1
The output of 32 is also low logic when lines 33 and 39 are low. The output of the AND gate 132 is connected to the NOT element 134, and the line WEN signal generated at the output of the latter is the AND gate 59 of FIG.
Is connected to one input of. Therefore, as long as the output of AND gate 132 is at a low logic value, line WEN is at a high logic value and the line W'clock signal is enabled and gated through the multiplexer / converter 60 to the write mask. -The contents of the register 54 are supplied to the line WCLK. As mentioned above, the line WCLK signal has a write clock signal to the I / O buffer 24, causing the data on line 27 to be written to array 2 and, in this case, stored in write mask register 54. These I / O buffers associated with the holding "0" do not perform write operations. Line WE were but the connexion, other transitions from high while active in the low logic value to a low logic value _-
Depending on the logic condition is satisfied during (i.e., line RAS _{- -} line CAS the line WE in connection with the transition _- the transition to and to return to a high logic value generating line W 'clock signal to the logical value A clock signal is generated on line W ', which gates the select input of multiplexer 60 to line WCLK and causes the I / O buffer 24 to perform the write operation.

FIG. 6 is a register scale diagram showing the write mask write operation. An example of 8 bit storage locations before the mask write operation is shown at 2n, where each of the 8 bits corresponds to an addressing location within each array 2 of dual port storage device 1. In this example, the data source containing data to be written is the color register 50, an example of the contents shown in FIG. 6 is a 10101010 _2. Write mask
The contents of register 54 are, in FIG. 6, only the four central bits, that is, the lower third of the eight bit storage locations.
The write operation is masked only for the second to sixth digits, and conversely, the write operation is masked for the two most significant digits and the two least significant digits of the memory location 2n. The updating of the addressed memory location during the execution of the write cycle described above, where the contents of the color register 50 are written in a mask write, is shown as 2n 'in FIG. It is clear that only the middle four bits are written with the contents of the color register 50 and the two most significant digits and the two least significant digits are kept the same as before the write operation.

As mentioned above, the dual port storage device 1 has a latch 42 which is clocked by the line W'clock signal.
Write mask during the latter part of the memory cycle.
The register 54 can be loaded. Figure 5b shows the timing cycle of loading the write mask register during the latter part of the store cycle. Line 33,37,39
Are connected to the inputs of AND gate 132 without inversion of any of these three signals, as discussed above, and thus the output of AND gate 132 is the output of these lines. It is at a high logic value when all three signals are at a high logic value. This corresponds to Table 1, in this table, the signal-seat load due to the logic condition is satisfied in the write mask register 54 is RAS _- line SF at a high logic value both at the time of transition, W
E _- and TR _- are by go-between can be used to signal. AND gate 13
The high logic value at the output of 2 is passed through the negation element 134 to the line WEN
Resulting in a low logic value on the write line WCLK clock signal, thereby disabling a write operation to array 2. The output of AND gate 132 the other input with the latter being connected to one input of NAND gate 136 receives the line connection W 'line, and (line RAS _- after the transition) line WE _- or C
AS _- Slow whichever i.e., the output of NAND gate 136 until a logical condition formed physician therebetween holds the logic high value. NOR gate 138 receives at one input the output of NAND gate 136 and at its other input the output of latch 34 via line 35, and as described above, latch 34.
The line CAS _- storing the value of the transition time signal SF of. First
Table, write mask register 54 a line CAS _- loaded when in the line SF is a logical value "0" at the time of the transition, line RAS _- line SF at the time of transition, WE _-, and TR _- are all logic high It indicates that there is. Therefore, to load the write mask register 54, the signal on line 35 should be low.
It will be at a low logic value in response to the line CAS 'clock signal storing the SF signal in latch 34.

Write load hanging in the mask register 54, (line RAS _- transition after) the line WE _- and CAS _- by the logical condition formed between connexion completed. Example illustrated in FIG. 5a, the line WE _- the line CAS _-
, Followed by the transition, and the description below uses this example. Referring back to FIG. 2, the latch 42 receives the data terminal D0 in response to the line clock signal W '.
Loaded with value on D7 from the clock signal (while the other is active, Figure 3b reference) line WE transitions from high to a low logic value _- is delayed in the signal _- and CAS. FIG. 5b is the line WE _- data terminal D at the time of transition to a low logic value
Write Mask Register 5 as "MASK" on 0 to D7
The expression of the contents of 4 is shown. In addition, the line W'clock signal causes the output of NAND gate 136 to transition to a low logic value, thereby producing a high logic value at the output of NOR gate 138.
This results in a high logic value on line LDMSK via OR gate 124, thereby loading write mask register 54 also at the output of multiplexer 60. NAND gate 11
As long as the output of 8 is at a logic "1" (line 39 is high), line SEL40 will be low due to the operation of NOR gate 120. As described above, the low logical value of the line SEL40 controls the multiplexer / conversion device 60 to select the contents of the latch 42, which is generated when the line LDMSK signal is generated as described above.
Supply to write mask register 54 and latch 42
Holds the value of the data terminals D0 to D7 loaded on it at this time. In this way, the combinational logic circuit 44
Write mask register 54 according to the timing in Figure 5b.
Performs a logical condition is satisfied load hook, also line SF the line CAS _-
There is a low theoretical value at the transition of.

Color register 50, in the same manner as the write mask register 54 in the logic condition is satisfied loads embodiment, as shown in Table 1, line CAS _- loaded only when the signal SF at the time of transition is at a high logic value . This is done by NOR gate 140, which is the NAND gate 13 discussed above.
The latter receives the output of 6 and the latter negates the signal on line 35.
Receive after reversal by. Line CAS _- high logic value of the line SF during transition is a logic low of one input of NOR gate 140 results. Line transitions from high to low logic value WE _- and CAS _- in late, as described above, the output of NAND gate 136 transitions to a low logic value, driving the output of NOR gate 140 to a high logic value. The output of NOR gate 140 is line LDCLR, which is connected to color register 50, and this output loads color register 50 with the contents of latch 42 at a high logic value. Latch
42 is loaded with the value on data terminals D0 through D7 (ie, the value "content" in FIG. 5b) in response to clock signal W ', as described above.

Note that either constant loading of dual port storage 1 is prohibited for either loading color register 50 or delay loading write mask register 54. This ensures that the address values on address terminals A0 to A8 are on line RA, as shown in FIG. 5b.
The "do not cares (worry)" in both of the transition _- S _- and CAS. As discussed in [Prior Art],
The ability to use the contents of write mask register 54 in multiple store cycles and the ability to perform a maskless write operation without requiring the loading of write mask information prior to a subsequent mask write operation is advantageous. Is. Therefore, Table 1 shows some for the repeated use of the contents of the writemask register, as well as for holding the writemask information in the writemask register while performing an unmasked write operation. It is shown that the operation mode of can be used.

Special function logic circuit 30 and combinational logic circuit 44 therein
Is designed to achieve these functions.

FIG. 5c illustrates an unmasked write operation without reloading the writemask information, that is, utilizing the previous contents of writemask register 54. During the transition, line TR _{- -} line RAS and the SF is at a high logic value, while the line WE _- is at a low logic value. As previously mentioned, latches 32,36,3
8 stores these values under the control of the line RAS 'clock signal, which are received by the combinational logic circuit 44. Referring to FIGS. 2 and 4, since the output of AND gate 128 is at a low logic value in these combinations, line SELMSK is at a high logic value, and therefore the contents of writemask register 54 are: The output of the AND gate 59 will be selected to feed the line WCLK line when transitioning to a high logic value. Line RAS _- transition at line TR _-, SF and WE _- since the output of the Yotsute in combination AND gate 132 is a logic low, Shigatsute, line WEN is at a high logic value, which is the line WE _- a line transitions to logic low CAS _- to allow the logical condition is satisfied between, as a result, the output of the Oka converter 60, i.e., to supply the contents of the write mask register 54 to the line WCLK line.

However, the above-described line TR _-, SF and WE _- For the combination, the contents of write mask register 54 is applied during this cycle have not been changed from the previous state. Reload of write mask register 54 is inhibited by combinatorial logic 44, which causes the low logic output of AND gate 132 to also place the output of NAND gate 136 at a high logic value, the latter further NOR gate. This is because it puts the output of 138 at a low logic value. As shown in the 5c Figure, line RAS _- Line TR during transition _-, SF and WE _- above with respect to the combination of
The output of NAND gate 118 is at high logic value, so NOR gate
The output of 120 is forced low. Therefore, both inputs of OR gate 124 are at a low logic value, which forces line LDMSK to a low logic value to prevent write mask register 54 from being loaded. The previous contents of writemask register 54 are thus retained and, as described above, the line
Used during the write cycle selected by SELMSK.

Line CAS _- depending on the state of the line SF during transitions, data supplied to the line 27 for receiving a mask write operation, if the contents of the color register 50 or latch 42 depending on the line W 'clock signal Therefore, it can be any of the data values stored on data terminals D0 to D7. The combinatorial logic circuit 44 shown in FIG. 4 allows this selection by passing through the AND gate 142 according to the truth table of Table 1, which gate connects its three inputs. 33, 37, 39, and the signal on line 39 is inverted by inverting element 116. Was but connexion, the output of AND gate 142, line RAS _- line is a logic high value at the time of transition TR _- would in response to a combination of taking a high logic value _- the line WE in the SF and logic low. AND
The output of gate 142 is connected to the first output of OR gate 144,
When it is a high logic value, it drives the output of OR gate 144 to a high logic value. The output of the OR gate 144 is connected to the first input of the NAND gate 146, the other input of the latter is connected to the line W'clock signal described above, and its output is the AND gate 127.
Connected to the input of. Therefore, NAND gate 146
Is driven to a low logic value when the output of AND gate 142 is at a high logic value on the transition of the line W'clock signal from a low to a high logic value. The low logic value output of NAND gate 146 forces the output of AND gate 127 to a low logic level,
This causes the NOR gate 126 input to go low as described above. Line WT as described above with respect to Figure 5a.
CLR is driven to by connexion high or low logic value to the operation through line 35 from the latch 34, the latch the line CAS _-
The line SF value at the time of transition is stored, and by this, the multiplexer / conversion device 26 is controlled to select the contents of the color register 50 and supplied to the input / output buffer storage device 24 via the line 27. Or the values of the data terminals D0 to D7 are selected. 5c
The figure shows the timing necessary to provide such valid data "DATA" when valid input data is the desired data source for data terminals D0 through D7. As mentioned above, the latch 42 stores input data in response to the line W'clock signal, and the output of the latch 42 is provided to one input of the data multiplexer 26 if the user so desires.

The contents of write mask register 54 are special function logic circuits.
In the special cycle performed by 30, and the combinational logic circuit 44 therein, it is ignored for write operations, but held for subsequent mask write operations. The timing of an example of such a cycle is shown in Figure 5d. During the transition, as shown in Table 1, line TR _{- -} line RAS, SF is at a high logic value, whereas the line WE _- is at a low logic value, also as described above, these The value of is latched by the line RAS _- clock signal.
It is stored in 36,38,32. Due to the combination of this signal appearing on lines 37, 39, 33 (line 33 is counter-warmed by negator 114), the output of the AND gate transitions to a logical "1" and the line SEELMS goes low. As a result, the multiplexer / converter 0 is made to ignore the contents of the write mask register 54, select the power supply Vdd, and supply it to the line WCLK at an appropriate time. Line RAS _- because the contents of the latch 32 corresponding to the state of the line SF at the transition of the signal at a low logic value, there is an output also logic low of AND gates, places the line WEN to a high logic value, the but On the other hand, since the line WCLK has a low logical value, the line W'clock signal is passed through the multiplexer / converter 26 and the line W'clock signal is transmitted.
Generates a high logic value on all WCLKs. With respect to the previous cycle, the 5d diagram, line WE _- the line CAS _- indicates that it is driven to a low logic value after the transition, the line W 'is to perform the write operation via the clock signal There is.

Signal RAS _- line at a high logic value of遷時of TR _-, WE _- and output the output of the AND gate 132 is logic low and NAND gate 118 for a combination of line SF to a low logic value logic high As in Figure 5b, the write mask register
54 loads are forbidden. The new value is not loaded into the writemask register 54 (line LDMSK remains low) and the previous value stored therein is retained. Therefore, the subsequent cycle as shown in FIG.
The write mask information held in is used to perform the write operation without having to reload this write information.

As discussed above in connection with the 5c Figure, line CAS _- the state of the line SF during transition, or (line SF using the contents of the color register 50 write cycles of the 5d diagram as data source Low logic value) or the value of data terminals D0 to D7 (first
Use either "DATA" in Fig. 5d. Combinational logic circuit 44 performs this selection,
This is because the output of AND gate 128 is connected to the second input of OR gate 144, thereby providing the output of AND gate 142, discussed above in connection with the cycle of FIG. 5c.
This is because it has the same effect as the generation of the line WTCLR by the NOR gate 126.

In the use of dual port storage devices such as the dual port storage device 1 shown in FIG. 1 within a video device, multiple sequential stores are often written with equivalent data. For example, where the dual port storage device 1 includes a bit map display of a graphical image, a large area of the displayed image is filled with a color. Therefore, it may be advantageous to write equivalent data to multiple locations within the dual port storage device in a single cycle.

Referring to FIG. 7, a block diagram of the Y-decoder 20 is shown, which includes circuitry that implements the feature of addressing adjacent columns within it in a single cycle,
Hereinafter, this feature will be referred to as the "block write" feature. Although the operation of the dual port storage device 1 is enhanced by the features described below in connection with FIG. 7, it should be noted that the dual port storage device described below has a block write feature. It is possible to operate sufficiently even without. Also note that FIG. 7 shows a Y-decoder for a single array 2 in dual-port memory 1, but of course the circuit shown in FIG. It is associated with each of the Sequences 2 shown. The Y decoder 20 has the address terminal A0 as described above.
To A7 receive the latch values of the column address signals received on A7, the latch column address lines being represented by terminals AY0 to AY7 in FIG. Array 2 of course
Since in each absent only 256 columns, line CAS _-
The value of the terminal A8 latched by is not used in the column decoding operation. The decoder 200 receives the terminals AY2 to AY7, decodes these 6 bits, and outputs 64 output lines 20.
Put in 2, one of these is enabled by being at a high logic value. Therefore, each of the output lines 202,
Display the selection of the group of four columns in its associated array 2.

There is a column selection circuit 204 associated with each group of four columns, and for simplicity only one column selection circuit 204 is shown in FIG. Associated output line 2 from predecoder 200
02 is connected to one input of an AND gate 206 and one input of an AND gate 208 included in each column selection circuit 204. Line WTCLR from special function circuit 30 is AND gate 20
The line WTCLR connected to the second input of 6 and inverted by the inverting element 207 is connected to the second input of the AND gate 208. As mentioned above, the line WTCLR is generated when the color register 50 is written to array 2 and the features described herein in addressing the multiple columns in each of array 2 are the same signal. It is possible to use. Also included in the column selection circuit 204 is a 4-to-1 decoder 210, which selects terminals AY0 through AY7 for selecting columns in array 2 to be addressed in the constant velocity call mode. Perform the actual decoding of the lower column address bits. 4--1 Decoder
210 indicates four lines 214n according to the values of terminals AY0 to AY7.
Drives from 214n ₊₃ . Pass transistors 212n through 21
2n ₊₃ connects its corresponding line 214n to 214n ₊₃ to the gate of its corresponding transistor 220n to 220n ₊₃ . The gate of each transistor 212n to 212n ₊₃ is controlled by the output of AND gate 208. Therefore, in the event that the block write feature is selected, i.e., the line WTCLR is at a high logic value, the operation result of the 4-to-1 decoder 210 will be the corresponding output line 202 and its associated four lines. Even if a group of columns is selected, the operation result of the 4-to-1 decoder 210 will be ignored.

The column select circuit 204 receives an even bit of the contents of the latch 42, shown as lines 43 ₀ , 43 ₂ , 43 ₄ , 43 _{6 in} FIG. As described above, latch 42 stores the values on data terminals D0 through D7 it receives at each clock after the write enable signal clock signal. Line 43 ₀ , 43 ₂ , 43
_4, 43 ₆ each is connected from the pass transistor 216n to 216n _+3, these transistors are connected to its gate to the output of an AND gate 206, each of these transistors also 220n from the corresponding transistor 220n It is connected to the gate of ₊₃ .

Transistors 220n to 220n ₊₃ connect the I / O buffer memory 24 associated with array 2 to the read amplifier 4 associated with that column, thereby writing to the selected column in a manner well known in the art. Achieve the action. In normal operation when line WTCLR is not available, the output of AND gate 206 is at a low logic value, and lines 43 ₀ , 43 ₂ , 43 ₄ , 43 ₆
The use is prohibited so as not to affect the state of 220n to 220n ₊₃ . At the same time, the outputs for the group of four columns selected by the predecoder 200 of the AND gate 208 are at a high logic value, and thus the result of the 4-to-1 decoder 204 is relevant. It makes it possible to control the connection of the read amplifier 4 to the selected column of the input / output buffer memory device 24.

Combinational logic 44 line as shown in Table 1 in order to enable use by connexion line WTCLR the WE _-, SF and RT _- when block write feature is selected depending on the state of the terminal
The output of AND gate 206 would be at a high logic value for the group of four columns selected by predecoder 200 in response to AY2 through AY7. About this situation, lines 43 ₀ , 43 ₂ ,
43 _4, 43 ₆ condition of determines any transistors 220n of 220n ₊₃ conducts, and indeed in the associated group with the highest total of four connections to the input and output storage buffers 24 column It is possible. The bit contents of color register 50 corresponding to array 2 are then written into the column selected by the state of lines 43 ₀ , 43 ₂ , 43 ₄ , 43 ₆ from latch 42.

Referring to FIG. 8, there is shown a timing diagram illustrating the block write operation. As can be seen from Table 1 above, the line RA is associated with the line SF being high logic when the line CAS _- column address signal goes high.
S _- line at the time of transition to activity of TR _- is at a high logic value and the two lines WE _-, the contents of the color register 50 during the write cycle when the SF is at a low logic value is written. According to Table 1 and as shown in FIG. 8, the color register write operation (and the block write feature in this embodiment).
Is the line RAS _- when a row address strobe signal transitions to an active at its low logic value, line TR _- is at logic high, and the line WE _- that the logical AND of the SF is at a low logic level Request and also the line CAS _- column address strobe signal goes active, requesting line SF to be at a high logic value. And WE _- line CAS block write mode is to migrate in this way accompanied connexion to be enabled, the active
_- the value of the even bits of the data input signal from the data terminal D0 D7 according to the logic condition is satisfied, the (i.e., the data terminal D
0, D2, D4, D6) specify the column in the group of four columns to be written with the contents of the color register 50 for the corresponding array 2. As mentioned above, all 4 of such rows
One is addressed in this manner, providing the feature that four columns within each of the eight arrays 2 are written in a single cycle.

The first table, referring again line SF and WE _- both the line R
AS _- in the event that a low logic value at the time of transition to activity, the mask write operation is subordinate connexion available to block write feature. In this way, the contents of color register 50 are written to multiple columns (within a group of four columns), only to the selected other array. Referring to FIG. 9, the color register
Fifty applications are shown on a register scale, and write mask register 54 is shown to modify the contents of memory locations within each of the two arrays associated with the two columns COLn and COLn _{+ 1} . As described above, the line CAS in timing of Figure 8 _- the data terminal D0, D2 when the enable signal is shifted to the active has a logical value "1" and the data terminal D4 _- line WE after has decreased to the active , D6 is at the logical value "0", the columns COLn and COLn _{+ 1} are selected. In the example of FIG. 6, only the lower third bit through the sixth bit were written with the contents of color register 50, however, the block write feature described above does not affect the selected columns COLn and COLn.
_It also _{happens at +1} at the same time.

Here, the configuration and operation of the additional circuit in the dual port memory device 1 for executing the selected row write operation will be described in detail with reference to FIG. FIG. 11 shows a single read amplifier 4, which is a bit line 300a and 300b.
Connected to. The configuration of the bit circuit shown in FIG. 11 is
April 14, 1987 David J. Matsukeroy (David J.
McElroy) and assigned to Texas Instruments Limited Liability Company, a "wrap-around" bit line similar to that described in US Pat. No. 4,658,377. Data is stored in the form of charge storage in storage capacitors 306a and 306b, each of which has a transfer gate 308a.
And 308b to connect to the bit lines 300a and 300b. Transfer gates 308a and 308b are row select lines XWD0 and XW
Controlled by the D1 signal, these signals are generated by the X decoder 18 from the decoding of the row address signals received by the dual port store 1. of course,
A number of storage capacitors 306 are associated with each of the read amplifiers 4, half of these capacitors being on the bit line 30.
0a and the other half can be connected to the line 300b (ie, for a 1Mb bit constant velocity call store in a 512 × 2048 configuration, out of 512 storage capacitors 306).
256 can be connected to each of the bit lines 300a and 300b). For simplicity, a single storage capacitor 306 is shown in FIG. 11 associated with each of the bit lines 300a and 300b. A single row address signal line is associated with each storage capacitor 306 associated with read amplifier 4 and only one of the row select signals (eg lines XWD0 and XWD1).
Only one of them will take a high logic (active state) value during the call cycle. Dummy capacitors 302a and 302b associated with each of the bit lines 300a and 300b are provided to store a reference charge and the charge in the storage capacitor 306 selected for this reference charge is read out by the amplifier 4.
Are compared. In this embodiment, the dummy
Capacitor 302 is substantially the same size as storage capacitor 306 and has the same capacitance. Dummy capacitors 302a and 302b can be connected to bit lines 300a and 300b by dummy transfer gates 304a and 304b, respectively. Dummy transfer gates 304a and 304b are controlled by dummy word line DUM0 and DUM1 signals, respectively, which are generated by X decoder 18 in response to a row address signal in the manner described below. To be done.

Further connected to the dummy capacitors 302a and 302b are dummy precharge transistors 312a and 312b, each of which is connected to a precharge voltage Vref. The gate of the dummy precharge transistor 312 is controlled by the precharge clock signal PC, which is provided during the precharge portion of the memory cycle during which dummy word lines DUM0 and DUM1 are supplied.
Has a low logic value, and therefore dummy capacitor 302
Is isolated from its associated bit line 300. During the application of the precharge clock signal, transistor 312 is turned on and the precharge voltage Vref is applied to dummy capacitor 302 and stores the associated charge inside this capacitor. In this embodiment, the voltage Vref is about one-third of the power supply voltage Vdd of the dual port storage device 1 and the dummy capacitor 302 has almost the same capacitance value as the storage capacitor 306, so all "1" state. Approximately 1/3 of this is stored in each of the dummy capacitors 302 during precharging (all "1" states are stored by the application of the Vdd value to the storage capacitor 306).
Written or stored in). Dummy capacitor 302
This 1/3 Vdd value in the range between the reference charge of "1" and "0" states allows for the reduction of all stored "1" states due to leakage of storage capacitors and other effects. Therefore, it is suitable for this embodiment that the values are almost equidistant from them.

Bit lines 300a and 300b are preferably equalized and 1/2 Vdd, as described in the above-referenced US Pat. No. 4,658,377.
It is precharged to the voltage of. That is, after the restore operation of the read amplifier 4 in the preceding memory cycle, one of the bit lines 300 is substantially at Vdd and the other bit lines are substantially at ground potential, thus precharging to a voltage of 1/2 Vdd. Is achieved for the most part by simply equalizing the two bit lines 300a and 300b with each other, thus requiring less external power to precharge these bit lines 300 to the desired voltage. This equalization and precharging occurs after the active cycle and can of course occur during the precharging of dummy capacitor 302.

As described in U.S. Pat. No. 4,658,377, the folded bit line arrangement connects the storage capacitor 306 in the selected row to one of the bit lines 300, while the dummy capacitor 302 is connected to the other in that bit line pair. Bit line 3
Works by connecting to 00. For example, if storage capacitor 306a is about to be selected, the row select line XWD0 signal will take an active or high logic value to turn on transfer gate 308a, thereby causing storage capacitor 306a to go to bit line 300a. Will be connected. The decoded row address value will drive dummy word line DUM1 to an active or high logic value to turn on dummy transfer gate 304b, which will connect dummy capacitor 302b to bit line 300b. . U.S. Pat. No. 4,65 listed above
Readout amplifier 4, as described in No. 8,377,
After the storage capacitor 306a and the dummy capacitor 302b are connected to this read amplifier, the voltage stored differentially between the bit lines 300a and 300b is read out (readout amplifier 4 is selected by the Y decoder 20). This read differential voltage is amplified to a logic value for transmission to the I / O buffer 24 (if any) and (whether its associated read amplifier 4 was selected by the Y decoder 20). The read logical value is restored in the storage capacitor 306a. It should be noted that the above-referenced U.S. Pat.No. 4,658,377 describes a solution of segmented folded bit lines, where each of the bit lines 300 is segmented, in which case the individual segment selected. Is to be applied to the read decoder 4 with additional decoding. Although the advantages of this partitioning solution are equally applicable to the dual port storage device 1 described herein, the configuration of FIG. 11 includes such partitioning of the bit line 300 for simplicity. No, because the partitioning solution is not essential for achieving the operation and advantages of the selected row write aspects described herein.

For the purposes of the selected row write mode described herein, transistors 320a and 320b are respectively bit lines 300a and 30b.
Connected to 0b. The gates of transistors 320a and 320b are controlled by the line F0 and F1 data signals, respectively. Transistors 320a and 320b are connected via line 321 to one electrode plate of capacitor 322, which is grounded to the other electrode plate. Transistor 32
4 is connected in parallel with the capacitor 322, whose gate is controlled by the precharge clock signal PC, when the precharge clock signal PC is active or at a high logic value (which occurs during the precharge portion of the memory cycle). The capacitor 322 discharges to reach ground potential. Line 321 is likewise for transistor 3
It is possible to connect via 20 to an additional bit line 300 associated with another read amplifier 4. In this way, the capacitor 322 is shared by many pairs of bit lines 300.
Preferably, the sharing of a single capacitor 322 is limited to the bit line 300 associated with a single input / output (ie, within a single array 2) of dual port storage device 1. The selection of the data state provided by the capacitor 322 is described further below.

The selected row write scheme incorporated in this embodiment negates the charge provided to the read amplifier 4 by the storage capacitor 306 and the dummy capacitor 302, so that each read amplifier 4 is forced to the same. This is accomplished by placing the state and restoring the same data state in each of the storage capacitors 306 in the selected row. In this embodiment, this is done by connecting the capacitor 322 to either the bit line 300 to which the storage capacitor 306 is connected during reading or to the partner bit line 300 to which the dummy capacitor 302 is connected. Is achieved. In modern dynamic constant velocity read storage devices, the typical parasitic capacitance of the bit line 300 is the typical storage capacitor 3
It is, of course, well known that it is about 10 times the capacitance of 06. The capacitor 322 is set to discharge either the storage capacitor 306 or the dummy capacitor 302, and the bit line 300 to which the line 321 is connected through the transistor 320, the read amplifier 4 being set in the pre-defined polarity direction. Depending on the extent, it is of sufficient size to partially discharge. If the selected row write operation is accomplished such that the storage capacitor 306a is written to the "0" state, the line F0 signal goes active prior to reading,
Capacitor 322 is connected to bit line 300a, which acts to discharge storage capacitor 306a and bit line 300a regardless of the stored data in storage capacitor 306a. During a read, the read amplifier 4 therefore behaves as if the storage capacitor 306a has no charge stored therein (ie a "0" state). In the restoring operation, the read amplifier 4 operates as the storage capacitor 30.
Restore the "0" state in 6a. This is the word line XWD0
It also occurs for each of the storage capacitors associated with the signal, so that the entire row of storage devices 1 is the Y decoder 20.
Also, the "0" state is written in a single cycle without using the write circuit in the memory device 1.

Table 2 shows the states of the bit lines to which capacitors 322 are connected to achieve "1" and "0" state writes in the storage capacitors 306a and 306b associated with the bit lines 300a and 300b, respectively.

As is apparent from FIG. 11, in order to write the "0" state, the capacitor 322 must be connected to the bit line 300 of the selected storage capacitor 306, and to write the "1" state, Capacitor 322 must be connected to bit line 300 of the selected dummy capacitor.

The minimum capacitance of capacitor 322 to achieve the above function can be easily calculated. In the worst case for the capacitor 322 in the selected row write operation, writing a "0" state to the bit line 300 to which this capacitor is connected while the storage capacitor 306 is storing a "1" state. Is. In this case, the operation
322 to (for example) discharge the storage capacitor 306a from the all "1" state, and to read that the read amplifier 4 is in the "0" state of the storage capacitor 306a while accomplishing the write, To ensure that it is restored in this storage capacitor, it is possible to further discharge the bit line 300a associated with the storage capacitor by the amount of charge stored in the dummy capacitor 302b (associated with bit line 300b). I need. Dummy capacitor 302b
Therefore, the electric charge supplied to the bit line 300b is the precharge voltage difference Vbit−Vr of multiplying the capacitance C _{302 of} this capacitor.
ef, where Vbit is the bit line precharge voltage or Vref
Is the precharge voltage of the dummy capacitor. The maximum charge delivered to the bit line 300a by the storage capacitor 306a is Vdd of multiplying the capacitance C ₃₀₆ of this capacitor.
It is the voltage difference of Vbit (when "1" is stored). Capacitor
The charge that can be stored by ₃₂₂ is the voltage difference between its initial precharge voltage V ₀ applied to its capacitance C ₃₂₂ and the bit line precharge voltage Vbit, to which this capacitor It is connected through the transistor 320a. Each pair of bit lines 300 may have its own capacitor 322 and associated precharge transistor 324. However, from a layout perspective, it is much more efficient to share a single capacitor 322 and precharge transistor 324 with multiple pairs of bit lines 300. In this case, of course, capacitor 322 is sized to meet the worst-case conditions (eg, discharging the "1" state from all selected storage capacitors 306) for all associated pairs of bit lines 300 at the same time. You need to be one. Therefore, the sequential selection row write operation requires that the capacitance C ₃₂₂ of the capacitor 322 satisfy the following relationship.

C ₃₂₂ (Vbit-V ₀ )> n [C ₃₀₆ (Vdd-Vbit) + C ₃₀₂ (Vbit-Vref)] where n is the number of storage capacitors 306 selected for each row sharing the single capacitor 322 ( 1 for n if each pair of bit lines 300 has its own capacitor 322
be equivalent to). This relationship therefore follows that the charge to be stored by the capacitor 322 in such an operation is stored by the n storage capacitors 306a having a "1" state (with respect to the precharge voltage of the bit line 300a). Of added charge (with respect to precharge voltage of bit line 300)
This is equivalent to the requirement that it must be at least equal to the charge stored by each of the dummy capacitors 302b. However, as described above in this example, V ₀ is at ground potential, Vbit is 1/2 Vdd, C ₃₀₂ is equal to C ₃₀₆ , or Vref is 1/3 Vdd. Therefore, the above relationship defining the value of the capacitance of the capacitor 322 is simplified as follows.

C ₃₂₂ (Vdd / 2)> n [2Vdd / 3)] From now on, it becomes as follows.

C ₃₂₂ > n [C ₃₀₆ (4/3)] If the capacitance value of the storage capacitors 306 is 5fF, assuming that 256 storage capacitors 306 are selected in one row of each array 2 (constant speed call) 512 × 204 in storage device 1
8 storage capacitors are organized in 8 arrays 2 of 512 x 256 each). The capacitance value of capacitor 322 should be at least about 17PF. Of particular note is that by precharging capacitor 322 to ground potential, if bit line 300 is precharged to 1/2 Vdd, then capacitor 322 of minimum size is sufficient.

The dimensions of the capacitor 322 do not assume its practical maximum due to the desire to have the performance of the selected row write mode described herein. However, it should be noted that if the capacitor 322 over discharges the bit line 300 to which it is connected, it will adversely affect the read amplifier 4 which does not utilize the selected row write mode. This situation may occur in a storage device configured as dual-port constant velocity call storage device 1 in which each of array 2 is independently selected or prohibited in executing the selected row write mode.

Referring to FIG. 11a, there is shown a typical complementary metal oxide semiconductor (CMOS) read amplifier 4 described in the above-referenced US Pat. No. 4,658,377. Bit lines 300a and 300b are connected via p-channel transistor 346a (or 346b, but bit line 300b via transistors 319a and 319b, respectively).
And n-channel transistor 344a (or 344)
Connected to the read connection points 301a and 301b, respectively, at the junction with b), these transistors 344 and 346 work in the well-known cross-coupling negation circuit. The connection point 340 at the source of the transistor 344 is shared by the plurality of read amplifiers 4, as is the connection point 342 at the source of the transistor 346. Clock signal S1 (clock signal S1 is clock signal S2 during read operation)
Prior to the transition to a high logic value to initiate amplification, node 340 is isolated from ground, which causes the differential voltage between bit lines 300a and 300b to precede its amplification. Stabilize. Furthermore, during this time, the clock signal T takes a high logic value, and as a result, the bit line 300a and
300b is connected to read connection points 301a and 301b via transistors 319a and 319b. The stabilization of this difference voltage is
This is effective in preventing erroneous reading due to noise coupled to the read amplifier 4.

If the capacitance of the capacitor 322 in FIG. 11 is too large, the bit line 300 to which it is connected is 1/2 Vdd
It is discharged to a voltage below the threshold voltage of the underlying n-channel transistor 344. For example, if bit line 300a is connected to capacitor 322 and discharged excessively, transistor 344b is turned off and thus transistor 344a is turned on,
As a result, connection point 340 initiates discharge of bit line 300a through transistor 344a. Although such a discharge at node 340 is harmless to the read amplifier 4 whose read operation is overridden by the capacitor 322, how many nodes of the read amplifier 4 do not utilize the selected row write mode. If shared by one of the amplifiers,
This discharge of node 340 prematurely sets the state of the cross-coupling negator in the amplifier prior to the stabilization of the bit line voltage (ie, as if clock signal S1 were to stabilize bit line 300). As if it started to change the connection point 340 to the ground potential). Accordingly, capacitor 322 must be dimensionally limited so that it does not change its bit line below its associated bit line precharge voltage and deeper than one threshold voltage of transistor 344. The maximum value of the capacity of the capacitor 322 is the bit line 300 and the read amplifier 4 in the memory device 1.
, And is easily calculated by one of the usual skilled arts schools.

FIG. 12 shows, in block form, the configuration of the capacitors 322 in the double constant velocity call store 1 in association with each of the arrays 2. In FIG. 12, some of the functional blocks of FIG. 1 are not shown for simplicity. Array 2 ₀ to 2 ₇
Each has an associated capacitor 322 and transistor 324 (shown in FIG. 12 as a collection by block 326) as described above for FIG. It should be noted that the single capacitor 322 and the single transistor 324 can also be shared by all of the arrays 2. Selection logic circuit 328
Receives the line FWM signal from the writemask register 54 and the color register 50, as shown in FIG.
Receives line FWD signal from. The line XDUM signal is used in the storage device 1 to generate the line DUM0 and DUM1 signals shown in FIG. 11, which are dummy capacitors at appropriate times.
Connect the selected one of 302 to its associated bitline 300. The line AX0 signal is the least significant bit of the row address and is used in connection with the data written by the selective write mode according to Table 1. Select logic circuit 328 also receives a circuit FW signal from combination logic circuit 44, which enables the select row write mode according to the state of the control inputs according to Table 1 above. Two circuits send the output from the selection logic circuit 328 to each of the arrays 2 and, if these two lines are the lines F0 and F1 shown in FIG. 11, if any of the bit lines 300a and 300b. Capacitor 322
Select for each pair of bit lines 300 in an array that attempts to connect. As is apparent from FIG. 12, the connection of capacitors 3222 can be controlled individually for each of the arrays 2, in which case the selected row write mode is inhibited according to the information stored in write mask register 54. The data state for each array 2 is controllable by the information stored in the color register 50.

Referring now to FIG. 13, the configuration and operation of the select logic circuit 328 incorporated in the memory device 1 in determining one of the pairs of bit lines 300 to which the capacitor 322 is to be connected, and the write mask. -Incorporation of write mask information from the register 54 into the selected row write mode is shown. First
The portion of the selection logic circuit 328i shown in FIG. 13 is shown in FIGS.
Shall apply in relevant part into an array 2i from sequence 2 ₀ 12 Figure to 2 _7, logic circuit 328i, of course, repeated cage 8 times with eight each sequence 2 in the storage device 1. First
The selection logic circuit 328i of FIG. 13 is thus associated with the single capacitor 322 (and thus the associated transistor 324) and in this embodiment is dedicated to one of the arrays 2.

The NAND gate 330 is a combinational logic circuit 44 shown in FIGS. 2 and 4.
Receives the line FW signal from.

Active signal on line FW the line RAS _- line W when transitions
E _-, SF, TR _- indicates that the slave connexion selected row write operation to the received data state Te Niyotsu is selected. NAND gate 330 also connects line mask from write mask register 54.
Receive WMi signal. The logic circuit of FIG.
Associated with one (ie, array 2i) and thus receives the corresponding bit i of writemask register 54. The write mask mode for prohibiting the write operation for the selected array 2 is built into the selected row write mode described herein. Of course, the application of the write mask information shown in FIG. 13 is not essential for the selected row write mode of operation, but if applied in this manner there are alternative advantages.

NAND gate 330 further receives the line XDUM signal described above at its input. In this way, the supply of the lines F0i, F1i signals occurs ad-hoc at the proper time during the store cycle. Therefore, the output of the NAND gate 330 is
The line FWMi is at a low logic value only when the line FW is enabled (ie, the selected row write mode is selected), and the line FWMi signal is at a high logic value (ie, writing is not inhibited for array 2). ), And line XDUM is at a high logic value at the proper time for this cycle.

The selection of the signal lines F0i and F1i signals for array 2 is also
This is achieved by the logic circuit of FIG. Exclusive OR gate
331 receives at its one input the lowest row address bit AX0, which bit AX0 is word circuit XWD0 or word line XWD1.
Whichever is asserted (assuming that the upper bits of the row address select one of the wordline pairs). Exclusive-OR gate 331 also receives line FWDi from color register 50. Line FWDi carries the data bits to be written in the selected row of array i. Although the data source for the selected row write mode is described herein as color register 50, it will be apparent that the data input terminal can also provide the data to be written in this mode. Since the selected row write mode is directed to clearing and filling the storage portion stored in storage device 1, it is useful to supply the same data to multiple rows within this mode. The use of the color register 50 as a source for the data to be used in the selected row write mode is suitable for such an application because it allows the user to repeatedly input the same input data through the data terminals D0 to D7.
This is because it is possible to avoid supplying to.

The output of the exclusive-OR gate 331 is connected to the input of the NOR gate 332 and via the NOT circuit 333 to the input of the NOR gate 334. NOR gate 332 is NA on its remaining inputs
Receive the output of the ND gate 330, and use your own output to connect to line F
Drive 0i. Similarly, NOR gate 334 receives the output of NAND gate 330 at its remaining inputs and drives line F1i with its output. When the output of NAND gate 330 is at a high logic value, the outputs of NOR gates 332 and 334 do not meet the condition and take a low logic value, so the output of NAND gate 330 thus acts as a usable signal. During the unmasked selected row write operation, the output of NAND gate 330 is at a low logic value so that exclusive OR gate 33 performs the selection described in Table 2 above.
In response to an output of 1, the output of either NOR gate 332 or NOR gate 334 will take a high logic value. Either line F0i or F1i is driven to its high logic value depending on the input data and row selection, connecting capacitor 322 to bit line 300a or 300b as necessary to achieve the desired operation.

Referring to FIG. 14 in conjunction with FIGS. 11 and 11a, the timing of operation of the selected row write function for array 2 of storage device 1 is shown. At time t ₀ , memory device 1 is in the precharge portion of the memory cycle (following the preceding active cycle). The clock signal T is at a high logic value and therefore the bit lines 300a and 300b are connected to the read connection points 301a and 301b of the read amplifier 4. At this time, the bit line 300 is about 1/2 Vdd by the read amplifier 4.
It is being precharged up to Vbit. Read connection point 301a
And 301b (representing the voltage on these corresponding bit lines 300a and 300b while the clock signal T is at a high logic value) is shown at line 14 at line _V301 . At this time, the capacitor 322 is being precharged to the voltage Vss, and the dummy capacitors 302a and 302b have Vref (about 1).
/ 3Vdd) is being precharged.

Following a time t _0, the line RAS _-, performs transition from a high to a low logic value at the beginning of the next active cycle. For the purposes of this example in FIG. 14, assume that the selected row write mode is being selected and that a logic "0" state is to be written into the storage capacitor 306a of FIG. At some time (as shown as time t _{1 in} FIG. 14) after the row address has been latched and decrypted by the X-decoder 18, the logical "0" state is stored (in the even-encrypted row). Written to capacitor 306a, line F0 will be driven to a high logic value by select logic circuit 328 (for Array 2 considered). This causes transistor 320a to connect capacitor 322 to bit line 300a, as described above. Also, at about this time, the line
DUM1 is driven to a high logic value, resulting in a dummy transfer gate
304b connects dummy capacitor 302b to bit line 300b and line XWD0 is driven to a high logic value so that transfer gate 308a connects storage capacitor 306a to bit line 300a. Conversely, lines XWD1 and DUM0 are held low and
Storage capacitor 306b and dummy capacitor 302a are isolated from bit lines 300b and 300a, respectively. By connecting the dummy capacitor 302b to the bit line 300b, the voltage on the bit line 300b is reduced by a small amount at this time, which is less than the voltage at which the dummy capacitor 302b charges the bit line 300b. This is because it is charged with a low electric love. Since the capacitor 322 is connected to the bit line 300b, the capacitor 322 draws electric charge from the bit line 300a and the storage capacitor 306a, and accordingly, after the time t ₁ , the voltage of the bit line 300a is higher than that of the bit line 300b. Pull it low. This means that the voltage at the read connection point 301a after the time t ₁ in FIG.
It is shown by being below the voltage of 1b.

Note that word lines XWD0, XWD1 and dummy word lines
This means that it is preferable to flexibly connect the capacitor 322 to the bit line 300a or 300b before the time when DUM0 and DUM1 are activated. Since bit line 300 is precharged to store a substantial charge, capacitor 322 is connected to its associated bit line 300 early prior to connecting storage capacitor 306a or dummy capacitor 302 to this line. By doing so, this line can be pulled down to a low voltage. Such early connection can minimize the noise effects caused by the connection of multiple capacitive elements to the bit line 300. However, it is only necessary to connect capacitor 322 to bit line 300a (in this example) for a sufficient time to discharge bit line 300a to a stable voltage prior to amplification of the differential voltage by read amplifier 4. .

In time t _2, the clock signal S1 becomes active state, to start the amplification stage of a cycle. U.S. Pat.
As described in US Pat. No. 377, activation of transistor 310 by clock signal S1 causes transistor 310 to have a relatively high impedance relative to its parallel transistor 318.
Is turned on to slowly start the separation between the voltage at the read connection point 301a and the voltage at 301b by the cross coupling negation circuit. Following separation of the voltages at these read connection points, the clock signal T transitions to a low logic value, causing the transistors 319a and
By turning off 319b, the bit line 300a and
Isolate the capacitive load of 300b (as well as capacitor 322) from amplifying operations. Clock signal S2 is then at time t ₃ goes to a high logic value, rapidly changing to a ground potential connection points 340, also bit lines 300a and 300b are read connection point 301a
And promptly complete the amplification process during the time decoupled from 301b.

Voltage difference between read connection points 310a and 310b (read connection circle 301a
Voltage is near Vss and the voltage at connection point 301b is near Vdd)
After the time when is amplified, the read operation is complete and no further assistance from dummy capacitor 302b is needed, so the dummy word circuit DUM1 signal goes to a low logic value. The line XDUM signal has transitioned to a low logic value by this time and line F0
(And line DUM1) is deactivated so that the restoration of the storage capacitor 306a is not loaded by the capacitor 322. The restore operation is initiated by a clock signal transitioning to a high logic value, turning on transistors 319a and 319b, which results in the amplified voltage at read nodes 301a and 301b being applied to bit lines 300a and 300b. Case) The storage capacitor 306a is charged to the "0" state. As shown in FIG. 14, at time t ₄ , the word line XWD0 and the clock signal T are boosted to a voltage higher than Vdd by a well-known technique, so that the "1" state is being written. If present, transfer gate 304a and transistor
There will be no threshold voltage drop across 319a. However, since the capacitor 322 discharges the bit line 300a to a low potential during the read cycle, the "0" state is "restored" to the storage capacitor 306a by the read amplifier 4 at this time. The memory sylk is signal S1,
Termination with deactivation of S2 and line XWD0, after which precharge and equalization operations begin.

The selected row write mode described here is shown in FIGS.
It is the most appropriate alternative to the block writing aspects described with respect to the figures above, and any of these aspects can be used to fully perform the clear and charge operations when the storage device 1 is utilized for image storage. However, these two aspects do not necessarily have to be mutually exclusive, and both can be incorporated in the same storage device 1 if desired.

Although the present invention has been described with reference to specific embodiments,
It is obvious that the present invention has been made merely by way of example and is not intended to be construed in a limiting sense. Numerous changes in the details of this specific embodiment and additional embodiments of the invention will be apparent to and can be made by those skilled in the art upon reference to this description.
It is also clear. Furthermore, it will be apparent to one of ordinary skill in the art that the present and future equivalent components to the components described herein can be easily replaced to achieve the same result as this specific embodiment. It is therefore believed that such changes, substitutions and additions are within the spirit and scope of the invention as defined by the appended claims.

The following items are further disclosed with respect to the above description.

(1) Rows, an array of memory cells arranged in rows, a row decoder for receiving a row address signal and selecting a row of the memory cells in response to the row address signal, and a plurality of bit lines Of the plurality of read lines, each bit line being associated with a column of storage cells and each storage cell in the selected row being connected to the bit line associated with the column; A plurality of read amplifiers, each read amplifier being associated with one of the bit lines, the read amplifier comparing the voltage at the reference node with the voltage of the bit line associated with the read amplifier; Regardless of the data state stored by the storage cell in the selected row in the column associated with the amplifier, the capacitor is available for comparison by the associated read amplifier. A read / write storage device comprising a connection device responsive to a data signal for connecting the capacitor to the bit line so as to have a defined result.

(2) In the read / write storage device according to item 1, the capacitor can be connected to each bit line of the plurality of bit lines, and the connection device is connected to the storage cell in the selected row. Read / write storage, characterized in that the capacitor is connected to the plurality of bit lines so that the capacitor has a predetermined result for comparison by the associated read amplifier regardless of the stored data state. apparatus.

(3) In the read / write memory device according to the item (2), each read amplifier restores the comparison result of the amplifier in the memory cell connected to the bit line associated with the amplifier. Read / write storage device.

(4) In the read / write memory device according to the item (2), in the connection device, each transistor of the first plurality of transistors is connected between the first electrode plate of the capacitor and the bit line associated with the transistor. A first plurality of transistors having a source-drain path and a gate, and connecting the bit line associated with the transistors to the first plate of the capacitor in response to the data signal. And a selection logic circuit for driving the gates of the first plurality of transistors.

(5) In the read / write memory device according to the fourth aspect, the connection device is configured such that each transistor of the second plurality of transistors has the first electrode plate of the capacitor and the reference connection of the read amplifier associated with the transistor. Further comprising a second plurality of transistors having a source-drain passage connected to a point and having a gate, wherein the selection logic circuit is also connected to the gates of the second plurality of transistors. A gate of the first plurality of transistors or the first electrode plate of the capacitor for connecting the bit line associated with the first plurality of transistors to the first electrode plate of the capacitor in response to the data signal. To the gate of the second plurality of transistors to connect the reference connection point associated with the transistor to the second plurality. The read / write storage device, characterized in that any one of them is driven.

(6) The read / write storage device according to claim 5, further comprising a mode selection device that receives a mode control signal indicating a normal operation of the storage device, and the selection logic circuit in the storage device operates normally. Reading in response to the mode control signal indicating that the first electrode plate of the capacitor is not connected to the bit line or the reference connection point. Storage device.

(7) The read / write storage device according to the sixth aspect, further comprising a data register that stores the data signal so that the data signal is supplied to a plurality of rows selected by a subsequent row address signal. The read / write storage device comprising:

(8) The read / write storage device according to claim 1, further comprising a device for precharging the capacitor to a predetermined voltage before the connection device connects the capacitor to the bit line. Read / write storage device.

(9) The read / write storage device according to item 2, further comprising a device for precharging the capacitor to a predetermined voltage before the connection device connects the capacitor to the bit line. Read / write storage device.

(10) An array of memory cells arranged in rows and columns, a row decoder that receives a row address signal and selects a row of the memory cells in response to the row address signal, and a plurality of bit line pairs A plurality of bit lines in which a bit line pair is associated with a column of the storage cells and the storage cells in each column in a selected row are connected to one of the bit line pairs; A plurality of dummy capacitors each of which is connectable to the bit line for storing a reference charge; and each read amplifier of the plurality of read amplifiers includes the bit line. Associated with one of the pairs, the read amplifier compares the voltage on the bit line to which the storage cell in the selected row is connected to the voltage on the partner bit line in the bit pair. The partner bit line is connected to the associated dummy capacitor, the plurality of read amplifiers, the capacitor, and the capacitor regardless of the data state stored by the storage cells in the selected row. A connection device responsive to a data signal for connecting the capacitor to any of the bit lines in the bit line pair so that each read amplifier provides a predetermined result for comparison. Read / write storage device.

(11) In the read / write memory device according to item 10, each read amplifier restores the comparison result of the amplifier in the memory cell in the selected row connected to the bit line associated with the amplifier. The read / write storage device.

(12) In the read / write storage device according to item 10, the connection device, for each bit line pair, between the first electrode plate of the capacitor and the first bit line of the bit line pair. A first transistor having a source-drain path connected thereto, and a second transistor having a source-drain path connected between a first electrode of the capacitor and a second bit line of the bit line pair. The connection device further includes a selection logic circuit that drives either the gate of the first transistor or the gate of the second transistor in response to the data signal for each bit line pair. The read / write storage device.

(13) In the read / write storage device according to the twelfth item, the columns are grouped into predetermined groups, and the connection device includes mask data corresponding to each group of the columns and the capacitors. Further comprising a mask register for storing the mask data indicating whether or not should be connected to the bit line in the group, the selection logic circuit being connected to the mask register and the capacitor. The gate of the first transistor associated with the group is also responsive to the mask data indicating for each group that is not to be connected to the bit lines in one of the groups. The read / write storage device, characterized in that the gate is also not driven.

(14) The read / write storage device of claim 13, wherein each of the plurality of capacitors includes each of the plurality of capacitors associated with one of the groups of the column. The read / write storage device.

(15) The read / write storage device according to claim 10, further comprising: a mode selection device that receives a mode control signal indicating a normal operation of the storage device, wherein the connection device is normally operated. The read / write storage device is responsive to the mode control signal indicating that the capacitor is responsive to the mode selection device so that the capacitor is not connected to any of the bit lines.

(16) The read / write storage device according to item 10, wherein the column is grouped into a predetermined group, and the storage device has each of a plurality of capacitors of the group of the column. The read / write storage device including the plurality of capacitors associated with one of the storage devices.

(17) The read / write storage device according to item 16, wherein the input data register stores input data corresponding to each group of the column, and the input data is a bit line pair in the group. The input data register for indicating whether or not the first electrode plate of the capacitor should be connected to the first bit line or the second bit line, and the selection logic in the storage device. A circuit is connected to said input data register and is responsive to input data associated with said group stored in said input data register for each said bit line pair associated with said one group. The gate or the second
The storage device is characterized in that any one of the gates of the transistors is driven.

(18) In the read / write storage device according to item 17, the connection device is a mask register for storing mask data corresponding to each group of the column, and the mask data is the group of each capacitor of the mask data. A bit line in the group, the mask logic register indicating whether or not to connect to the bit line in the group, and the select logic circuit being connected to the mask register and the capacitor being in one of the groups. Neither drive the gate of the first transistor nor the gate of the second transistor associated with the one group in response to the mask data indicating for each group that it should not be connected to The read / write storage device.

(19) In the read / write storage device according to item 10, the bit line is precharged to a first predetermined voltage, and the capacitor is precharged to a voltage different from the first predetermined voltage. The read / write storage device.

(20) In a read / write memory device of the type having an array of memory cells arranged in rows and columns, if the memory cells are in a selected row of the array, the memory cells direct the memory cells to a bit line. A read circuit used in the storage device including a capacitor to be connected and a transfer gate, comprising:
A first bit line associated with a first plurality of storage cells in one column, a second plurality of bit lines in the column, and one storage cell of the second plurality of storage cells is selected. A dummy cell associated with the first bit line and a dummy transfer gate for connecting the dummy capacitor to the first bit line; A second dummy cell associated with the second bit line, the dummy capacitor and a dummy transfer gate for connecting a dummy capacitor to the second bit line when one of the storage cells is selected. A read amplifier for reading the polarity of the difference voltage between the first bit line and the second bit line, a capacitor, and a first electrode plate of the capacitor and the first bit line. It continued by source - has a drain passage and the first to have a gate for receiving a first data signal
A select transistor and a second select transistor having a source-drain path connected between the first electrode plate of the capacitor and the second bit line and having a gate for receiving a second data signal. In the read circuit, the capacitor is connected to one of the bit lines by the first selection transistor or the second selection transistor.
The read circuit is sized to set the polarity of the differential voltage between the bit line and the second bit line.

(21) The read / write circuit according to claim 20, having a source-drain path connected between the first electrode plate of the capacitor and a predetermined voltage, and having a gate for receiving a precharge signal. The readout circuit further comprising a precharge transistor.

(22) The read circuit according to the twenty-first aspect, wherein the capacitor and the precharge transistor are shared by a plurality of the read circuits in the storage device.

(23) In the read circuit according to the twenty-first item, the predetermined voltage is a ground potential.

(24) In a memory device of the type having memory cells arranged in rows and columns and a plurality of read amplifiers, if the memory cells are in the selected row of the array, the memory cells are the first bit. A second line connected to the line, each said read amplifier being associated with said one column of said array and connected with one of said first bit lines and a dummy capacitor.
A method of writing data into the storage cells in the selected row of the storage device for reading a voltage difference between a bit line and the data line, the data indicating a data state to be written in the storage cells in the row. A step of receiving a signal, a step of connecting a plurality of storage cells in the selected row of the array to the first bit line corresponding to the storage cells for reading by the read amplifier, and the data signal received. Of each bit line of the first bit lines associated with the plurality of memory cells or of the second bit line read by the read amplifier associated with the plurality of memory cells. A step of connecting a capacitor to any of the bit lines and the first bit for each memory cell of the previous memory cells in the selected row. And a step of reading the voltage difference between the line and the second bit line, and restoring the voltage corresponding to the read voltage difference in the memory cells connected to the plurality of memory cells in the selected row. And a writing step.

(25) In the write method described in the paragraph 24, the step of connecting the capacitor is executed before the step of connecting the plurality of storage cells in the selected row to the corresponding first bit line. The writing method characterized by the above.

(26) The writing method according to the paragraph 24, wherein a single capacitor is shared by the plurality of storage cells in the selected row, and the writing method is performed before the step of connecting the capacitors. The writing method, further comprising precharging the capacitor to a predetermined voltage.

(27) The writing method according to paragraph 24, wherein the columns in the array are arranged in groups, and the writing method indicates which group of the columns in the array should not be written. The writing method further comprising receiving a mask signal and inhibiting a step of connecting the capacitor to a selected group of the columns in the array in response to the mask signal.

(28) The write method according to claim 27, wherein the single capacitor is shared by the plurality of storage cells in the selected row in the same group of the column. .

(29) A read / write memory device having the ability to write the same data to multiple memory cells in a selected row in a single cycle is disclosed. The present invention uses the bit line 30 received by each read amplifier 4 to override the read operation.
It is built in the storage device by a capacitor 322 that sets the polarity of the read differential voltage to a predetermined state by being selectively connected to one of 0. The restore operation of the read amplifier 4 restores the read data state in the selected memory cell 306, thus completing writing. The capacitor 32
2 can be connected to many bit lines for design efficiency. Each of the capacitors 322 has sufficient capacitance to completely discharge the charge of the dummy capacitor 302 which is applied to the stored "1" state for each bit line to which it is connected. . Logic circuits are included in the memory device for receiving the data state to be written and for receiving the low bit of the row address. The logic circuit connects the capacitor 322 to a bit line to which a memory cell is connected to write a "0" state (the capacitor is precharged to ground potential) and a dummy to write a "1" state. .Bit lines to which cells are connected
The capacitor 322 is connected to 300. In the case of multiple read / write storage, a write mask is included to inhibit writing by the capacitor for each selected array of storage. A data input register is also provided to store the data written during the multiple write cycle.

[Brief description of drawings]

1 is a schematic block diagram of a preferred embodiment of a dual port storage device constructed in accordance with the present invention, and FIG. 2 is a schematic block diagram of the special function logic circuit of the dual port storage device of FIG. 3a and 3b are schematic diagrams of a clock signal generating circuit used by the special function logic circuit of FIG. 2, and FIG. 4 is a combination in the special function logic circuit of FIG. A schematic diagram of a logic circuit, FIG. 5a is a timing diagram of a storage cycle when the write register according to the invention is loaded during the early part of its storage cycle, and FIG. 5b is a storage cycle of the write register according to the invention. The timing diagram of the storage cycle when loading either the write register or the color register during the latter part of the drawing, FIG. 5c shows the contents of the write register loaded in the preceding cycle in the storage device of the invention. 5d is a timing diagram of a memory cycle in which the contents of the write register are ignored without destroying the contents of the write register according to the present invention, and FIG. 6 is a mask write operation according to the present invention. FIG. 7 is a schematic diagram of a column decoder including the addition of the block write feature of the memory device of FIG. 1, FIG. 8 uses the circuit of FIG. A timing diagram of the operation of a block write cycle, FIG. 9 is a register scale diagram for explaining a block write cycle using the circuit of FIG. 7, and FIG. 10 is a precedent in which the present invention is effectively incorporated. A block type electric circuit diagram of a double buffer display device constructed by the technology, FIG. 11 is a schematic circuit diagram of a circuit in a memory device incorporating the selective writing mode of the present invention, and FIG. 11a is a typical circuit diagram. Read FIG. 12 is a block-type electric circuit diagram of the circuit of FIG. 11 incorporated in a memory device utilizing the selective writing mode of the present invention. FIG. 13 is a selection circuit diagram of the present invention. FIG. 6 is a schematic electric circuit diagram of the logic circuit for selecting a data state to be written in a row writing mode. FIG. 14 is a timing diagram illustrating the operation of the selected row write mode of the present invention. [Description of Symbols] 1: Dual-port storage device 2: Array 4: Read amplifier bank or read amplifier 6: Transfer gate 8: Data register 10: Pointer 12: Serial input / output buffer storage device 14: Serial logic circuit 16 : RAM logic circuit 18; X decoder 20: Y decoder 22: Torg counter / detector 24: Input / output buffer memory device 26: Multiple conversion device 30: Special function logic circuit 31: Output drive circuit 34: Write mask register D0 to D7: data terminal SD0-SD7: input and output terminals A0 - A8: address terminals SF: function signal line WE _-: write enable signal line TR _-: transfer enable signal RAS _-: clock signal line CAS _-: clock Signal line CAS: Address / Strobe signal line SCLK: Clock signal line SOE: Serial output usable signal line 26: Multiplexing converter 34, 36, 38, 40, 42: Latch 44: Combination logic circuit 50: Color register 54: Write mask register 58,60: Multiplexing converter 200: Predecoder 204: Column selection Circuit 210: 4-−1 decoder 300: Bit line 301: Read connection point 302: Dummy capacitor 304: Dummy transfer gate 306: Storage capacitor 308: Transfer gate 312: Dummy precharge transistor 322: (For writing selected row) ) Capacitor 324: Capacitor precharge transistor 328: Selection logic circuit 326: Selection row writing block 344,346: Cross-coupling NOT circuit transistor

Claims (3)

[Claims] 1. An array of storage cells arranged in rows and columns, a row decoder for receiving a row address signal and selecting a row of the storage cells in response to the row address signal, and a plurality of bit lines. A plurality of bit lines, each bit line of which is associated with a column of storage cells and each storage cell in the selected row is connected to the bit line associated with the column; A plurality of read amplifiers, each read amplifier of which is associated with one of the bit lines, the read amplifier comparing a voltage at a reference node with a voltage of a bit line associated with the read amplifiers;
A capacitor and the capacitor so that the capacitor has a predetermined result for comparison by the associated read amplifier regardless of the data state stored by the storage cell in the selected row in the column associated with the read amplifier. And a connection device responsive to a data signal for connecting a capacitor to the bit line. 2. An array of memory cells arranged in rows and columns, a row decoder for receiving a row address signal and selecting a row of the memory cells in response to the row address signal, and a plurality of bit line pairs. Each bit line pair of is associated with a column of storage cells, and the storage cells in each column in a selected row are connected to one of the bit line pairs. A plurality of dummy capacitors each of which is connectable to the bit line for storing a reference charge, and each of the read amplifiers of the plurality of read amplifiers, In connection with one of the bit line pairs, the read amplifier sets the voltage of the bit line to which the storage cell in the selected row is connected to the voltage of the other bit line in the bit pair. In comparison, the counterpart bit line is connected to the associated dummy capacitor, the plurality of read amplifiers, a capacitor, and the capacitor regardless of the data state stored by the storage cells in the selected row. Includes a connection device responsive to a data signal for connecting the capacitor to any of the bit lines in the bit line pair so that the comparison by each read amplifier has a predetermined result. Read / write storage device. 3. A storage device of the type having storage cells arranged in rows and columns, and a plurality of read amplifiers, wherein said storage cells are of a first row if said storage cells are in said selected row of said array. Connected to a 1-bit line, each said read-amplifier reading the difference voltage associated with said one column of said array and between one of said first bit-lines and a second bit-line to which a dummy capacitor is connected. A method of writing data into the storage cells in the selected row of the storage device, the method comprising: receiving a data signal indicating a data state to be written in the storage cells in the row; Connecting a plurality of storage cells in the selected row of the array to the first bit line corresponding to the storage cells for reading; Of each bit line of the first bit lines associated with the plurality of storage cells depending on the data signal or of the second bit lines read by the read amplifier associated with the plurality of storage cells. Connecting a capacitor to any of the bit lines of, and a difference voltage between the first bit line and the second bit line for each memory cell of the previous memory cells in the selected row. And reading the voltage corresponding to the read difference voltage in the memory cells connected to the plurality of memory cells in the selected row. Method.