JPH066832A - Picture processing unit with real time fault diagnostic function - Google Patents

Picture processing unit with real time fault diagnostic function

Info

Publication number
JPH066832A
JPH066832A JP18437592A JP18437592A JPH066832A JP H066832 A JPH066832 A JP H066832A JP 18437592 A JP18437592 A JP 18437592A JP 18437592 A JP18437592 A JP 18437592A JP H066832 A JPH066832 A JP H066832A
Authority
JP
Japan
Prior art keywords
test signal
signal
microcomputer
processing
high speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18437592A
Other languages
Japanese (ja)
Inventor
Hiroyuki Nishikawa
博幸 西川
Kazuhiro Tanabe
一宏 田辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP18437592A priority Critical patent/JPH066832A/en
Publication of JPH066832A publication Critical patent/JPH066832A/en
Pending legal-status Critical Current

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  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

PURPOSE:To attain various kinds of fault diagnosis for a picture processing unit in real time even with a microcomputer whose processing speed is slow. CONSTITUTION:A picture processing unit 1 processing a video signal is provided with a means 3 generating a prescribed test signal changing at a high speed corresponding to a picture element (several tens ns period) in place of a video signal for a blanking period, a signal fetch means 5 collecting a test signal processing output as the result of processing the test signal at the picture processing unit 1 at a high speed corresponding to the picture element (several tens ns period) and storing the signal to a storage means 6, the storage means 6 accessible independently of both the signal fetch means 5 and a microcomputer 7 and the microcomputer 7 fetching properly the content of the stored test signal processing output, analyzing it and implementing fault diagnosis.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、テレビジョンカメラ装
置等の画像処理装置の故障診断に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure diagnosis of an image processing device such as a television camera device.

【0002】[0002]

【従来の技術】図2に従来のマイクロコンピュータを使
用した故障診断機能を持つ画像処理装置の概略構成図を
示し、従来の故障診断方式の説明を行う。テレビジョン
カメラ装置等の映像信号は、内蔵の画像処理装置1で各
種の信号処理がなされるが、このテレビジョンカメラ装
置等の画像処理装置の故障診断を行う場合、映像信号の
ブランキング期間(通常、垂直ブランキング期間)に、
テスト信号発生回路3’から時変化のないパルス状のテ
スト信号2’を画像処理装置1に入力する。そして、ブ
ランキング期間に挿入されたこのテスト信号2’に対
し、画像処理装置1で処理された結果のテスト信号処理
出力4’をマイクロコンピュータ7に取り込み、その内
容を解析することで、リアルタイムで画像処理装置1の
故障診断を行う。
2. Description of the Related Art FIG. 2 shows a schematic configuration diagram of an image processing apparatus having a conventional failure diagnosis function using a microcomputer, and a conventional failure diagnosis method will be described. A video signal of a television camera device or the like is subjected to various kinds of signal processing by the built-in image processing device 1. However, when a failure diagnosis of the image processing device such as the television camera device is performed, a blanking period of the video signal ( Usually in the vertical blanking period),
A pulse-shaped test signal 2 ′ that does not change with time is input to the image processing apparatus 1 from the test signal generation circuit 3 ′. Then, with respect to the test signal 2'inserted in the blanking period, the test signal processing output 4'resulted from the image processing device 1 is fetched into the microcomputer 7 and the content thereof is analyzed to realize in real time. The failure diagnosis of the image processing apparatus 1 is performed.

【0003】[0003]

【発明が解決しようとする課題】前述の従来技術では、
ブランキング期間毎に発生するテスト信号処理出力4’
がそのままマイクロコンピュータ7に取り込まれるが、
マイクロコンピュータ7におけるテスト信号処理出力
4’のデータ採集はマイクロコンピュータ7のマシンサ
イクルに依存するため、実際には数μs周期程度でしか
データ採集が出来ない。これに対し、映像信号の水平走
査期間はNTSC方式の場合で約64μsであり、この
間の映像信号は画素対応で約70nsと高速に変化する
ため、このように処理速度の遅いマイクロコンピュータ
7で直接データの採集を行う従来の方法では、時変化の
ないパルス状のテスト信号にて故障診断ができるホワイ
トバランス調整等、レベル系のごく一部の故障診断が限
界であり、画素対応で高速に変化する信号により、リア
ルタイムに画像処理装置1の各種故障診断を正確に行う
ことは出来ない。本発明はこれらの欠点を除去し、処理
速度の遅いマイクロコンピュータでも、リアルタイムで
の画像処理装置の各種故障診断を可能とすることを目的
とする。
In the above-mentioned prior art,
Test signal processing output 4'generated every blanking period
Is taken into the microcomputer 7 as it is,
Since the data collection of the test signal processing output 4'in the microcomputer 7 depends on the machine cycle of the microcomputer 7, the data collection is actually possible only in the period of several μs. On the other hand, the horizontal scanning period of the video signal is about 64 μs in the case of the NTSC system, and the video signal during this period changes at a high speed of about 70 ns for each pixel, and thus the microcomputer 7 having a slow processing speed directly In the conventional method of collecting data, only a part of the level system's failure diagnosis, such as white balance adjustment that allows failure diagnosis with a pulse-shaped test signal that does not change over time, is the limit, and it changes at high speed with pixel correspondence. The failure signal of the image processing apparatus 1 cannot be accurately diagnosed in real time by the signal. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate these drawbacks and enable various failure diagnosis of an image processing apparatus in real time even with a microcomputer having a slow processing speed.

【0004】[0004]

【課題を解決するための手段】本発明は上記の目的を達
成するため、映像信号の処理をする画像処理装置におい
て、ブランキング期間に画素対応(数十ns周期)で高
速に変化する所定のテスト信号を発生する手段と、該テ
スト信号が上記画像処理装置で処理された結果のテスト
信号処理出力を画素対応(数十ns周期)で高速に採集
して取り込み記憶手段に記憶させる信号取り込み手段
と、該信号取り込み手段とマイクロコンピュータの双方
から独立にアクセス可能な上記記憶手段と、この記憶し
たテスト信号処理出力内容を適宜取り込み解析して故障
診断を行う上記マイクロコンピュータとを有する構成と
したものである。
In order to achieve the above object, the present invention provides an image processing apparatus for processing a video signal, wherein a predetermined change is made at high speed in correspondence with pixels (several tens of ns cycle) during a blanking period. A means for generating a test signal, and a signal fetching means for fastly collecting the test signal processing output of the result obtained by processing the test signal by the image processing device for each pixel (several tens ns cycle) and storing it in the fetching storage means. And a storage means that can be independently accessed from both the signal capturing means and the microcomputer, and the microcomputer that appropriately captures and analyzes the stored test signal processing output content to perform failure diagnosis. Is.

【0005】[0005]

【作用】その結果、画素対応(数十ns周期)で高速に
変化するテスト信号処理出力を、記憶手段に画素対応
(数十ns周期)で高速にデータ採集・記憶出来るた
め、マイクロコンピュータでは、このデータを所望時に
マイクロコンピュータのマシンサイクルで取り込み、マ
イクロコンピュータの処理速度に応じて適宜、故障診断
の解析を行うことが出来、処理速度の遅いマイクロコン
ピュータでもリアルタイムで画像処理装置の故障診断が
可能となる。
As a result, the test signal processing output that changes at high speed in correspondence with pixels (several tens of ns cycle) can be collected and stored in the storage means at high speed in correspondence with pixels (several tens ns cycle). This data can be taken in the machine cycle of the microcomputer when desired, and failure diagnosis can be analyzed appropriately according to the processing speed of the microcomputer. Even a microcomputer with a slow processing speed can perform failure diagnosis of the image processing device in real time. Becomes

【0006】[0006]

【実施例】以下、本発明の一実施例を図1に示し、その
内容を詳細に説明する。1は画像処理装置で、画像デー
タの各種演算処理を行う装置である。3はテスト信号発
生回路で、映像信号のブランキング期間(ここでは、垂
直ブランキング期間)に、画像処理装置1に故障診断用
の画素対応(数十ns周期)で高速に変化するテスト信
号2を発生・入力する回路である。4はテスト信号処理
出力で、画像処理装置1がテスト信号2に対し処理した
結果の出力信号である。5は信号読み取り回路で、テス
ト信号処理出力4を画素対応(数十ns周期)で高速に
採集し、共有メモリ6に記憶する回路である。6は共有
メモリで、図3に示すように信号読み取り回路5とマイ
クロコンピュータ7の双方から独立にメモリセル9にデ
ータの書き込み及び読み出しが可能な2つのポート8,
10を有するメモリである。7はマイクロコンピュータ
で、共有メモリ6の記憶データの内容から故障診断の解
析を行うものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is shown in FIG. 1 and its contents will be described in detail below. An image processing apparatus 1 is an apparatus for performing various arithmetic processing of image data. A test signal generation circuit 3 is a test signal 2 which changes at high speed in the blanking period of the video signal (vertical blanking period in this case) corresponding to the pixel for failure diagnosis (several tens of ns cycle) in the image processing apparatus 1. Is a circuit that generates and inputs. Reference numeral 4 denotes a test signal processing output, which is an output signal obtained by processing the test signal 2 by the image processing apparatus 1. Reference numeral 5 denotes a signal reading circuit, which is a circuit for collecting the test signal processing output 4 at a high speed for each pixel (several tens of ns) and storing it in the shared memory 6. Reference numeral 6 denotes a shared memory, and as shown in FIG. 3, two ports 8 capable of writing and reading data to and from the memory cell 9 independently from both the signal reading circuit 5 and the microcomputer 7.
A memory having 10. A microcomputer 7 analyzes the failure diagnosis from the contents of the data stored in the shared memory 6.

【0007】以下この動作を説明すると、テスト信号発
生回路3に画像処理装置1を接続し、ブランキング期間
に映像信号のかわりに画素対応(数十ns周期)で高速
に変化する所定のテスト信号2を発生させ画像処理装置
1に入力する。そのテスト信号2に対し画像処理装置1
で処理された結果のテスト信号処理出力4を、信号取り
込み回路5が画素対応(数十ns周期)で高速に採集し
て共有メモリ6に記憶する。そして、共有メモリ6に記
憶されたデータを、マイクロコンピュータ7がそのマシ
ンサイクルで取り込み、そのデータを解析し、各種故障
診断を行う。
This operation will be described below. The image processing apparatus 1 is connected to the test signal generating circuit 3 and a predetermined test signal that changes at high speed corresponding to pixels (several tens of ns cycle) instead of the video signal during the blanking period. 2 is generated and input to the image processing apparatus 1. The image processing apparatus 1 for the test signal 2
The signal processing circuit 5 collects the test signal processing output 4 obtained as a result of (1) at high speed for each pixel (several tens ns cycle) and stores it in the shared memory 6. Then, the microcomputer 7 takes in the data stored in the shared memory 6 in the machine cycle, analyzes the data, and makes various failure diagnoses.

【0008】以上のように、画素対応(数十ns周期)
で高速に変化するテスト信号処理出力4を、画素対応
(数十ns周期)で高速にデータ採集・記憶の出来る信
号取り込み回路5と、双方から独立にデータの書き込み
及び読み出しが可能な2つのポート8,10を有する共
有メモリ6を用いることによって、共有メモリ6に画素
対応(数十ns周期)で高速にデータ採集・記憶出来る
ため、マイクロコンピュータ7では、このデータを所望
時にマイクロコンピュータ7のマシンサイクルで取り込
み、マイクロコンピュータ7の処理速度に応じて適宜、
故障診断の解析を行うことが出来、処理速度の遅いマイ
クロコンピュータ7でもリアルタイムで画像処理装置1
の故障診断が可能となる。
As described above, pixel correspondence (several tens of ns cycle)
The test signal processing output 4 that changes at high speed with a signal, the signal acquisition circuit 5 that can collect and store the data at high speed in correspondence with the pixel (several tens of ns cycle), and the two ports that can write and read data independently from both By using the shared memory 6 having 8 and 10, data can be collected and stored in the shared memory 6 at a high speed with a pixel correspondence (several tens of ns cycle). Captured in cycles, depending on the processing speed of the microcomputer 7,
A failure diagnosis analysis can be performed, and even the microcomputer 7 having a slow processing speed can perform image processing in real time.
It is possible to diagnose the failure.

【0009】[0009]

【発明の効果】本発明によれば、画素対応(数十ns周
期)で高速に変化するテスト信号処理出力を、共有メモ
リに画素対応(数十ns周期)で高速にデータ採集・記
憶出来るため、マイクロコンピュータでは、このデータ
を所望時にこのマシンサイクルで取り込み、この処理速
度に応じて故障診断の解析を行うことが出来、処理速度
の遅いマイクロコンピュータでもリアルタイムで画像処
理装置の故障診断が可能となり、大事故の予測、事故発
生時の迅速かつ適切な処理に多大な効果を発揮する。
According to the present invention, it is possible to collect and store a test signal processing output which changes at high speed in correspondence with pixels (several tens of ns) in a shared memory at high speed in correspondence with pixels (several tens of ns). In a microcomputer, this data can be taken in this machine cycle at a desired time, and a failure diagnosis can be analyzed according to this processing speed, and even a microcomputer with a slow processing speed can perform failure diagnosis of an image processing device in real time. It is very effective in predicting a major accident and in swift and appropriate processing when an accident occurs.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の全体構成を示すブロック図。FIG. 1 is a block diagram showing the overall configuration of the present invention.

【図2】従来例の構成を示すブロック図。FIG. 2 is a block diagram showing a configuration of a conventional example.

【図3】共有メモリの構成を示すブロック図。FIG. 3 is a block diagram showing the configuration of a shared memory.

【符号の説明】[Explanation of symbols]

1 画像処理装置、2 テスト信号入力、3 テスト信
号発生回路、4 テスト信号処理出力、5 信号取り込
み回路、6 共有メモリ、7 マイクロコンピュータ。
1 image processing device, 2 test signal input, 3 test signal generation circuit, 4 test signal processing output, 5 signal acquisition circuit, 6 shared memory, 7 microcomputer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 映像信号の処理をする画像処理装置にお
いて、ブランキング期間に画素対応(数十ns周期)で
高速に変化する所定のテスト信号を発生する手段と、該
テスト信号が上記画像処理装置で処理された結果のテス
ト信号処理出力を画素対応(数十ns周期)で高速に採
集して取り込み記憶手段に記憶させる信号取り込み手段
と、該信号取り込み手段とマイクロコンピュータの双方
から独立にアクセス可能な上記記憶手段と、この記憶し
たテスト信号処理出力内容を適宜取り込み解析して故障
診断を行う上記マイクロコンピュータとを有することを
特徴とするリアルタイム故障診断機能付き画像処理装
置。
1. In an image processing device for processing a video signal, a means for generating a predetermined test signal that changes at high speed corresponding to a pixel (several tens of ns period) during a blanking period, and the test signal is used for the image processing. A signal fetching unit that collects a test signal processing output as a result of processing by the device at a high speed for each pixel (several tens of ns cycle) and stores it in a storing unit, and an independent access from both the signal fetching unit and the microcomputer. An image processing apparatus with a real-time fault diagnosis function, comprising: the above-mentioned possible storage means and the above-mentioned microcomputer which appropriately fetches and analyzes the stored test signal processing output content to perform a fault diagnosis.
JP18437592A 1992-06-18 1992-06-18 Picture processing unit with real time fault diagnostic function Pending JPH066832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18437592A JPH066832A (en) 1992-06-18 1992-06-18 Picture processing unit with real time fault diagnostic function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18437592A JPH066832A (en) 1992-06-18 1992-06-18 Picture processing unit with real time fault diagnostic function

Publications (1)

Publication Number Publication Date
JPH066832A true JPH066832A (en) 1994-01-14

Family

ID=16152112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18437592A Pending JPH066832A (en) 1992-06-18 1992-06-18 Picture processing unit with real time fault diagnostic function

Country Status (1)

Country Link
JP (1) JPH066832A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003530791A (en) * 2000-04-07 2003-10-14 ピルツ ゲーエムベーハー アンド コー. Protective device for safeguarding hazardous areas and method for checking the functional reliability of the device
US10565466B2 (en) 2016-03-14 2020-02-18 Kabushiki Kaisha Toshiba Image processor and image processing method
JP2020145633A (en) * 2019-03-08 2020-09-10 株式会社東芝 Image processing device
JP2020160026A (en) * 2019-03-28 2020-10-01 ラピスセミコンダクタ株式会社 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003530791A (en) * 2000-04-07 2003-10-14 ピルツ ゲーエムベーハー アンド コー. Protective device for safeguarding hazardous areas and method for checking the functional reliability of the device
US10565466B2 (en) 2016-03-14 2020-02-18 Kabushiki Kaisha Toshiba Image processor and image processing method
JP2020145633A (en) * 2019-03-08 2020-09-10 株式会社東芝 Image processing device
JP2020160026A (en) * 2019-03-28 2020-10-01 ラピスセミコンダクタ株式会社 Semiconductor device

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