JPH0667979A - Control system for main storage device - Google Patents

Abstract

PURPOSE:To attain a quick switching processing without a flash processing though a cache-flash is usually requested at the time of switching a fault since writing to a cache is not at once reflected to a main storage device when a copy-back cache is adopted for the duplex processor system of a memory synchronization. CONSTITUTION:Between the information processing systems (SYSA and B) 11, 12 of active and standby systems, copy-back buffer devices (CBBM) 4a, 4b are respectively provided to store a switching content which is not reflected to the main storage device (MEM) 3b of the standby system is CBBM 4a of SYSA 11, for example. At the time of system switching occurring, whether to hit or not in the CBBM 4a is investigated at individual memory accesses so as to invalidate an entry at the time of hitting in writing. At the time of hitting in reading, the main storage reading of a copy-back cache memory (CBCM) 2a is stopped to process writing data in CBBM 4a back to the main storage device (MEM) 3b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory control method, and more particularly to a main memory control method in a dual information processing system.

[0002]

2. Description of the Related Art Generally, in a dual information processing system, two information processing systems are constructed by installing two units each of which are the constituent elements of the information processing system, that is, an arithmetic unit, a main memory unit, a control unit and an input / output unit. , A high-reliability system was constructed by connecting the two systems. In the case of the above information processing system, when one system of the two systems is the active system and the other system is the standby system and the necessary processing is performed in the active system, the standby system is the primary system of the active system. The data of the active system is transferred using the signal line connected between the two systems so that the same contents as the storage device are obtained. When the active system fails, the process can be continued without interruption by continuing the process by the main storage unit which is matched with the active system by the standby system.

In the conventional control method of the main memory, it is necessary to immediately reflect the writing to the main memory of the active system to the main memory of the standby system. Therefore, when the cache memory is adopted, the main memory is used. In many cases, the write-through method, in which writing to the device is performed immediately, is adopted. Also, when a copy-back type cache memory that does not immediately write to the main memory is used, the contents of the main memory in the cache memory that have not been updated before the system switching are changed. It is written back to and reflected in the main storage device before switching.

[0004]

In the above-mentioned conventional control method for the main storage device, the processing that was being performed until the failure occurred in the active system needs to be continued in the standby system without interruption. The contents of the main memory are made to match between the active system and the standby system, and when the write to the main memory of the active system occurs in the subsequent processing, the same contents are written in the standby system, so that Main memory is kept consistent.

In the case of such a control system, if a sash memory is to be installed in order to improve the performance of the main memory, the main memory must be updated immediately, so the write-through cache system must be installed. I have to. However, the write-through cache method has a problem in that the write speed of the main storage device is reached at the time of writing, and the effect of introducing the cache memory is halved in a system having a high write frequency.

Further, when the copy-back cache method is adopted to improve the performance at the time of writing, the contents of the cache memory are updated at the time of occurrence of a failure, but the contents of the main storage device are still updated. Therefore, the main memory of the standby system is not updated. Therefore, there is a problem that a process of reflecting the main memory device end update portion in the cache memory on the standby main memory device is required when performing the switching process.

Since the update processing of the main memory of the standby system must use the hardware of the system in which the failure has occurred, it is difficult to expect that it will end normally, and the processing must be continued promptly. There is a problem that the switching process takes a lot of time even though it is a tracing system.

[0008]

According to the control method of the main memory of the present invention, a failure occurs when a failure occurs in one system of an information processing system having dual systems and two systems. Duplicated information processing that employs a copy-back cache memory that controls the contents of both main memories of both systems to always match in order to continue processing to the system that has not occurred from the system In the control method of the main storage device of the system, a buffer for storing the write contents of the storage device in each of the two systems is provided between the two systems, and each of the two systems is provided with a buffer. When a system switch occurs in, the stored contents of the main storage device of the second system after switching are not updated,
When the latest content is stored in the buffer of the first system, the write content in the buffer of the first system is written before the stored content of the main storage device of the second system is used. It has processing means for writing to the main memory of the second system.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a duplex information processing system to which an embodiment of the present invention is applied.

In FIG. 1, in the duplex information processing system of this application example, two systems having the same configuration are connected in order to take over the processing at the time of failure, and an active information processing system (hereinafter referred to as SYSA) 11 and processing at the time of failure are processed. And a standby information processing system (SYSB) 12 that takes over.

SYSA11 is a processor (hereinafter CPU)
1a and CPU 1a have an address bus 5a and a data bus 6
a copyback cache memory (hereinafter referred to as CBCM) 2a connected by a, and an address bus 7a to the CBCM 2a,
A main memory device (hereinafter ME) connected by a data bus 28a.
M) 3a and a copyback buffer device (hereinafter referred to as CBBM) 4a connected to the CPU 1a by an address bus 5a and a data bus 6a.

The SYSB 12, like the SYSA 11, has a CPU 16, a CBCM 2a, a MEM 3b, and a CBB.
And M4b.

The CBBM 4a of SYSA11 is SYS.
Address bus 9a and data bus 1 in MEM 3b of B12
0a and CBBMb of SYSB12 is SYS.
Address bus 9b and data bus 1 on MEM 3a of A11
0b, and this application example is SYSA11 and SYSB.
The system configuration is such that 12 and 12 are connected symmetrically to each other.

FIG. 2 is a block diagram showing an example of the copy-back buffer device in this application example and showing a case in the active information processing system.

In FIG. 2, the CBBM in the SYSA 11
Reference numeral 4a denotes a data memory 21a connected to the CPU 1a by a data bus 6a, and a free memory 20a connected to an address bus 5a from the CPU 1a and an address bus 5b from the CPU 1b and indicating an address of a copy of the MEM 3a stored in the data memory 21a. And a valid flag memory 22a including a flag indicating that data is valid and a flag indicating that data has been written.

Next, the operation of this application example will be described with reference to FIGS.

When the SYSA 11 and SYSB 12 start operating, all the copies of the main memory in the CBCMs 2a and 2b are in the invalid state. At this time, CPU1a is MEM
3a is read by the CBCM2 through the address bus 5a.
When instructed to a, the CBCM 2a is searched for a copy of the contents of the MEM 3a corresponding to the address. Corresponding MEM
If the copy of 3a does not exist, the CBCM 2a instructs reading of the MEM 3a through the address bus 7a.
The MEM 3a returns the contents of the main memory corresponding to the address to the CBCM 2a via the data bus 8a. CBCM2
a sends the contents of the main storage device returned from the MEM 3a to the CPU 1a via the data bus 6a and at the same time CBCM
The data is stored in the data memory 21a as a copy of the main storage device in the empty buffer in which the valid flag is not set in 2a, and the corresponding address is stored in the tag memory 20a. Also, a valid flag is set to indicate that this copy is valid. If there is no free buffer, select the buffer referenced most recently and store it. At this time, the flag indicating that the data has been written is cleared, and the contents of the MEM3a read after that are stored.

As described above, the MEM 3a is stored in the CBCM 2a.
When there is a copy of the MEM3a, the copy of the MEM3a stored in the CBCM2a can be returned to the CPU1a without accessing the MEM3a, and the CPU1a apparently receives the ME.
It seems that M3a has been sped up.

When the CPU 1a writes, the write address is instructed to the CBCM 2a through the address 5a, and at the same time, the data to be written to the data bus 6 is sent. The CBCM 2a receiving the address and data is CB
If there is a copy of the same address as the address to be written in the CM 2a, it is replaced and a flag indicating that it has been written is set. If it does not exist, the same processing as that which did not exist at the time of reading is performed and the data is stored.

At the time of writing by the CPU 1a, the write address and data are transmitted to the CBCM 2a and simultaneously to the CBBM 4a via the address bus 5a and the data bus 6a. The CBBM 4a has the structure shown in FIG.
The address via the address bus 5a is the tag memory 20.
If all the entries of a are compared and there is a matched address, the address match signal 24 of a signal indicating that there is
The location of the entry that was output to a is indicated in the valid flag memory 22a of the data memory 21a through the address matching entry number 25a.

When the valid flag of the matching entry is set, the cache read stop signal 14 indicating that the entry corresponding to the address to be written is valid.
It is output as a and is overwritten on the data memory of the same entry. If there is no matching entry, an empty entry in which the valid flag is not set is searched for, an address is written in the tag memory of the empty entry, data is written in the data memory, and the valid flag is set. If there is no empty entry, the data of the oldest written entry is written to the standby MEM 3b via the data bus 10a and the address bus 9a, and then new data is written to the entry.

When the processing of the active system proceeds as described above, CB
Recently used MEM3 for the cache memory of CM2a
Since a copy of a is stored, the probability that data to be accessed exists in the cache memory of the CBCM 2a is high due to the locality of reference of the program, and the average access time of the MEM 3a is shortened. CBBM4
The recently written data is stored in a, and the contents of the MEM 3b of the SYSB 12 match the contents of the MEM 3a of the SYSA 11 except those stored in the CBBM 4b.

At this time, a failure occurs in SYSA11,
When the SYSB12 takes over the process, the newly operating SYSB12, which was the standby system before, operates by the CPU 11b accessing the CBCM2a similarly to the old operating system SYSA11. At this time, the data in the MEME3b is in the old operating system. It is left in the CBBM 4a of the SYSA11 system, and may not be the latest version. Therefore, the address bus 5b in the SYSB 12 is not limited to the CBCM 2b but also the other system SYSA.
The CBBM 4a, which is also connected to the 11 CBBM 4a, receives the address from the address bus 5b, checks whether there is a copy of the address indicated by 5b, and if there is, a valid bit of the valid flag memory 22a at the time of writing. To clear. At the time of reading, it is indicated to the CBCM 2b that it was present via the cache read stop signal 14a, the main memory read operation of the CMCM 2b is temporarily stopped, and the contents of the data memory are passed through the address bus 9b and the data bus 10b. At the same time as writing to MEM3a, the valid flag is cleared. After that, the processing of the CMCM 2b can be restarted and correct data can be read by the CBCM 2b.

[0025]

As described above, according to the present invention, when a failure occurs in a system on one side of an information processing system having a dual system and having two systems, the failure system does not occur. The main memory of the duplicated information processing system adopting the copy-back cache memory that controls the contents of each main memory of both systems to always match so that the system can continue processing. In the control method, a buffer for storing the write contents of the storage device in each of the two systems is provided between the two systems, and each of the two systems is provided with a buffer to switch the system from the first system to the second system. If the write contents of the main memory of the second system after switching are not updated and the latest contents are stored in the buffer of the first system, the main memory of the second system is changed. Use the memory contents of the device By having a processing means for writing the write contents in the buffer of the first system to the main storage device of the second system before the operation, the contents of the cache memory on the switching side at the time of system switching are stored in the main storage device of the same system. Since it is possible to use the switched copyback cache memory without writing back to the memory, the performance of the memory access at the time of writing to the switched main storage device is improved, and the switching process at the time of failure can be performed. It has an effect that it can be made faster than before.

[Brief description of drawings]

FIG. 1 is a block diagram showing a duplex information processing system to which an embodiment is applied.

FIG. 2 is a diagram showing an internal configuration of a copyback buffer device in the present application example.

[Explanation of symbols]

1a, 1b Processor (CPU) 2a, 2b Copyback cache memory device (CBCM) 3a, 3b Main memory device (MEM) 4a, 4b Copyback buffer device (CBB)
M) 5a, 5b Address bus between processor caches 6a, 6b Data bus between processor caches 7a, 7b Address bus between cache and main memory 8a, 8b Data bus between cache and main memory 9a, 9b Copyback buffer-Other main memory Inter-address bus 10a, 10b Data bus between copy-back Huffer-main system main memory 11 Active information processing system (SYSA) 12 Standby information processing system (SYSB) 14a, 14b Cache read stop signal 20a Tag memory 21a Data memory 22a Valid flag memory 23a Valid flag 24a Address match signal 25a Address match entry number

Claims (1)

[Claims] 1. When a failure occurs in a system on one side of an information processing system having dual systems and two systems, processing is continued from the failed system to the system that has not In order to control the contents of both main memories of both systems so as to always match each other, in the control method of the main memory of the duplicated information processing system that employs the copyback cache memory, In each of the two systems, a buffer for storing the write contents of the storage device of each of the two systems is provided, and when the system is switched from the first system to the second system, the buffer after the switching is performed. When the storage contents of the main storage device of the second system are not updated and the latest contents are stored in the buffer of the first system, the storage contents of the main storage device of the second system are changed. The first before use A system for controlling a main memory device, comprising: processing means for writing the write contents in the buffer of the system of 1) into the main memory device of the second system.