JPH0666757B2 - Synchronous acquisition device for spread spectrum communication - Google Patents

Description

The present invention relates to a synchronization acquisition device for spread spectrum communication used in spread spectrum communication.

[Conventional technology]

In spread spectrum communication, the transmitting side transmits a signal that has been band-spread using a pseudo noise signal, and the receiving side uses the same pseudo noise signal as that used on the transmitting side for correlation,
Since it detects necessary signals and has advantages such as excellent confidentiality, multiplexing, and anti-multipath characteristics, it is expected as a promising communication system in the future.

FIG. 10 is a block diagram showing an example of a conventionally proposed device. In the figure, 1a to 1c are correlators, 2a to 2c are bandpass filters, 3a to 3c are detectors, 4 is a differential amplifier, 5
Is a control unit, 6 is a VCO, 7 is a frequency divider, 8 is a pseudo noise generator, 9a is a 1-bit delay circuit, and 9b is a 1-bit delay circuit.

In the device configured as described above, the oscillation frequency of the VCO 6 is divided by the frequency divider 7, a pseudo noise generator 8 generates a pseudo noise signal based on the frequency-divided signal, and the signal is delayed by a delay circuit. Correlators 1a to 1 are delayed by 9a and 9b to provide a phase difference.
supply to c. Then, when the correlation is not obtained, no output is generated from any of the detectors 3a to 3c, but when the correlation is obtained, the output from these detectors is generated,
The control unit 5 controls the oscillation frequency of the VCO 6 so that the outputs of the detectors 3a and 3b become equal and the output from the differential amplifier 4 becomes zero while the output of the detector 3c is generated. Therefore, the oscillation frequency of the VCO 6 is controlled so that the input voltage of the differential amplifier 4 becomes equal. Therefore, a stable synchronization state is achieved when the input voltages of the differential amplifier 4 are equal. Also, such synchronization can be performed by changing the division ratio of the division cycle 7.

[Problems to be solved by the invention]

However, such a conventional device has a drawback that it takes a long time to acquire the synchronization.

[Means for solving problems]

In order to solve such a drawback, the present invention generates a pseudo noise by selectively generating a pseudo noise signal having the same number of bits as the one cycle of the pseudo noise signal of the received signal and a different number of bits of one cycle. It is equipped with a container.

[Operation] Pseudo-noise signal having the same number of bits as that of the input signal after synchronization is acquired by the pseudo-noise signal of one period and the pseudo-noise signal of different bit number of the input signal. Is switched to.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.
The same parts as those in FIG. 10 and the corresponding parts have the same symbols. In the figure, 10a to 10c are comparators which generate an output signal of "1" level when an input voltage higher than an internal reference voltage is supplied, 18 is a first pseudo noise signal having a predetermined number of bits as one cycle, and The sum of the bits at one or more arbitrary positions for the bit sequence of the first pseudo-noise signal is the number of correlators equal to 2
Second increase or decrease within the limit of the number of bits less than double
A pseudo noise generator that selectively generates a pseudo noise signal. When a "1" level signal is supplied to the terminal 18a, the first pseudo noise signal is supplied and a "0" level signal is supplied. Then, the second pseudo noise signal is generated. In this embodiment, one cycle 10 is used as the first pseudo noise signal.
As the second pseudo noise signal of 23 bits, 3 bits are added to the last part of the first pseudo noise signal to obtain one cycle of 1026 bits. As described above, the bit to be changed may be added to or subtracted from the first pseudo noise signal, the entire bit sequence in a certain range may be changed, or the bit sequence may be distributed to a plurality of arbitrary places. However, the total sum of the number of bits that increases or decreases must be less than twice the number of correlators. 11 generates the same number of output signals as the number of correlators based on the output signal of the pseudo noise generator 18, so that the phase difference between the output signals whose phases are separated by the maximum is one bit less than the number of correlators. The phase difference is 1 bit in this embodiment. 15
Is a control unit, and when an output voltage is generated from any of the comparators, a signal of "1" level is transmitted from the terminal 15d to cause the pseudo noise generator 18 to generate the first pseudo noise. Also, when the output voltage is not generated, a signal of "0" level is transmitted, and the pseudo noise generator 18 generates the second pseudo noise.

The operation of the device configured as described above is as follows. The signal generated from the pseudo noise generator 18 is supplied to the phase shifter 11, and its output terminal outputs signals having different phase differences by 1 bit. When not synchronized, control unit 15
Generates a "0" level signal from the terminal 15d, so that the pseudo noise generator 18 generates a second pseudo noise signal of 1026 bits per cycle.

FIG. 2 is a diagram for explaining the operation when synchronization is achieved. (A) is the second pseudo noise signal, (b) is the bit sequence of the received signal, and 1023 bits are the symbols "a" to "". The second pseudo noise signal is obtained by adding three bits of the symbol "to" to the rear part of the first pseudo noise signal having the same bit arrangement as the received signal. When the received signal is input at time t1 and synchronization tracking is started, the bit train of the received signal is compared with the second pseudo noise signal at regular intervals, and at time t2 both signals match and synchronization is achieved. This state is a correlated state, and at this time, for example, when a signal is output from the correlator 1a, this signal becomes a bandpass filter 2a.
Is detected by the wave detector 3a via. 2 (c), (d)
Is a second pseudo noise signal supplied to the other two correlators, and these signals (a), (c) and (d) have a phase difference of 1 bit each. In this way, since the second pseudo noise signal is deviated by 1 bit, if the correlation between the second pseudo noise signal and the received signal is obtained by 1023 bits at regular intervals,
Any one of the three correlators is first correlated.

In this way, when the correlation between the received signal and the second pseudo noise signal is obtained by any one of the correlators, the control unit 15 generates a "1" level control signal from the terminal _1501, so that the pseudo noise generator is generated. The pseudo noise signal generating 18 is switched from 1026 bits to 1023 bits. As a result, the number of bits of the input signal matches the number of bits of the pseudo noise signal, and moreover, one of the output signals of the phase shifter 11 and the input signal are correlated with each other, and synchronization acquisition is realized.

In this example, the shift is 3 bits each, so this shift is repeated 341 times. If you do, it will return to its original state. Conversely, at the worst, shift
If it is performed 341 times, the correlation is always obtained. If the bit rate of the pseudo noise signal is 1.023MBPS (megabit pars), the shift will be Every time, Capture is completed within. Although details are omitted, the conventional method requires a capture time of, for example, about 27 seconds.

The example of FIG. 2 is an example in which 3 bits are added to the rear part of the first pseudo noise signal, but the present invention is not limited to this, and these 3 bits can be dispersed to a plurality of arbitrary places as shown in FIG.
In this case, when all the bits are correlated, but when a certain range of bits are correlated, for example, when about 800 bits out of 1023 bits are correlated, it is sufficient to establish a correlated state. In this case, the determination can be made by a method such as setting the comparison voltages of the comparators 10a to 10c to appropriate values.

FIG. 4 is a block diagram showing another embodiment. In the figure, 25 is a control unit, 21 is a pseudo noise signal, and the output signals are generated in a number exceeding the number of correlators based on the pseudo noise signal, and a plurality of columns are generated in which the phase difference between adjacent output signals is shifted by 1 bit or less. The phase shifters 30, 40 and 50 are switchers that switch and output the input signal according to the signal supplied from the control unit 25. In this example, the phase shifter 21 generates 17 types of pseudo noise signals having different phases by 1/4 bit based on the pseudo noise signal.
When no correlation is detected in any of the comparators, the control unit 25 outputs a signal of "0" level at the terminal 25i, a fifth output signal of the phase shifter 21 at the terminal 25g, and a phase shifter 21 at the terminal 25f. 9
The terminal 25e is adapted to output the thirteenth output signal and a signal for selecting the thirteenth output signal of the transporter 21. Terminal
When the output in which the correlation is detected is sent from any of the comparators connected to 25a to 25c, the terminal 25i outputs "1".
The level of the signal to be transmitted to the terminals 25e to 25g depends on which of the terminals 25a to 25c the detection signal is supplied to. It is decided to follow the table.

The operation of the device configured as described above is as follows.
The phase shifter 21 has 17 output terminals as shown in FIG. 5, and outputs signals whose phases are shifted by 1/4 bit from each terminal. Then, the switching devices 30, 40, 50 are the fifth and the ninth of the phase shifter 21 according to the signal supplied from the control unit 25.
The 13th and 13th output signals are selected and output.

If synchronization is not achieved in this state, synchronization is acquired in the same manner as the operation up to the previous example. When the synchronization is acquired, the pseudo noise generated by the pseudo noise generator 18 is switched from the 1026 bit second pseudo noise signal to the 1023 bit first pseudo noise signal. After that, the control unit 25 selects the output signal of the phase shifter 21 according to the reference in Table 1 according to which of the terminals 25a to 25c the detection signal is supplied to.

FIG. 6 shows the output signal of the phase shifter 21 and the detectors 3a to 3c at this time.
Of the output voltage of the phase shifter 21, the output terminal number of the phase shifter 21 (phase of the output signal), a, b, and c are the output voltage characteristics of the detectors 3a, 3b, and 3c, respectively Is the comparator 10a
Represents a threshold level of ~ 10c. Now, when the synchronous acquisition is performed at the point of the symbol "d" and the output signal is transmitted from the detector 3a, the signal output from the comparator 10a is in the range "1" above the threshold level represented by the alternate long and short dash line. It is a portion indicated by "a". In this case, the synchronization state is not the most stable synchronization point because the synchronization acquisition is not performed at the center of the detector 3b. Therefore, if the output of the phase shifter 21 is selected from the 1st, 4th, and 7th according to the criteria of Table 1, the synchronization state becomes as shown in FIG. 7, and the range “a” in FIG. 6 is obtained. Since the signal of is received, it can be received at the most stable synchronization point.

FIG. 8 shows another embodiment, 17 is a frequency divider for inverting the phase of the input signal of the frequency divider according to the signal supplied from the control unit 25,
In addition to the function of the control unit 15 described above, the terminal 25h is provided so that the correlation becomes better when an output signal is generated from any of the comparators and the output voltage of the differential amplifier 4 becomes zero. Is a control unit for inverting the input signal phase of the frequency divider 17 according to the output of the.

The device constructed in this way is first described in the same way as the above example.
After the synchronous acquisition by the 26-bit second pseudo-noise signal, the pseudo-noise signal is switched to the 1023-bit first pseudo-noise signal. At this time, the correlation is established in any one of the correlators 1a to 1c as described above. At this time, since the correlation output signal can be obtained within the range of the bit deviation of up to ± 1 bit, the correlation output is obtained, and even if the cycle is changed from 1026 bits to 1023 bits per cycle, the maximum is 1 bit deviation, and the bit synchronization is completely completed. Can't get Therefore, as described above, the changeovers 30, 40 and 50 are controlled to suppress the bit shift to 1/4 bit or less. Then, the control unit 25 inverts the output signal phase of the frequency divider 17 so that the correlation becomes better when the output signal is generated from any one or a plurality of comparators, and further finely correlates. It is connected.

The reason why the correlation state changes due to the phase inversion is as follows. FIG. 9 (a) shows an input signal of the frequency divider 17, and the signal shown in FIG. 9 (b) is normally output. However, if the output signal is phase-inverted at the time t1, FIG. The waveform shown in FIG. 9D is obtained, and when the phase is inverted at the time t2, the waveform shown in FIG. 9C is obtained. As you can see from Figure 9,
The waveform of (c) is 1/2 bit behind the waveform of (b),
The waveform in (d) is advanced by 1/2 bit.

Therefore, after the synchronization acquisition is performed, the correlation is better, that is, the center correlator among the three correlators is used.
It is effective to invert the output signal phase of the frequency divider 17 by 1/2 bit so that the correlation can be obtained in 1b. And
Since the output of the detector 3a and the output of the detector 3c are supplied to the positive and negative input terminals of the differential amplifier, the voltage of the difference is the control unit 25.
Supplied to d. As a result, the control unit 25 selects the frequency division stage of the multistage frequency divider 17 according to the signal transmitted from the terminal 25h, so that the best correlation state, that is, the highest level at the top of the characteristic "B" in FIG. Make correlations close to each other.

The reason why the best correlation point is obtained by selecting the division stage of the multistage divider 17 is as follows. As described above, if the output signal of the frequency divider is phase-inverted at an appropriate timing in synchronization with the input signal, the phase can be adjusted within the range of ± 1/2 bit. Now, assuming that the oscillation frequency of the VCO 6 is 64f ₀ and the multistage frequency divider 17 is configured in 6 stages, the first stage is 32f ₀ , the second stage is 16f ₀ ,
The third row is 8f ₀ , the 4th row is 4f ₀ , the 5th row is 2f ₀ , and the 6th row is f ₀
Becomes Therefore, if the phase inversion is performed in the sixth stage, the phase change range is ± 1/2 bit, but in the fifth stage it is ± 1/4 bit, in the fourth stage it is ± 1/8 bit, and in the third stage it is ± 1 bit. / 16
Bits: ± 1/32 for the 2nd stage, ± 1/32 for the 1st stage
If the input signal of the multi-stage frequency divider 27 is inverted by 64 bits, the phase can be controlled within the range of ± 1/128 bits. Therefore, for example, in the case of a 6-stage multi-stage frequency divider, if phase shift control is performed in the order of 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 bits. , The range of 1 bit can be synchronized with the precision of 1/128 bit by 7 phase shifts.
The phase control in the same range cannot be performed unless it is performed 28 times (64 + 32 + 16 + 8 + 4 + 2 + 1). Therefore, if one shift requires 1 msec, the former requires 7 msec, while the latter requires 128 msec.

In this way, by controlling the output phase of the multi-stage frequency divider 27, synchronous follow-up can be performed with an accuracy of 1/128 bit. As shown in FIG. 7, the output of the differential amplifier 4 is obtained by inverting the output of the detector 3a indicated by "a" and the output of the detector 3c indicated by "c", that is, the characteristic indicated by the dotted line. Since they are added together, the characteristics shown by the chain double-dashed line are obtained. Here, if the frequency dividing stage that performs phase inversion is selected from the multi-stage frequency divider 17, the output signal of the differential amplifier 4 becomes 1 /
It approaches zero level with an accuracy of 128 bits. This comes close to the top of the drag characteristic "b" as shown in FIG.

After that, the control unit 35 selects a frequency dividing stage for inverting the output signal of the multi-stage frequency divider 27 so that the output of the differential amplifier 4 becomes zero.

In the above embodiment, the phase transition of the frequency divider output is performed by the phase inversion of the frequency divider output.However, a method using an integrating circuit or the like can also be used in an LSI if a digital device is used. It is possible and stable operation can be achieved at low cost.

〔The invention's effect〕

As described above, according to the present invention, since the synchronization acquisition is performed by the pseudo noise signal having the bit number different from the bit number of the reception signal, the high-speed synchronization acquisition can be performed, and the pseudo noise signal is input to the input signal after the synchronization acquisition. Since the number of bits is changed to the same number, the stable reception can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a phase relationship between an input signal and a pseudo noise signal, and FIG.
FIG. 4 is a diagram showing another pseudo noise signal, FIG. 4 is a diagram showing another embodiment, FIG. 5 is a diagram showing output terminals of a phase shifter, and FIGS. 6 and 7 are output characteristics of a detector. FIG. 8 is a block diagram showing another embodiment, FIG. 9 is a waveform diagram showing a waveform of a frequency divider output signal, and FIG. 10 is a block diagram showing an example of a conventional device. 1a to 1c …… Correlator, 2a to 2c …… Band pass filter, 4
...... Differential amplifier, 5,15,25 …… Control unit, 6 …… VCO, 7,1
7,27 …… divider, 8,18 …… pseudo noise generator, 11,21 ……
Phase shifter, 30, 40, 50 ... Switching device.

Claims (2)

[Claims] 1. A direct sequence spread-spectrum communication synchronization acquisition apparatus having N correlators (N is a positive integer of 1 or more) and performing synchronization by shifting bits at a constant cycle. , The first pseudo noise signal having a predetermined number of bits as one cycle and the second pseudo noise in which the total sum is increased or decreased by the number of bits of 2N times or less at one place or a plurality of arbitrary places with respect to the bit sequence of the first pseudo noise signal A pseudo noise generator that generates any one of the signals by selection, and generates N kinds of output signals based on the output signal of the pseudo noise generator, and the phase difference between the output signals whose phases are maximum apart is N-1. A phase shifter that is set to be less than or equal to a bit and a second pseudo noise signal is generated when no correlation is detected by any correlator, and at least an arbitrary number of bits of the second pseudo noise signal is generated by any correlator. Phase of There detected when the spread spectrum communication synchronization acquisition apparatus characterized by comprising a control unit for controlling the pseudo-noise signal generator to the first pseudo-noise signal is generated. 2. A synchronization acquisition device for spread spectrum communication of a direct sequence system, which has N correlators (N is a positive integer of 1 or more) and carries out synchronization by shifting bits at a constant cycle. , The first pseudo noise signal having a predetermined number of bits as one cycle and the second pseudo noise in which the total sum is increased or decreased by the number of bits of 2N times or less at one place or a plurality of arbitrary places with respect to the bit sequence of the first pseudo noise signal A pseudo noise generator for generating any one of the signals by selection, and a phase shifter for generating a plurality of columns in which the phase difference between adjacent output signals is shifted by 1 bit or less based on the output signal of the pseudo noise generator. , A signal switcher which has the same number as the number of detectors and selects and sends out different signals from the signals supplied from the phase shifter, and the second pseudo noise when no correlation is detected in any of the correlators. Generate a signal The pseudo noise signal generator is controlled so that the first pseudo noise signal is generated when at least an arbitrary number of bit correlations of the second pseudo noise signal are detected in one of the correlators, and the first pseudo noise signal is generated. For spread spectrum communication, a control unit for controlling the signal switching device to select the one having the best correlation among the signals supplied to the signal switching device when Synchronous acquisition device.