JPH0666060B2 - Bus priority control method - Google Patents

Description

The present invention relates to a high-speed bus priority control system in an information processing system that uses a system bus shared by a plurality of processors and the like.

[Conventional technology]

FIG. 2 shows a general configuration example of an information processing system using a system bus. In the figure, 21 is a system bus, and 22 and 23 are CPUs of the central processing unit.
# 0 and CPU # 1, 24 are the MAC of the storage controller, 25 is the MSU of the storage device, and 26 and 27 are the CH # of the channel device, respectively.
0 and CH # n. In this example, a bus arbiter is provided in each CPU.

Right to use the SysM Bus 21 1 of the devices that will be the bus master
Only given to one device. When bus usage requests from multiple devices are in conflict, priority control is performed,
The right to use the bus is given to the highest-level device. Such priority control is performed using, for example, a bus arbiter provided in each CPU.

FIG. 3 shows the internal structure of a CPU having a bus arbiter. In the figure, 21 is the system bus and 22 is
CPUs # 0 and 31 are arithmetic units, 32 is a buffer, 33 is a buffer controller, 34 is a bus arbiter, 35 is a system bus controller, 36 is another BRQ line indicating a bus request from another device, and 37 is from its own device. Own BRQ line indicating bus request, 38 is address line, 3
Reference numeral 9 represents a data line.

Taking the execution of the LOAD instruction as an example, the operation will be described with reference to the time chart of FIG. 4. When the LOAD instruction requests loading of data necessary for the arithmetic processing in the arithmetic unit 31, the buffer 32 is searched first. . If the data at the target address cannot be found in the buffer 32, the buffer controller 33 sets a buffer miss flag,
A signal BSMS is sent to the bus arbiter 34 indicating that data needs to be fetched from the MSU 25.

In response to the signal BSMS, the bus arbiter 34 turns on the signal BRQ on the own BRQ line 37 to notify the other device of the bus request, and at the same time, the presence or absence of a bus request from the other device by the other BRQ line 36 and the own device. Determine the bus priority based on the priority level,
As a result, when the bus use right can be acquired, the control is passed to the system bus controller 35, and a command for READ access to the MSU 25 is sent to the MAC 24. During this period, three cycles are spent as shown.

[Problems to be solved by the invention]

As described above, the conventional method has a relatively large overhead based on the control for establishing the bus use right,
The higher the frequency of use of the system bus, the lower the efficiency of the system.

[Means for solving problems]

In the conventional method, the bus request signal (BRQ) is issued to determine the priority of the bus usage after the cause of the bus usage is determined. By the way, when the possibility of bus use arises without determining the reason why bus use is necessary, for example, in the above-mentioned example, the LOAD instruction is issued, so that the MSU uses the system bus to transfer data. If the priority determination control of the bus use right can be started at the stage where it is found that there is a possibility of fetching, the overhead time when using the bus can be shortened. However, on the other hand, when it is determined that the bus use is unnecessary after that, not only the prioritization control performed earlier becomes useless, but also when another device makes a bus request, the bus use is delayed. It will also happen.

Therefore, the present invention provides a dummy bus request signal (referred to as a DBRQ signal) having a priority level lower than that of the bus request signal (BRQ), and the dummy bus request signal (DBRQ signal is generated when the possibility of using the bus occurs. ) Is turned on to start priority control of the bus use right, and the bus use right is acquired on condition that there is no bus request signal (BRQ) from another device. This can be seen as a kind of reservation. As a result, even if it is determined that the bus is not used after that and the bus use right once obtained is abandoned, the influence on other devices can be made extremely small.

The configuration of the present invention thereby provides an information processing system having a system bus shared by a plurality of devices having a bus arbiter, wherein each of the above devices detects the execution of a processing instruction including the possibility of using the system bus. And a means for sending a first signal to the bus arbiter, and a means for sending a second signal to the bus arbiter when the necessity of using the system bus is confirmed by the processing instruction. When this signal is detected, a dummy bus request having a lower priority level than the bus request is made, and immediately the control for determining the priority right for acquiring the system bus use right is started. If it cannot be obtained, a rightful bus request is made when the second signal is detected to obtain the right of use. Performs control to, the second from the detection of said first signal within a predetermined time
When the signal of is not detected, if the use right is acquired by the dummy bus request, the acquired use right is abandoned, and the control for determining the priority right for acquiring the use right is executed. The feature is that the control is stopped.

〔Example〕

 The details of the present invention will be described below with reference to examples.

FIG. 1 is a block diagram of one embodiment of the present invention, which is an improvement of the conventional example shown in FIGS. 2 and 3. In the figure, 1 is an arithmetic unit, 2 is a buffer, 3 is a buffer controller, 4 is a bus arbiter, 5 is a system bus controller, 6 is another BRQ line indicating a bus request from another device, and 7 is a bus request of its own device. Own BRQ line that indicates, 8 is an address line, 9 is a data line, and 10 is a BSMS that notifies a buffer miss flag state.
Line, 11 is LOAD / ST that notifies the occurrence of LOAD / STOR access
OR line, 12 is another DBRQ indicating a dummy bus request from another device
Line 13 is the own DBRQ line indicating the dummy bus request of the own device. Reference numerals 21 and 22 respectively correspond to the system bus and CPU # 0 in FIG. 2, and the other CPUs have the same configuration as CPU # 0.

FIG. 5 is a flow chart showing the control function of the bus arbiter 4 in FIG. 1, and FIG. 6 is a time chart for explaining the operation of this embodiment. Below, FIG. 1, FIG.
This embodiment will be described with reference to FIGS.

For example, when a LOAD instruction is issued, the buffer control device 3 turns on the LOAD / STOR signal on the LOAD / STOR line 11 and then searches the buffer 2.

The bus arbiter 4 is, as shown in FIG.
When the ON of the OR signal is detected, the dummy bus request signal DBRQ is immediately turned ON with. Next, check the other BRQ line 6, and if none of the other devices have turned on BRQ, check the other DBRQ line 12 with, and if none of the other devices turned on DBRQ, then use the bus , And then monitors the BSMS line at and waits for the buffer miss flag BSMS to turn ON, which indicates that there is no access data in the buffer. BSMS is ON
If so, a command for data fetch is sent to the MAC 24 (see FIG. 2) of the storage controller via the system bus controller 5 to execute data transfer.

However, if BSMS does not turn on within a certain time in, the bus usage right is abandoned by assuming that the system bus is not used.

Also, if DBRQ from another device is detected to be ON,
Priority determination (described later) is performed, and if the priority level of the own device is higher than, the bus usage right is acquired. On the other hand,
If the priority level of its own device is lower, it will be in the waiting state of BSMS = ON.

If ON is detected in BRQ from another device, wait for BSMS to turn ON with, turn ON BRQ when BSMS turns ON, and then determine priority priority. To do. When the priority of the own device is obtained in, the bus use right is acquired in and the command of is issued.

It should be noted that in the above priority determination in and, there are n devices (CPUs) that can be bus masters, one of the n priority levels is assigned to each, and the priority level of the own device is m. If (1 <m <n), BRQ and DBRQi (i = 1, ..., M, ...
During n), the following priority relations can be set and logically performed.

BRQ0- (m-1)>BRQm> BRQ (m + 1) -n> DBRQ0-
(M-1)>DBRQm> DBRQ (m + 1) to n As a result, as shown in FIG. 6, when there is no BRQ or DBRQ having a higher priority level than the DBRQ of the own device, B
Since the procedure for transmitting the RQ can be omitted, the operation can be performed in two cycles which is one cycle shorter than the case of the conventional example shown in FIG. Although the present invention has been described by taking the case where the system bus is acquired in the execution of LOAD / STOR as an example, it is obvious that the present invention can be applied to any case where the possibility of using the system bus can be detected immediately before. .

〔The invention's effect〕

As described above, according to the present invention, the priority determination control for acquiring the bus use right can be started earlier than the conventional method, so that the time required for data transfer can be shortened and the utilization efficiency of the system bus can be improved. be able to.

[Brief description of drawings]

1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of a conventional system having a system bus, FIG. 3 is an internal block diagram of the CPU in FIG. 2, and FIG. 4 is a block diagram of FIG. FIG. 5 is a flow chart of an embodiment of the present invention, FIG.
FIG. 6 is the time chart. In the figure, 1 is an arithmetic unit, 2 is a buffer, 3 is a buffer controller, 4 is a bus arbiter, 5 is a system bus controller,
6 is another BRQ line, 7 is own BRQ line, 8 is address line, 9 is data line, 10 is BSMS line, 11 is LOAD / STOR line, 12 is other DBRQ line,
13 indicates its own DBRQ line.

Claims (1)

[Claims] 1. An information processing system having a system bus shared by a plurality of devices having a bus arbiter, wherein each of the first devices detects the execution of a processing instruction including the possibility of using the system bus. The bus arbiter detects the first signal, and includes means for sending a signal to the bus arbiter, and means for sending a second signal to the bus arbiter when the necessity of using the system bus is determined by the processing instruction. When this occurs, a dummy bus request having a lower priority level than the bus request is issued and control for immediately determining the priority for acquiring the system bus usage right is started, and the usage right can be acquired by the dummy bus request. If not possible, when the second signal is detected, a regular bus request is made to control the acquisition of the right of use. The second signal is detected within a fixed time after the first signal is detected.
When the signal of is not detected, if the use right is acquired by the dummy bus request, the acquired use right is abandoned, and the control for determining the priority right for acquiring the use right is executed. A bus priority control method characterized by stopping the control.