JPH0661966A - Digital stuff control circuit - Google Patents

Abstract

PURPOSE:To provide a digital stuff control circuit which reduces various types of jitters and can maintain the high quality of a transmission circuit. CONSTITUTION:The digital stuff control circuit consists of a memory 10 where the input data are temporarily written, a write counter 20 which produces a write pulse from an output clock to the memory 10, a timing signal generating circuit 30 which produces a clock and a toothless clock from an output clock only when a frame pulse and the data are required, a read counter 40 which produces a read pulse from the toothless clock to read the data out of memory 10, a subtractor circuit 50 which performs the subtraction between the outputs of both counters 20 and 40, and a deciding circuit 60 which decides the necessity for insertion of a stuff bit based on the output of the circuit 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital stuff control circuit for digital communication. In recent years, a communication system called a new synchronous network has been adopted as digital communication.

FIG. 8 is a diagram for explaining an example of a frame format. The figure shows an example in which four lines of data are multiplexed, and additional bits are inserted at fixed timings and stuff bits are further inserted.

The additional bits are used for line monitoring and control, and the stuff bits are inserted for frequency matching. Further, the additional bits used here are continuous information of several bytes, and data cannot be inserted during that period. As a result, the circuit that determines the necessity of inserting the stuff bit has a great influence, and the stuff bit cannot be inserted properly, and the jitter amount, which is a minute phase shift from the position where the data should originally be, is generated. Increases and deteriorates the line quality.

There is a demand for a stuff control circuit capable of suppressing the jitter and improving the line quality.

[0005]

2. Description of the Related Art FIG. 9 is a block diagram for explaining a conventional example. In the figure, 10 is a memory, 10A is a multiplexing circuit, 20 is a write counter, 30 is a timing signal generating circuit, 40 is a read counter, 90A is an AND circuit, and 90B is an SR latch circuit.

In this circuit, the write counter 20 counts the input clock to write the write pulse 2a to the memory 10 and the phase signal 2b to the specific memory 10.
To occur. The timing signal generation circuit 30 generates various timing signals 3a from an output clock and a toothless clock 3b having a clock only in a necessary portion of data.

The read counter 40 generates a read pulse 4a and a phase signal 4b for a specific memory 10, holds input data 1a in the memory 10 with a write pulse 2a, and outputs it as output data 1b with a read pulse 4a. The timing signal 3a causes the multiplexing circuit 10A to
The output data 1b from the memory 10 and the additional bit 1c are multiplexed to create the output data 1d.

Further, the AND circuit 90A outputs the detection pulse 9a when detecting the overlap between the specific phase signal 2b for writing and the specific phase signal 4b for reading, and the SR latch circuit 90B holds the detection pulse 9a. A signal 9b requesting insertion of a stuff bit is input to the frame signal generation circuit 30 to control the tooth loss clock 3b,
Control to insert the stuff bit. When the stuff bit is inserted, the signal 3c for clearing the SR latch circuit is output.

The stuffing bit is inserted by such an operation, and whether it is stuffed or not is indicated by using a part of the additional bit described in FIG. FIG. 10 is a diagram for explaining the staff control operation of the conventional example. Figure is Figure 9
2 shows the phase state in the memory 10, the abscissa indicates the lapse of time t, the ordinate indicates the amount of lead / lag of the phase, and the dotted line indicates the criterion for stuff bit insertion.

The phase gradually changes due to the difference in frequency between the write pulse and the read pulse. When the judgment criterion is exceeded, a stuff bit is inserted and the phase is returned. As described with reference to FIG. 8, the position of inserting the stuff bit in the arrow in the figure is determined in the frame. Therefore, when the criterion is exceeded, the stuff bit is not inserted immediately but the stuff bit is inserted. Wait until the timing comes and insert at that position.

[0011]

In the above-mentioned conventional example, the missing of the clock for inserting the additional bit occurs asynchronously with respect to the specific phase of the memory regardless of the number of memory stages and the shape of the frame. Therefore, the influence of the additional bit insertion at each determination time is not constant.

Therefore, in the frame format as shown in FIG. 10 in which the judgment criterion is exceeded only for a short time, the detection becomes irregular, the waiting jitter becomes large, and the generation cycle becomes random.

Further, since a part of the additional bits is used to indicate whether or not to perform stuffing, a certain time is required from the decision to perform stuffing to the actual stuffing. Since the detection of whether or not to stuff in the next frame has already started, the stuff bit is likely to be inserted twice in succession. In that case, the phase returns more than necessary, the time until the insertion of the next stuff bit becomes long, and the stuff jitter has a large amplitude and a long cycle.

Further, on the receiving side of this data, after removing the additional bit and the stuff bit, the clock is regenerated by the phase locked loop (hereinafter referred to as PLL) circuit and the data is output through the memory. Since the circuit has the characteristics of a low-pass filter, jitter due to additional bits can be sufficiently suppressed because the repetition frequency is short, but queuing jitter and stuff jitter can be sufficiently suppressed when the amplitude is large and the repetition frequency is long. Instead, it remains in the output signal, causing the line quality to deteriorate.

The present invention reduces queuing jitter having a large amplitude and a random period, and jitter having a large amplitude and a long repeating period due to continuous stuffing, thereby maintaining high quality of a transmission line. Try to realize a staff control circuit.

[0016]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 100 is a digital stuff control circuit, and 10A is a multiplexing circuit that adds additional bits to a plurality of N pieces of data having a first clock frequency f1 and multiplexes them with a signal having a second clock frequency f2.
10 is a memory for temporarily writing input data,
Reference numeral 20 is a write counter that creates a write pulse to the memory 10 from an input clock whose frequency is the first clock frequency f1, and 30 is a second clock frequency f.
2 is a timing signal generating circuit for generating a frame pulse from the output clock of 2 and a tooth-missing clock for generating a clock only when data is required. Reference numeral 40 denotes a timing-missing clock generated by the timing signal generating circuit 30 in the memory 10. It is a read counter that creates a read pulse for reading the written data.

Reference numeral 50 denotes the output of the writing counter 20,
Is a subtraction circuit for subtracting the output of the read counter 40,
Reference numeral 60 denotes a determination circuit that determines whether or not the stuff bit needs to be inserted from the output of the subtraction circuit 50.
The subtraction circuit 50 performs subtraction with the count value of the read counter 40 indicating the 0 read phase, and the result is determined by the determination circuit 6.
When 0 is input and it is determined that the phase difference is smaller than a predetermined value, the timing signal generating circuit 30 is controlled to insert the stuff bit.

[0018]

In the figure, the write counter 20 generates a write pulse for writing the memory from the input clock, and outputs a counter value indicating the write phase of the memory 10 to input to one terminal of the subtraction circuit 50.

The timing signal generation circuit 30 is a frame timing signal for creating a frame from the output clock,
A toothless clock for memory reading is created and input to the reading counter 40.

The read counter 40 outputs a pulse for memory reading and a counter value indicating the read phase of the memory 10 from the missing clock and inputs it to the other terminal of the subtraction circuit 50.

Input data is written in the memory 10 by a write pulse and read by a read pulse, and the data output from the memory 10 by the multiplexing circuit 10A and the additional bit are multiplexed by a timing signal and output as output data.

When the subtraction circuit 50 performs subtraction between the counter value indicating the write phase and the counter value indicating the read phase and inputs the result to the judgment circuit 60 and detects that the phase difference is smaller than a predetermined value. , A control signal for performing stuffing is output, and the timing signal generation circuit 30 controls the tooth missing clock to control whether or not to insert the stuff bit. By such an operation, it is possible to suppress the jitter and improve the line quality.

[0023]

FIG. 2 is a diagram for explaining the signal flow of the present invention. The configuration of FIG. 2 is obtained by adding an FF circuit 20A to the configuration of the principle diagram.

In the figure, a write counter 20 is rotated by an input clock to generate a write pulse 2a and a phase signal 2b indicating the phase of the memory 10. The timing signal generation circuit 30 generates various timing signals 3a from the output clock and a toothless clock 3b having a clock only in a necessary portion of the data, and the read counter 40 outputs the read pulse 4a.
And a phase signal 4b indicating the phase of the memory 10 is generated.

The input data 1a is held in the memory 10 by the write pulse 2a, and the output data 1b is output by the read pulse 4a. The multiplexing circuit 10A multiplexes the output data 1b from the memory 10 and the additional bit 1c by the timing signal 3a to create the output data 1d.

Further, since the input clock and the output clock are asynchronous, the count value of the write counter 20 is synchronized with the output clock by the FF circuit 20A and output as the phase signal 2c.

The subtraction circuit 50 is the timing signal generation circuit 3
F when the specific timing signal 3d is input from 0
The phase signal 2c output from the F circuit 20A and the read counter 4
0 is subtracted from the phase signal 4b output, and the difference is output as a signal 5a.

The decision circuit 60 decides whether or not the signal 5a is larger than a preset value, and if it is smaller, outputs the control signal 6a for stuff control and controls the timing signal generation circuit 30. Insert the stuff bit.

FIG. 3 is a diagram for explaining an embodiment of the present invention. The figure shows an example of multiplexing three input data 1 to 3,
101 to 103 in the figure are digital stuff control circuits,
Numerals 11 to 1n are memories constituted by FF circuits (denoted by MM in the figure), and 10A are multiplex circuits (denoted by MUX in the figure), 1
0B is an n: 1 selector (shown as SEL in the figure), 21, 4
1 is a loop counter (indicated by LC in the figure), 22 and 42 are encoders (indicated by ENC in the figure), 23 is an FF circuit (indicated by FF in the figure), and 30 is a timing signal generation circuit (indicated by TMG in the figure). , 50 is a subtraction circuit (denoted by SUB in the figure), and 60 is a decision circuit (DET in the figure).

Here, the write pulse is created by the loop counter 21, and the encoder 22 converts the n pulses into a binary number to indicate the phase of the memories 11 to 1n. The memory 10 described in the principle diagram is composed of the memories 11 to 1n and the n: 1 selector 10B.

The FF circuit 23 is for changing the clock and is composed of m FF circuits. The subtraction circuit 50 does not perform normal subtraction, but determines the phase margin from the phase difference between the write pulse and the read pulse. Output the indicated value. This numerical value is input to the determination circuit 60, and when the phase difference is smaller than a predetermined value, the timing signal generation circuit 30 is controlled to insert the stuff bit.

In the embodiment shown in FIG. 3, a write pulse,
Although the encoders 22 and 42 are used to generate the read pulse, it is also possible to use this as a binary counter and use a decoder that converts a binary signal into a sequential pulse as a signal to the memory side. It is also possible to use the loop counters 21 and 41 for generating the write pulse and the read pulse, delete the encoders 22 and 42, and configure the subtraction circuit 50 to obtain the phase margin from the sequential pulse.

FIG. 4 is a diagram for explaining the staff control operation of the embodiment of the present invention. The thin arrow in the figure indicates the timing for determining the necessity of inserting the stuff bit, and the thick arrow indicates that the stuff bit has been inserted. As described above, according to the present invention, since the determination timing is the specific point of the data frame, the influence of the missing bit of the clock due to the additional bit insertion is the same every time, and the determination of each time accurately reflects the lead / lag of the phase of the memory. It is possible to insert an appropriate stuff bit. Due to such an operation, the waiting jitter due to the insertion of the stuff bit has a small amplitude and occurs almost evenly.

Therefore, on the receiving side, in the clock recovery of the PLL circuit, the effect of the low-pass filter can sufficiently suppress the jitter. FIG. 5 is a diagram for explaining the subtraction process according to the embodiment of the present invention. In the figure, the horizontal direction indicates the phase of the write pulse (denoted by W), and the vertical direction indicates the phase of the read pulse (denoted by R).

Here, for example, when W = 0 and R = 0, the phase margin is zero. Further, when W = 1 and R = 0, the phase margin is 1. On the contrary, when W = 0 and R = 1, the phase margin is the maximum n-1.

FIG. 6 is a diagram (1) for explaining another embodiment of the present invention. The figure shows an example in which four input data 1 to 4 are multiplexed, and 101 to 104 in the figure are digital stuff control circuits. Here, as the memory 10 described in the principle diagram, the dual address space is n or more. This is an example of using the portram 10C. In this configuration, since writing and reading to and from the dual port RAM 10C are performed by addresses, the counters 21A and 41A only use binary counters, and the encoders 22 and 42 or decoders are not necessary.

FIG. 7 is a diagram (2) for explaining another embodiment of the present invention. Here, the data is not multiplexed and only the additional bits are inserted, and the configuration is used when the existing line is taken into the new synchronous network.

The difference from the embodiment of FIG. 3 lies in the loop counters 21B and 41B, which generate write pulses and read pulses and at the same time generate specific phase signals ΦX and ΦY.

Further, the NOR circuits 71 and 72 constitute the SR latch circuit 70, and the specific phase signals ΦX and ΦY are SR.
The duty ratio signal is generated by inputting it to the latch circuit 70. This duty ratio signal is sent to the FF circuit 73.
Is synchronized with the output clock and the counter 80 performs up-counting / down-counting to integrate the duty-ratio signal and determine whether the phase of the memory is advanced or delayed.
A control signal indicating whether or not the stuff bit is inserted by detecting 0 is created.

By such an operation, the missing tooth due to the addition of the additional bit is canceled by the integration effect of up-counting / down-counting by the counter 80, and the lead / lag of the phase of the memory can be accurately determined. It is possible to suppress the jitter.

In the above description, the stuff bit is one bit, but it is also possible to set the stuff bit to a plurality of N bits and insert n bits among them. In this case, the determination circuit 90 may control how many bits of a plurality of N bits are inserted.

[0042]

According to the present invention, when the frequency is adjusted by inserting stuff bits in a frame format in which a large number of additional bits are inserted, the amplitude of queuing jitter or stuff jitter is reduced and the repetition cycle is also shortened. Since it is possible to suppress the jitter remaining in the data output on the receiving side,
High line quality can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram for explaining a signal flow of the present invention.

FIG. 3 is a diagram illustrating an embodiment of the present invention.

FIG. 4 is a diagram illustrating a staff control operation according to the embodiment of this invention.

FIG. 5 is a diagram illustrating subtraction processing according to the embodiment of this invention.

FIG. 6 is a diagram (1) for explaining another embodiment of the present invention.

FIG. 7 is a diagram (2) illustrating another embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a frame format.

FIG. 9 is a block diagram illustrating a conventional example.

FIG. 10 is a diagram illustrating a staff control operation of a conventional example.

[Explanation of symbols]

 100, 101-104 Digital stuff control circuit 10, 11-1n memory 10A Multiplexing circuit 10B n: 1 selector 10C Dual port RAM 20 Write counter 20A, 23, 73 FF circuit 21, 41, 21B, 41B Loop counter 21A, 41A, 80 counter 22, 42 encoder 30 timing signal generation circuit 40 read counter 50 subtraction circuit 60, 90 determination circuit 70, 90B SR latch circuit 71, 72 NOR circuit 90A AND circuit

Claims (2)

[Claims] 1. In digital transmission, a multiplexing circuit (1
0A) and a plurality of first clock frequencies (f1) (N)
Is a digital stuff control circuit (100) for adding an additional bit to the data of (1) and multiplexing it with the signal of the second clock frequency (f2). A write counter (20) that creates a write pulse to the memory (10) from an input clock of a first clock frequency (f1), and a frame pulse and data from an output clock of a second clock frequency (f2). Is written in the memory (10) from a timing signal generating circuit (30) for generating a toothless clock that generates a clock only when necessary, and a toothless clock generated by the timing signal generating circuit (30). A read counter (40) for creating a read pulse for reading data, an output of the write counter (20), A subtraction circuit (50) for subtracting the output of the read / write counter (40) and a determination circuit (60) for determining whether or not stuff bit insertion is necessary from the output of the subtraction circuit (50). Digital stuff control circuit. 2. A memory (10) for temporarily writing input data, and a write counter (20) for creating a write pulse to the memory (10) from an input clock having a frequency of a first clock frequency (f1). A timing signal generating circuit (30) for generating a frame pulse and a toothless clock for generating a clock only when data is required from an output clock having a frequency of a second clock frequency (f2), and the timing signal generating circuit A read counter (40) for creating a read pulse for reading the data written in the memory (10) from the missing clock generated by (30), the write counter (20), and the read counter (4
0) a pulse of a specific phase as an input, and an S-R latch circuit (70) for outputting a lead / lag state of writing and reading to and from the memory (10) as a duty ratio; and the S-R latch circuit (70). ) Is used as an up / down control input, and a counter (80) for counting the lead / lag state and a judgment circuit (90) for judging whether or not stuff bit insertion is necessary from the output of the counter (80) are provided. Digital stuff control circuit characterized by.