JPH0661417A - Semiconductor device, electronic circuit device, and method and device for manufacturing them - Google Patents

Abstract

PURPOSE:To form a plurality of divided semiconductor devices by sealing the entire surface of the part where the conductive pattern of an electrically insulating substrate having a large area is formed with a sealing resin so that the surface can become smooth. CONSTITUTION:Semiconductor elements 2 are firmly fixed to prescribed parts of conductive patterns 1A with solder layers 3. After coating the elements 2 with a precoating resin, an electrically insulating substrate 1 having a large area is supported by means of a frame-like upper and plate-like lower casting mold members 6 and 7 so that a liquid sealing resin cannot leak out. After holding the substrate 1 between the members 6 and 7, the sealing resin is poured in the member 6 until the thickness of the resin reaches 1.5mm and vacuum- defoaming is performed. Then the resin is hardened by heating while the members 6 and 7 are horizontally maintained. After obtaining a molded product by removing the members 6 and 7, a plurality of divided semiconductor devices are obtained by applying an external force to the substrate 1 along the scribe line 1C of the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, an electronic circuit device, and a small, lightweight and thin semiconductor device which is formed by resin-sealing a semiconductor element fixed to a conductive pattern of an electrically insulating substrate, and an electronic circuit device. It relates to their manufacturing method.

[0002]

2. Description of the Related Art In general, converter power supplies and the like are required to be smaller and smaller, and development of on-board power supplies (OBP) by surface mounting method is being advanced. However, in order to make a large-capacity converter into a compact OBP, some semiconductor parts used in these converters are too large, so that the whole cannot be miniaturized. In particular, semiconductor components such as Schottky barrier diodes, bipolar transistors, and MOSFETs, which have a relatively large capacity, generate a large amount of heat from the semiconductor elements. Therefore, a metal heat sink and an external lead are simultaneously transfer-molded. Greater heat dissipation effect. However, because of this, the parts become large in size, and it is difficult to mount them on the board and make them smaller.

These Schottky barrier diodes,
It is optimal for downsizing if a semiconductor element, which is a bare chip of a semiconductor component such as a bipolar transistor or MOSFET, can be mounted on the substrate as it is and bonded and molded. The reliability such as impact resistance and moisture resistance is insufficient and there is room for consideration. Also, many circuit components are surface-mounted components that are resin-sealed, and if some of them are bare chips, they must be mounted separately and processed in different steps, which requires expensive dedicated equipment and increases the number of manufacturing steps. However, it has the drawback of increasing costs. There is also a method in which the above semiconductor element is soldered to an alumina substrate or the like having good heat dissipation, wire bonding is separately performed with an electrode pad or the like with a metal wire, and then a sealing resin is dropped to seal the semiconductor element. is there. This substrate is suitable for miniaturization because the back surface is an electrode that is conductive with a via hole. However, since the surface of these cured products of the sealing resin is molded into a convex lens shape and is not flat, there is a drawback that automatic mounting by vacuum suction cannot be performed.

As described above, electronic components used for surface mounting are required to be small, thin, lightweight, and low in cost in addition to improving quality. Generally, capacitors, resistors,
Circuit components such as coils, transformers, ICs, diodes, and transistors are designed to be easily mounted on the board, and the manufacturing method is shifting to surface mounting circuit components at high speed using an automatic insertion machine. . In this method, a cream solder is applied to a predetermined position of a conductive pattern of a substrate, a circuit component is mounted thereon and temporarily adhered, and soldering is performed by a reflow heat treatment or the like. In the surface mounting method, circuit components are sucked and mounted under reduced pressure, so it is inevitable that the shape is lightweight and the surface is flat.
To maintain quality, the exterior is made of epoxy resin, which has excellent electrical insulation properties, and mass-produced by the transfer molding method.

Referring to FIG. 7, a general lead wire type surface mount type semiconductor device will be described. A pair of lead electrodes 50 and 5 whose tip portions are bent to form a flat surface.
The semiconductor element 52 is soldered to one flat surface of 1,
The semiconductor element 52 is connected to the other lead electrode 51 by an internal lead terminal 53.
The flat portion 1 and the semiconductor element 52 are molded with a sealing resin 54. In addition, in order to reduce the size and thickness, save labor, and reduce the number of processes, bare chips and flip chips are directly mounted on the conductive pattern of the substrate by die bonding, etc.
There is also a method in which a conductive pattern including an electrode and a wiring pattern is bonded if necessary, and an epoxy resin having a good insulating property is dropped and coated. As an example of this,
There is one described in Japanese Patent No. 62-208652. This is Figure 8
First, as shown in FIG.
2, the semiconductor element 63 is adhered, and the thin metal wire 63 is used for electrical connection, and then the mold member 66 is placed on the dam 65.
Then, the sealing resin 67 is injected into the package from the groove 64 of the dam 65. After the encapsulating resin 67 is cured, the mold member 66 is removed to obtain a resin-encapsulated semiconductor device.

[0006]

However, in the case of the semiconductor device of FIG. 9, since the pair of lead electrodes 50 and 51 are bent in a U-shape, there is a great difficulty in reducing the thickness. Since it is necessary to sequentially perform transfer molding one by one including a part of the pair of lead electrodes 50 and 51, a special transfer molding device is required and mass production is difficult. Furthermore, since the pair of lead electrodes 50 and 51 are bent and used in a U-shape, it is difficult to reduce the size. Next, in the case of the one shown in FIG.
It is not suitable for mass production because it requires a step of placing a mold member 66 on top and injecting the sealing resin 67 into the package from the groove 64 of the dam 65. Moreover, the substrate is enlarged by the area of the dam 65. Since there is no choice but to do so, there is a problem in terms of miniaturization. Although not shown, in a power semiconductor device in which a lead wire extends from a sealing resin, a plurality of deburring steps including deburring at the root of the lead wire must be performed after sealing with the resin. However, it was difficult to reduce the size of semiconductor devices. The present invention is highly compact, thin, and lightweight, and is highly mass-producible, especially when a semiconductor element such as a Schottky barrier diode having a relatively large capacity, a bipolar transistor, a field effect transistor, or another circuit component is resin-sealed. , A thermal shock resistance, a moisture resistance, a PCT test, and the like, and an object of the present invention are to provide a manufacturing method having good characteristics.

[0007]

In order to solve such a problem, in the first invention, a plurality of predetermined conductive patterns are provided on one main surface, and at least the predetermined conductive pattern is not applied. A large area electrically insulating substrate having a plurality of scribe lines formed on one main surface is provided, and after a semiconductor element is fixed to each of the predetermined conductive patterns, the electrically conductive pattern of the large area electrically insulating substrate is provided. The whole surface of the part where the is formed is sealed with a sealing resin so that the surface is flat, and if necessary, a groove of a predetermined depth is formed along the position corresponding to the scribe line of the sealing resin. ing. A second aspect of the present invention is a large area electrical insulating material having a plurality of predetermined conductive patterns on one main surface and having a plurality of scribe lines formed on at least one main surface so as not to cover the predetermined conductive pattern. A substrate is provided, and after fixing one or more semiconductor elements to each of the predetermined conductive patterns, the large-area electrically insulating substrate is sealed so that the surface is flat over the entire surface of the conductive pattern formed portion. Sealing with a sealing resin, and during curing of the sealing resin, an external force is applied to divide the electrically insulating substrate and the sealing resin along the scribe line to separate individual semiconductor devices and electronic circuit devices. It has gained.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 shows an example of a transistor. 1 is a large area made of an inorganic alumina, aluminum nitride, ceramics such as glass, or a metal plate such as aluminum or copper to which an insulating film such as polyimide is adhered. It is an electrically insulating substrate, and a predetermined conductive pattern 1A is regularly formed in a matrix on one main surface. Another electrode pattern 1B corresponding to each of the conductive patterns 1A is formed on the other main surface, and the conductive pattern 1A and the electrode pattern 1B are connected to each other as desired by an ordinary via hole (not shown). ing. The conductive patterns 1A and the electrode patterns 1B are formed as electrodes for transistors by printing a conductive paste of copper, tungsten or the like by silk printing and baking. The electrode pattern 1B has a function as an external electrode soldered to a printed circuit pattern such as a printed circuit board (not shown). The scribe lines 1C are formed in a grid pattern on the surface on which the electrode pattern 1B is formed, the other surface, or both surfaces so that the conductive pattern 1A and the electrode pattern 1B are not covered. This scribe line 1C
Is for facilitating the splitting of a large-area molded product later, and is a group of minute cracks formed along a desired line by mechanically formed V-shaped grooves or the like by the action of ultrasonic waves, It is made of a weakened material in a line shape, and it is often indistinguishable from the outside except for grooves.

Next, the semiconductor element 2 is fixed to a predetermined portion of each conductive pattern 1A with a solder layer 3, and then a metal wire 4 is wire-bonded so that the emitter electrode and the base electrode of the transistor are fixed to the predetermined portion of the conductive pattern 1A. Connecting. Next, although not shown, normal passivation is performed with a precoat resin such as polyimide varnish, and then all conductive patterns 1A are formed with a specific sealing resin 5.
Then, the semiconductor element 2 is uniformly sealed, and then divided into individual semiconductor devices. At this time, if the scribe line 1C is formed on the main surface of the large-area electrically insulating substrate opposite to the surface covered with the sealing resin 5, the scribe line 1C can be easily divided. If it is formed only on the covered surface, it is very difficult to divide. Here, the conductive pattern 1A and the electrode pattern 1B shown in FIG. 1 are for the single semiconductor element 2, but each conductive pattern 1A and the electrode pattern 1B include one or more semiconductor elements, other active elements and passive elements. It is also possible to easily form a circuit pattern suitable for the circuit configuration such as a hybrid integrated circuit or a power supply circuit in which at least one element is mounted, and after mounting and bonding each of these elements and making a predetermined connection, the same is done. It is also possible to uniformly seal them and then divide them to obtain individual electronic circuit devices.

Next, the resin sealing will be described in detail. First, as the sealing resin 5, epoxy resin, phenol
An electrically insulating resin such as a resin or a polyester resin is suitable, and a thermosetting resin having a composition that is gradually hardened by heating is preferable. For the reasons described below, semi-curing or B-stain
A resin that passes through a di-state, particularly one based on an epoxy resin, is suitable, and acid anhydrides, phenol resins, aromatic amines, imidazoles, etc. can be used as curing agents and catalysts. In addition, pigments, fillers and additives can be used to maintain the properties. Quartz powder, alumina, etc. can be used as the filler, and generally, the content of about 60% or more is preferable. Improving workability such as adhesion to the electrically insulating substrate 1, splittability, releasability, flowability, low temperature curing, defoaming, low thixotropy, low expansion, low content of impurity ions, etc. Is also required. As the thermoplastic resin, PPO or liquid crystal polymer can be used, but it is necessary to melt and inject it.

Next, a concrete example of the epoxy resin-based sealing resin will be described. Epicron # 850 (Dainippon Ink and Chemicals) 15 parts Chisso Knox # 221 (Nissan Chisso) 10 parts Chisso Knox # 221 (Nissan Chisso) 10 parts Reactive Diluent GAN (Nippon Kayaku) 5 parts Hiyu-Rex Y-60 ( Tatsumori) 133 parts Epicron # B-4136 (Dainippon Ink and Chemicals) 27 parts 1B2MZ (Shikoku Kasei) 0.5 parts Defoamer (TSA-750 (Toshiba Silicone) 0.01 parts Total 190.51 parts like this The compounded product obtained in 1 above was thoroughly mixed with a stirrer and defoamed in a vacuum.

Next, a method of producing a molded product of the sealing resin having a flat upper surface by using the sealing resin thus treated will be described. As described above, after covering the semiconductor element 2 or the like with a precoat resin such as a polyimide varnish as necessary, a large-area electrically insulating substrate 1 is formed into a frame shape having a height of 5 mm as shown in FIG. It is supported by the upper mold member 6 and the plate-shaped lower mold member 7 to prevent the sealing resin from leaking. Here, the mold member is not limited to metal, but may be a material such as rubber or plastic. In addition, it is convenient to use a mold that has been subjected to a mold release treatment or a mold of a silicone resin in order to improve the mold release property. If necessary, sealing and packing processes are performed to prevent resin leakage, and a pressure mechanism for applying the required pressure is also provided.

After sandwiching the peripheral portion of the large-area electrically insulating substrate 1 between the upper mold member 6 and the lower mold member 7 as described above,
The liquid encapsulating resin as described above is poured over the entire surface of the frame until the thickness becomes approximately 1.5 mm, placed in a vacuum device (not shown), and vacuum defoamed. Since the air in the sealing resin has been defoamed in advance, the defoaming time at the time of sealing can be shortened. The vacuum referred to here is a pressure reduction that allows air in the sealing resin to be removed from the resin, and a vacuum degree of at least about 100 mmHg is required. The liquid sealing resin is injected under normal pressure or vacuum. Of course, vacuum defoaming may be performed after injecting undefoamed resin. If this defoaming step is not performed, bubbles will often remain on the surface of the sealing resin. And keep the mold member horizontal, 2
Vacuum degassing is performed for 5 minutes at mmHg, and this is heated in an atmosphere of 160 ° C. for about 2 hours to be cured. Next, after removing the mold members 6 and 7 to obtain a molded product, an external force is applied along the scribe line 1C on the back surface of the electrically insulating substrate 1 to obtain a semiconductor device individually or divided into a plurality of parts. it can. Here, the heat curing temperature depends on the type of sealing resin, but in transfer molding, the mold member temperature is 18
It is suitable for mass production in the range of 0 to 250 ° C and the time of 2 to 10 minutes. In the casting method, the temperature is 80 to 180 ° C.
Therefore, a suitable time is about 10 minutes to 2 hours.

When the thickness of the sealing resin 5 is approximately 2 mm or less, it can be easily divided manually along the scribe line 1C without adversely affecting the semiconductor elements, but the thickness of the sealing resin 5 is approximately 2 mm. When it exceeds, as shown in FIG. 3, it is preferable to form a groove 5A having a constant depth such as a concave shape, a linear shape, or a V-shaped cut at a position corresponding to the scribe line 1C on the back surface of the electrically insulating substrate 1. The grooves 5A formed in a grid pattern have a depth such that the thickness from the bottom to the surface of the electrically insulating substrate 1 is approximately 2 mm or less. The thickness of the sealing resin 5 is generally 1 to 5 mm, although it depends on the electronic circuit device such as a semiconductor device and a power supply. ， In some cases, the electrical characteristics may be adversely affected. Therefore, by providing the grid-shaped grooves 5A at the location of the sealing resin 5 corresponding to the scribe line 1C on the back surface of the electrically insulating substrate 1, it is possible to obtain a flat large-area molded product having relatively small deflection.

Since this large-area molded product is formed by pouring the sealing resin over almost the entire surface of the electrically insulating substrate 1, its upper surface is smooth, and naturally the upper surface of the divided semiconductor device is also smooth. However, the divided side wall surface below the groove 5A is rougher than the upper surface, indicating that the side wall surface was easily divided. As a simple method to make the groove 5A in a large area molding,
A pressing mold member 8 as shown in FIG. 4 is used to pressurize the sealing resin 5 before curing, or a liquid sealing is performed in a state where the pressing mold member 8 is previously set to the upper mold member 6 and the lower mold member 7. There is a method of pouring a stop resin. The pressing mold member 8 has convex portions formed in a grid pattern at the same intervals as the scribe lines 1C of the electrically insulating substrate 1, that is, a surface on which a ridge portion 8A is formed. The part surrounded by the shore 8A is the shore 8
It is lower than A, and the shape and height of the ridge 8A correspond to the groove 5A to be formed. The material of the pressing mold member 8 is the same as that of the upper mold member 6 and the lower mold member 7. Although not shown here, in order to perform the resin sealing reasonably, when the sealing resin is pressed by the pressing mold member, the upper mold member and the pressing mold member should be located at a place where the excess sealing resin can escape. You can make it between and. Furthermore, a smooth surface with few bubbles can be obtained by setting the pressing mold member in a vacuum. If necessary, the surfaces of these mold members may be patterned or marked such as marks.

A specific example of the resin sealing method will be described below. [Specific Example 1] A plurality of conductive patterns 1 as shown in FIG.
An A-printed 0.4 mm thick electrically insulating substrate 1 made of alumina, on which a plurality of bare chip semiconductor elements 2 having a relatively large current capacity are mounted, is set as a mold member, and
The thickness of the sealing resin is set to 1 mm. Using a transfer mold device, a transfer mold resin MP-3000 (Nitto Denko product) is heated and melted, and then poured into the entire surface of the mold member. Mold member temperature is 180 ℃
And heat for 2 minutes to cure. When the cured product was removed from the mold member frame, a large area molded product having a flat entire surface of the sealing resin 5 as shown in FIG. 5 was obtained. When divided along the scribe line 1C attached to the back surface of the electrically insulating substrate 1, a semiconductor device having a smooth top surface and four rough side wall surfaces was obtained. This semiconductor device has a mounting area of ⅓ to ¼, as compared with a conventional element having a similar current capacity.
The thickness was reduced to less than 1/2, which was extremely small.

[Specific Example 2] Opposed to a scribe line formed on the back surface of a 0.635 mm thick electrically insulating substrate made of alumina in which predetermined circuit components are mounted and connected to a plurality of identical circuit patterns. The mold member as shown in FIG. 4 which gives a V-shaped groove having a depth of about 2 mm to the sealing resin as shown in FIG. 3 is aligned with the position so that the thickness of the sealing resin becomes 4 mm. set. The sealing resin of the above formulation example is press-fitted into the mold member to mold the sealing resin to a thickness of 4 mm. This is heated at a mold member temperature of 150 ° C. for 10 hours to be cured. When the cured product is removed from the mold member frame after curing, the grid-shaped grooves 5 are formed on the surface of the sealing resin 5 as shown in FIG.
A large-area molded product in which A was formed was obtained. When divided along the lattice-shaped grooves 5A, a resin-sealed electronic circuit device having a smooth upper surface and four divided side wall surfaces that were rougher than the upper surface was obtained. The electronic circuit device thus obtained maintained the initial electrical characteristics, no adverse effects due to resin sealing and mechanical division were observed, and a good electronic circuit device was obtained. This electronic circuit device has a mounting area of ⅓ to ¼ and a thickness of almost ½, which is extremely small and lightweight, as compared with a conventional similar device. The resin-sealed semiconductor device and the resin-sealed electronic circuit device thus obtained did not require any deburring step.

In the above embodiments, the case where the large area molded product is divided after the sealing resin is completely cured has been described. However, as the sealing resin, it is semi-cured or thermoset through the B stage state. An example will be described in which a heat-resistant resin is used, and when the sealing resin reaches a semi-cured state (90% or less of the completely cured state) in the process of thermosetting, heating is stopped and the resin is divided. In this case, a large-area molded product can be divided with an external force that is considerably smaller than that after the sealing resin is cured. In this embodiment, a plurality of semiconductor elements are mounted on the electrically insulating substrate 1 made of alumina on which a plurality of circuit patterns are printed in the same manner as described above.
After mounting circuit components such as resistors, capacitors, and inductors (some of which are bare chips) and fixing them, make a predetermined connection to form a power supply circuit, and then add 2 mm high silicone rubber to it. Place the (mold) mold made of them, and bring them into close contact. A large area molded product was obtained by injecting the epoxy-based encapsulating resin of the above formulation example to a height of 2 mm and heating it in an atmosphere of 120 ° C. for 15 minutes while vacuum defoaming and semi-curing. . The heat distortion temperature at the time of complete curing of this sealing resin is 165 ° C.
However, the heat distortion temperature at the time of semi-curing at this time was 72 ° C. Then, if you remove the (rubber) mold made of silicone rubber,
A flat large-area molded product having a height of the sealing resin of 2 mm was obtained, and could be easily split by dividing along the scribe line on the back surface of the electrically insulating substrate 1.

Next, some specific examples will be described. [Specific Example 1] A plurality of conductive patterns 1 as shown in FIG.
A plurality of semiconductor elements 2 mounted on a 0.5 mm thick electrically insulating substrate 1 made of alumina printed with A is set in an upper mold member and a lower mold member having a height of 3 mm, and liquid epoxy-based encapsulation is performed. The resin was poured into the entire surface of the mold member to make it overflow and the height was set to 3 mm. Then 1 at 758 mmHg
Vacuum degassing is performed for 0 minutes, and this is heated in an atmosphere of 80 ° C. for 60 minutes to be semi-cured. The heat distortion temperature of this resin when it is completely cured is approximately 165 ° C, and the heat distortion temperature when it is half cured is 64 ° C.
Met. The height of the sealing resin thus obtained is 3
A large-area molded product having a flat millimeter had almost no bending and could be easily broken by dividing along the scribe line 1C on the back surface of the electrically insulating substrate 1. Then, the divided individual semiconductor devices are heated at an ambient temperature of about 150.degree.
It was heated for about 0 hours and completely cured. The side wall surface divided in this manner was rougher than the smoothness of the upper surface, but was finely cracked along the scribe line 1C, and could be sufficiently used as a semiconductor product.

[Specific Example 2] Opposed to a scribe line formed on the back surface of an electrically insulating substrate made of alumina and having a thickness of 0.4 mm, in which predetermined circuit components are mounted and connected to a plurality of identical circuit patterns. A mold member as shown in FIG. 4, which gives a V-shaped groove having a depth of about 1 mm to the sealing resin as shown in FIG. 3, is aligned with the position, and the thickness of the sealing resin is 3 m.
Set so that m. Silica powder 7 like compounding example
An epoxy / acid anhydride / imidazole-based encapsulating resin containing 0% is press-fitted into the mold member to mold the encapsulating resin to a thickness of 3 mm. This was heated at a mold member temperature of 160 ° C. for 10 minutes to be semi-cured, and the large-area molded product was removed from the mold member frame in the semi-cured state. This large-area molded product had a slightly smaller bending than that of Example 1, and the division along the lattice-shaped grooves 5A was easier. The heat distortion temperature of this resin at the time of complete curing was 165 ° C, whereas the heat distortion temperature at the time of semi-curing was 130 ° C. Each of the semiconductor devices thus obtained maintained the initial electrical characteristics, and no adverse effects due to resin encapsulation and mechanical division were observed. As a result of various other tests on the splitting of the sealing resin in a semi-cured state, the sealing resin used in the above examples is in a semi-cured state at a temperature of 80% or less of the thermal deformation temperature at the time of complete curing, It has been found that it can be easily cracked in the semi-cured state, preferably at a temperature below 50% thereof. Also, in this case, the mechanical stress at the time of division can be reduced,
It was also found that since the heat curing is performed at a temperature lower than that during complete curing, the mechanical stress during curing of the encapsulating resin is reduced, and therefore the effect on circuit components such as semiconductor elements can be sufficiently reduced.

Although the thermosetting resin is used in the above embodiments, a semiconductor device using an active energy ray curable resin such as an ultraviolet ray curable resin or an electron beam curable resin which is cured by an active energy ray, or A method and apparatus for manufacturing an electronic circuit device will be described. First, to give a typical composition of the active energy ray-curable resin, as the resin composition, an alkyd resin having an acrylic acid group, an allyl group, an itaconic acid group, an unsaturated group such as a conjugated double bond, or an acrylic resin is introduced. Resin, urethane resin, polyurethane resin, epoxy resin, etc. may be mentioned. As other constituents, oligomeric monomers are used for viscosity control, photopolymerization initiators and thermosetting catalysts are also used, and ordinary pigments, dyes,
Fillers and additives are added. If necessary, a resin such as a thermosetting resin that is hard to react with active energy rays can be used together. As a concrete example of the composition of the ultraviolet curable resin, Gocerac UV-7000B (manufactured by Nippon Synthetic Chemical Industry Co., Ltd.) 66 parts by weight TMPTA (trimethylpropane triacrylate) 30 parts by weight Irgacure 651 (manufactured by Ciba Geigy) 4 parts by weight ── ──────── is mentioned. 100 parts by weight

Next, using the ultraviolet curable resin having such a composition example, a manufacturing apparatus for encapsulating a plurality of electrically insulating substrates 1 having a large area as described in the above embodiments in the form of islands. This will be described with reference to FIG. FIG. 5 (A),
(B) shows a front view and a side view of the pressing mold member 8 constituting a part of the manufacturing apparatus, which is made of a plastic resin such as silicone resin or acrylic resin, or a substantially transparent material such as glass. Holding mold member 8
Consists of a base portion 8A and a holding portion 8B. Holding part 8
B has a pressing surface 8B1 having substantially the same size as the surface surrounded by the inner wall of the frame-shaped upper mold member 6 shown in FIG.
On the pressing surface 8B1, ridges 8B2 having a V-shaped cross section are formed in a grid pattern in a pattern matching the grid scribe lines formed on the large-area electrically insulating substrate 1. The height of the ridge 8B2 determines the thickness of the sealing resin formed on the large-area electrically insulating substrate 1, that is, the thickness of the sealing resin is substantially equal to the height of the ridge 8B2. In addition, through holes 8B for releasing excess sealing resin are provided at the four corners of the pressing portion 8B.
3 are formed, and the through holes 8B3 are formed in the base portion 8A.
To each of the through holes 8A1 formed in.

As shown in FIG. 2C, the upper mold member 6 is a large-area electrically insulating substrate 1 along the lower part of the inner wall.
6A is cut away, and therefore the large-area electrically insulating substrate 1 set on the flat surface of the lower mold member 7 is cut away from the lower mold member 7 and the upper mold member 6A. It is held tightly by the wall of. In such a state, the ultraviolet curable resin (not shown) of the above formulation example is injected into the upper mold member 6 and degassed in vacuum. After that, the pressing surface 8B1 of the pressing portion 8B is turned downward in FIG.
The pressing portion 8B of the pressing mold member 8 is pushed in, and the ridge 8B2 having a V-shaped cross section is held in a state of reaching the surface of the large-area electrically insulating substrate 1 (FIG. 6). In this state,
Ultraviolet rays are irradiated from above the pressing mold member 8. When the height of the grid-shaped ridges 8B2 is approximately 1.5 mm, that is, when the thickness of the sealing resin 5 is approximately 1.5 mm, the metal halide lamp (120 W / cm) is approximately 10 mm from the upper surface of the sealing resin 5.
Irradiation was carried out at a position with a height of cm, and the material was allowed to pass 10 times at a speed of 6 m / min for good curing. Thereafter, the large-area electrically insulating substrate 1 is removed from the mold member, and an external force is applied to the large-area electrically insulating substrate 1 scribe line 1C.
Thus, a very small and thin resin-encapsulated semiconductor device or resin-encapsulated electronic circuit device in which the encapsulating resin rises almost vertically from the peripheral edge of each electrically insulating substrate was obtained. The resin-encapsulated semiconductor device and resin-encapsulated electronic circuit device thus obtained have a mounting area of 1/3 to 1 as compared with similar devices.
/ 4, the thickness is almost 1/2, which is very small and lightweight. Also, no deburring process of the sealing resin is required.

Next, FIG. 7 uses a large-area electrically insulating substrate 1 as shown in FIG. 1, and mounts a semiconductor element or the like on the surface of the electrically insulating substrate on which the scribe line 1C is formed and seals it with resin. It is an example. In this case, a pressing mold member 8 having a flat top and a narrow width of the ridge 8B2 is used. By using the mold member 8 as described above, a very small and thin resin-sealed semiconductor device or resin-sealed electronic circuit device in which the sealing resin rises vertically from the peripheral edge of the substantially electrically insulating substrate is provided. Obtainable.

Next, FIG. 8 shows a bare chip of a planar transistor suitable for being applied to the semiconductor device as described above. This planar transistor has an n-type semiconductor grown on an n ⁺ semiconductor substrate 10 having a high n-type impurity concentration.
N ^- epitaxial layer 11 having sufficiently low type impurity concentration,
A p ⁺ emitter region 12 having a high p-type impurity concentration formed in the epitaxial layer 11 and an n ⁺ base region 1 having a high n-type impurity concentration formed in the semiconductor region 12
3, a collector electrode 14 formed on the exposed surface of the semiconductor substrate 10 in a hole extending at least to the surface of the semiconductor substrate 10, a collector bump electrode 15 formed on the collector electrode 14, and an emitter region 12 so as to form ohmic contact. From the emitter electrode 16 and the emitter bump electrode 17 thereon, the base electrode 18 formed to make ohmic contact with the base region 12, the base bump electrode 19 formed thereon, and the lateral resistance reducing metal film 20. Become. The feature of this planar type transistor is that the collector bump electrode 15 and the emitter bump electrode 1
7 and the base bump electrode 19 are all on the same surface, and their heights are all at the same level.

The conductive pattern of the electrically insulating substrate 1 shown in FIG. 1 is printed in advance so as to coincide with the positions of the collector bump electrode 15, the emitter bump electrode 17, and the base bump electrode 19, and the collector pattern is applied to the conductive pattern. By fixing the bump electrode 15, the emitter bump electrode 17, and the base bump electrode 19 with cream solder or the like, wire bonding is unnecessary and problems associated with wire bonding can be avoided. Similarly, if parts such as a diode, an FET, a thyristor, a resistor, and a capacitor provided with all electrodes on one main surface side are used, an inexpensive, compact, and thin resin-sealed semiconductor device that does not require wire bonding is used. It is possible to mass-produce electronic circuit devices such as power supplies. Each scribe line 1C on the back surface of the electrically insulating substrate 1 does not necessarily have to be formed so as to surround a single conductive pattern 1A, and a plurality of conductive patterns 1A may be collectively formed as one unit to form a scribe line. Good. Further, the electrically insulating substrate may be a multi-layer substrate in which desired circuit patterns and conductive patterns are formed in advance, and the electrically insulating substrate is provided with wedges or holes to improve adhesion of the sealing resin. Is also effective.

[00027]

As described above, according to the present invention, a very small, thin, lightweight, inexpensive resin-encapsulated semiconductor device that does not require deburring of the encapsulating resin, or a small power source can be used. Electronic circuit devices can be easily mass-produced with simple and inexpensive equipment, and the practical effects are extremely large.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. Figure 2
It is a figure for demonstrating one Example of this invention. Figure 3
FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a diagram for explaining one embodiment of the present invention. FIG. 5 is a diagram showing an embodiment of the present invention. FIG. 6 is a diagram showing an embodiment of the present invention. FIG. 7 is a diagram showing an embodiment of the present invention. FIG. 8 is a diagram for explaining one embodiment of the present invention. FIG. 9 is a diagram showing a conventional example. FIG. 10 is a diagram showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Electrically insulating substrate 1A ... Conductive pattern 1B ... Electrode pattern 1C ... Scribing line 2 ... Semiconductor element 3 ... Solder layer 4 ... Metal wire 5 ... Sealing resin 6 ... ..Upper mold member 7 ... Lower mold member 8 ... Pressing mold member 10 ... Semiconductor substrate 11 ... Epitaxial layer 12 ...
Emitter region 13 ... Base region

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[Procedure amendment]

[Submission date] March 3, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

Referring to FIG. 10 , a general lead wire type surface mount semiconductor device will be described. A pair of lead electrodes 50 whose tip portions are bent so as to form a flat surface,
A semiconductor element 52 is soldered on one flat surface of 51, and the semiconductor element 52 is connected to the other lead electrode 51 by an internal lead terminal 53.
The flat portions 0 and 51 and the semiconductor element 52 are molded with a sealing resin 54. In addition, in order to reduce the size and thickness, save labor, and reduce the number of processes, a bare chip or flip chip is directly mounted on the conductive pattern of the substrate by a die bonding method or the like and bonded, and if necessary, a conductive pattern including electrodes and wiring patterns. There is also a method in which the epoxy resin with good insulation is dropped and coated by performing bonding on the surface. An example of this is described in JP-A-62-208652. This is as shown in FIG.
The semiconductor element 63 is bonded to the
Electrical connection is made by the thin metal wires 63, a mold member 66 is then placed on the dam 65, and the sealing resin 67 is injected into the package from the groove 64 of the dam 65. After the encapsulating resin 67 is cured, the mold member 66 is removed to obtain a resin-encapsulated semiconductor device.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

However, in the case of the semiconductor device of FIG. 10 , since the pair of lead electrodes 50 and 51 are bent in a U-shape, there is a great difficulty in reducing the thickness. Since it is necessary to sequentially perform transfer molding one by one including a part of the pair of lead electrodes 50 and 51, a special transfer molding device is required and mass production is difficult. Furthermore, since the pair of lead electrodes 50 and 51 are bent and used in a U-shape, it is difficult to reduce the size. Next, in the case of the one shown in FIG. 11 , when it is attempted to obtain a flat resin seal on the upper surface, the dams 6
5, it is not suitable for mass production because it requires a step of applying the mold member 66 on top of 5 and injecting the sealing resin 67 into the package from the groove 64 of the dam 65. Since there is no choice but to increase the size, there is also a problem in terms of miniaturization. Although not shown, in a power semiconductor device in which a lead wire extends from a sealing resin, a plurality of deburring steps including deburring at the root of the lead wire must be performed after sealing with the resin. However, it was difficult to reduce the size of semiconductor devices. The present invention is highly compact, thin, and lightweight, and is highly mass-producible, especially when a semiconductor element such as a Schottky barrier diode having a relatively large capacity, a bipolar transistor, a field effect transistor, or another circuit component is resin-sealed. , A thermal shock resistance, a moisture resistance, a PCT test, and the like, and an object of the present invention are to provide a manufacturing method having good characteristics.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 00022

[Correction method] Change

[Correction content]

Next, using the ultraviolet curable resin having such a composition example, a manufacturing apparatus for encapsulating a plurality of electrically insulating substrates 1 having a large area as described in the above embodiments in the form of islands. for be described with reference to FIG. FIG. 6 (A),
(B) shows a front view and a side view of the pressing mold member 8 constituting a part of the manufacturing apparatus, which is made of a plastic resin such as silicone resin or acrylic resin, or a substantially transparent material such as glass. Holding mold member 8
Consists of a base portion 8A and a holding portion 8B. Holding part 8
B has a pressing surface 8B1 having substantially the same size as the surface surrounded by the inner wall of the frame-shaped upper mold member 6 shown in FIG.
On the pressing surface 8B1, ridges 8B2 having a V-shaped cross section are formed in a grid pattern in a pattern matching the grid scribe lines formed on the large-area electrically insulating substrate 1. The height of the ridge 8B2 determines the thickness of the sealing resin formed on the large-area electrically insulating substrate 1, that is, the thickness of the sealing resin is substantially equal to the height of the ridge 8B2. In addition, through holes 8B for releasing excess sealing resin are provided at the four corners of the pressing portion 8B.
3 are formed, and the through holes 8B3 are formed in the base portion 8A.
To each of the through holes 8A1 formed in.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 00002

[Correction method] Change

[Correction content]

As shown in FIG. 2C, the upper mold member 6 is a large-area electrically insulating substrate 1 along the lower part of the inner wall.
6A is cut away, and therefore the large-area electrically insulating substrate 1 set on the flat surface of the lower mold member 7 is cut away from the lower mold member 7 and the upper mold member 6A. It is held tightly by the wall of. In such a state, the ultraviolet curable resin (not shown) of the above formulation example is injected into the upper mold member 6 and degassed in vacuum. After that, the pressing surface 8B1 of the pressing portion 8B is turned downward in FIG.
The pressing portion 8B of the pressing mold member 8 is pushed in, and the ridge 8B2 having a V-shaped cross section is held in a state of reaching the surface of the large-area electrically insulating substrate 1 (FIG. 7 ). In this state,
Ultraviolet rays are irradiated from above the pressing mold member 8. When the height of the grid-shaped ridges 8B2 is approximately 1.5 mm, that is, when the thickness of the sealing resin 5 is approximately 1.5 mm, the metal halide lamp (120 W / cm) is approximately 10 mm from the upper surface of the sealing resin 5.
Irradiation was carried out at a position with a height of cm, and the material was allowed to pass 10 times at a speed of 6 m / min for good curing. Thereafter, the large-area electrically insulating substrate 1 is removed from the mold member, and an external force is applied to the large-area electrically insulating substrate 1 scribe line 1C.
Thus, a very small and thin resin-encapsulated semiconductor device or resin-encapsulated electronic circuit device in which the encapsulating resin rises almost vertically from the peripheral edge of each electrically insulating substrate was obtained. The resin-encapsulated semiconductor device and resin-encapsulated electronic circuit device thus obtained have a mounting area of 1/3 to 1 as compared with similar devices.
/ 4, the thickness is almost 1/2, which is very small and lightweight. Also, no deburring process of the sealing resin is required.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

Next, FIG. 8 uses the large-area electrically insulating substrate 1 as shown in FIG. 1 and mounts a semiconductor element or the like on the surface of the electrically insulating substrate on which the scribe line 1C is formed and seals it with resin. It is an example. In this case, a pressing mold member 8 having a flat top and a narrow width of the ridge 8B2 is used. By using the mold member 8 as described above, a very small and thin resin-sealed semiconductor device or resin-sealed electronic circuit device in which the sealing resin rises vertically from the peripheral edge of the substantially electrically insulating substrate is provided. Obtainable.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 00025

[Correction method] Change

[Correction content]

Next, FIG. 9 shows a bare chip of a planar transistor suitable for being applied to the semiconductor device as described above. This planar transistor has an n-type semiconductor grown on an n ⁺ semiconductor substrate 10 having a high n-type impurity concentration.
N ^- epitaxial layer 11 having a sufficiently low type impurity concentration,
A p ⁺ emitter region 12 having a high p-type impurity concentration formed in the epitaxial layer 11, and an n ⁺ base region 1 having a high n-type impurity concentration formed in the semiconductor region 12
3, a collector electrode 14 formed on the exposed surface of the semiconductor substrate 10 in a hole extending at least to the surface of the semiconductor substrate 10, a collector bump electrode 15 formed on the collector electrode 14, and an emitter region 12 so as to form ohmic contact. From the emitter electrode 16 and the emitter bump electrode 17 thereon, the base electrode 18 formed to make ohmic contact with the base region 12, the base bump electrode 19 formed thereon, and the lateral resistance reducing metal film 20. Become. The feature of this planar type transistor is that the collector bump electrode 15 and the emitter bump electrode 1
7 and the base bump electrode 19 are all on the same surface, and their heights are all at the same level.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an embodiment of the present invention. Figure 2
It is a figure for demonstrating one Example of this invention. Figure 3
FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a diagram for explaining one embodiment of the present invention. FIG. 5 is a diagram showing an embodiment of the present invention. FIG. 6 is a diagram showing an embodiment of the present invention. FIG. 7 is a diagram showing an embodiment of the present invention. FIG. 8 is a diagram showing an embodiment of the present invention. FIG. 9 shows a semiconductor device used in the present invention .
It is a figure which shows an example. FIG. 10 is a diagram showing a conventional example.
FIG. 11 is a diagram showing a conventional example. ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 27, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining one embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram for explaining one embodiment of the present invention.

FIG. 5 is a diagram showing an embodiment of the present invention.

FIG. 6 is a diagram showing an embodiment of the present invention.

FIG. 7 is a diagram showing an embodiment of the present invention.

FIG. 8 is a diagram showing an embodiment of the present invention.

FIG. 9 is a diagram showing an example of a semiconductor device used in the present invention.

FIG. 10 is a diagram showing a conventional example.

FIG. 11 is a diagram showing a conventional example.

[Explanation of Codes] 1 ... Electrically insulating substrate 1A ... Conductive pattern 1B ... Electrode pattern 1C ... Scribing line 2 ... Semiconductor element 3 ... Solder layer 4 ... Metal wire 5 ... Sealing resin 6 ... Upper mold member 7 ... Lower mold member 8 ... Pressing mold member 10 ... Semiconductor substrate 11 ... Epitaxial layer 12 ...
Emitter region 13 ... Base region

Front Page Continuation (72) Inventor Masafumi Kuwahara 1-1-18 Takada, Toshima-ku, Tokyo Origin Electric Co., Ltd. (72) Haruo Ninomiya 1-1-18 Takada, Toshima-ku, Tokyo Origin Electric Co., Ltd. In the company

Claims (17)

[Claims] 1. A semiconductor device in which one or more semiconductor elements fixed to a predetermined conductive pattern formed on one main surface of an electrically insulating substrate are sealed with a sealing resin. The resin has a flat upper surface having a size substantially equal to the area of the main surface of the electrically insulating substrate, and a molding side wall surface extending from the peripheral edge of the electrically insulating substrate substantially perpendicularly to the upper surface. Semiconductor device. 2. A semiconductor device in which at least one semiconductor element fixed to a predetermined conductive pattern formed on one main surface of an electrically insulating substrate is sealed with a sealing resin. The resin has a smooth upper surface having a size substantially equal to the area of the main surface of the electrically insulating substrate, extends from the peripheral edge of the electrically insulating substrate substantially perpendicularly to the upper surface, and is rougher than the smooth upper surface. A semiconductor device having a divided side wall surface. 3. A large area electrically insulating substrate having a plurality of predetermined conductive patterns on one main surface and having a plurality of scribe lines formed on at least one main surface so as not to cover the predetermined conductive pattern. , One or more semiconductor elements fixed to each of the predetermined conductive patterns, and sealing for sealing the entire surface of the large-area electrically insulating substrate where the conductive patterns are formed so that the surface is flat A large-area semiconductor device comprising a resin and a groove formed at a predetermined depth along a portion of the sealing resin corresponding to the scribe line. 4. The large-area semiconductor device according to claim 3, wherein the bottom of the groove reaches the surface of the large-area electrically insulating substrate. 5. The method according to claim 3, wherein the distance between the bottom of the groove and the surface of the large-area electrically insulating substrate is approximately 2 mm or less, and the scribe line has a sealing resin. A large-area semiconductor device formed on the surface of the large-area electrically insulating substrate opposite to the side. 6. A large-area electrically insulating substrate having a plurality of predetermined conductive patterns on one main surface and having a plurality of scribe lines formed on at least one main surface so as not to cover the predetermined conductive patterns. , One or more semiconductor elements fixed to each of the predetermined conductive patterns, 2 mm or less for sealing the entire surface of the large-area electrically insulating substrate on which the conductive patterns are formed so that the surface is flat A semiconductor device having a large area, which is provided with a sealing resin having a thickness of 1. 7. The desired electrode pattern according to claim 1, which is connected to a predetermined conductive pattern on one main surface of the electrically insulating substrate via a via hole. Is formed on the other main surface of the electrically insulating substrate. 8. The semiconductor device according to claim 1, wherein the semiconductor element has different electrodes on one main surface, and these electrodes are respectively fixed to independent conductive films of a conductive pattern. Surface mount semiconductor device. 9. The electronic circuit device according to claim 1, wherein other circuit components besides the semiconductor element are electrically connected to the conductive pattern. 10. A large area electrically insulating substrate having a plurality of predetermined conductive patterns on one main surface and having a plurality of scribe lines formed on at least one main surface so as not to cover the predetermined conductive pattern. And fixing one or more semiconductor elements to each of the predetermined conductive patterns, and then sealing the entire surface of the large-area electrically insulating substrate where the conductive patterns are formed so that the surface is flat. A semiconductor device is obtained by sealing with a resin and applying an external force during the curing of the sealing resin to divide the electrically insulating substrate and the sealing resin along the scribe line to obtain individual semiconductor devices. Of manufacturing a semiconductor device. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the encapsulating resin is divided in a semi-cured state at a temperature of 80% or less of a heat deformation temperature at the time of complete curing. 12. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is divided into individual semiconductor devices and then further heated and cured. 13. A large-area electrically insulating substrate having a plurality of predetermined conductive patterns on one main surface and having a plurality of scribe lines formed on at least one main surface so as not to cover the predetermined conductive patterns. And fixing one or more semiconductor elements to each of the predetermined conductive patterns, and then sealing the entire surface of the large-area electrically insulating substrate where the conductive patterns are formed so that the surface is flat. Along with sealing with a resin, a groove having a predetermined depth is formed along the portion of the sealing resin corresponding to the scribe line, and thereafter, heat curing is performed and external force is applied to seal the electrically insulating substrate. A method for manufacturing a semiconductor device, characterized in that the resin and the resin are divided along the scribe line to obtain individual semiconductor devices. 14. The mold member according to claim 13, wherein a flat side is formed with a narrow side portion having a predetermined height along a location corresponding to the scribe line, and the predetermined height is used. A method of manufacturing a semiconductor device, characterized in that a groove having a predetermined depth is formed along the portion of the sealing resin corresponding to the scribe line by the narrow side portion. 15. A large-area electrically insulating substrate having a plurality of predetermined conductive patterns on one main surface and having a plurality of scribe lines formed on at least one main surface so as not to cover the predetermined conductive pattern. And fixing one or more semiconductor elements to each of the predetermined conductive patterns, and then activating energy so that the surface of the large-area electrically insulating substrate is flattened over the entire surface of the conductive pattern formed portion. A plurality of ridges having a predetermined height are provided along a portion of the active energy ray-curable resin corresponding to the scribe line, which is made of a substantially transparent material, by supplying and covering the ray-curable resin. A semiconductor device characterized in that an active energy ray-curable resin is cured by pressing with a mold member and then irradiating with active energy ray through the mold member. Manufacturing method. 16. The electronic circuit device according to claim 10, wherein other circuit components other than the semiconductor element are electrically connected to the conductive pattern. Production method. 17. A large area electrically insulating substrate having a plurality of predetermined conductive patterns on one main surface and having a plurality of scribe lines formed on at least one of the main surfaces so as not to cover the predetermined conductive patterns. And a mold member having a frame portion suitable for a large-area electrically insulating substrate having one or more semiconductor elements fixed to each of the predetermined conductive patterns, and made of a substantially transparent material. An apparatus for manufacturing a semiconductor device, comprising a pressing mold member having a plurality of ridges having a predetermined height along a location corresponding to a scribe line and having a through hole for allowing an excess sealing resin to escape.