JPH0659933A - Code converter - Google Patents

Abstract

PURPOSE:To convert a program into a code capable of guaranteeing the stop of execution on an execution stop position specified by a user and rapidly executing other parts by parallel processing in the case of executing the sym bolic debugging of the program by a VLIW or super color system computer. CONSTITUTION:A program is analyzed (13), parallel optimization to be normally executed is executed (17) and the optimized program is converted into an object code (18). In order to stop execution in each sentence or in each function (specified in a debugging request specified and inputted (12)), the head of instructions constituting a sentence or a function is positioned on the head of an instruction string to be simultaneously executed and the arrangement of remaining instructions is corrected (16) by inserting an NOP instruction. The processing is controlled so as not to execute parallel optimizing processing over the range of one sentence or the range of one function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code conversion device in an electronic computer capable of executing a plurality of instructions in parallel.

[0002]

2. Description of the Related Art In recent years, computer technology has been introduced which enables parallel execution in units of instructions, and it is possible to process one or more instructions per cycle. VLIW
(Very Long Instruction Wo
The two methods, rd) technology and superscalar technology, are typical.

The VLIW technology combines a predetermined number of instructions into one execution unit (Long I).
nStructure) and supplies it to the computer. The computer distributes a given set of a plurality of instructions to a predetermined arithmetic unit and performs parallel processing. In this case, it is not necessary to determine the possibility of simultaneous execution of a plurality of instructions, and since the control is simple, it can be realized with a small amount of hardware. However, since processing is performed in parallel, it is necessary to perform optimization called "instruction scheduling" in which a group of instructions that can be executed in parallel is extracted by a compiler or manually and the instructions are combined into one execution unit.

On the other hand, the superscalar system is equipped with hardware for interpreting an instruction string assuming sequential execution as in the conventional case and checking the possibility of parallel execution of a plurality of instructions, and a plurality of read instructions can be executed in parallel. In such a case, it is a method of controlling these to be executed in parallel.

In this method, since the parallel executability determination of the instruction is entrusted to the dedicated hardware, even an ordinary serial processing program is guaranteed to be executed while maintaining compatibility with the serial execution time. However, when actually aiming to improve performance with the superscalar method, it seems that multiple arithmetic units are in the operating state as much as possible based on information such as hardware resources (number of arithmetic units, arithmetic delay) and data dependency. Therefore, it is essential to perform "instruction scheduling" in advance.

As an instruction scheduling method in the superscalar system, one basic block (an instruction sequence in a program that does not leave a branch) is processed and instructions are rearranged based on hardware resource constraint conditions and data dependency constraint conditions. In order to speed up the loop part of a program called "list scheduling" or a program, one iteration portion of the loop is allocated to a specific hardware resource, and a plurality of loop iterations are virtually used by using individual processing units. “Software Pipelining (Software Pipe)
A method called "elining)" is known. Also, to enhance the effect of list scheduling,
Loop Unrolling (Loop Unro) that expands and processes the instruction sequence of the loop part of the program for multiple iterations
In some cases, a technique called "lling)" is used in combination.

In the VLIW method and the superscalar method, high-speed parallel execution is possible by using such an instruction rearranging method, but when debugging is performed in consideration of the correspondence with the source code at the time of program development. A problem arises.

In other words, if the above instruction rearrangement optimization is performed, the instructions corresponding to a plurality of statements on the source program may be distributed within one execution unit of these parallel processing methods. sell. For example, in a superscalar computer that simultaneously executes up to four instructions,
Instructions may be arranged as shown in (b). Here, the instructions 1 and 2 are instructions for the statement 1 in the source program (FIG. 2A), and the instructions 3 and 4 are instructions corresponding to the statement 2. When debugging such a program, the user sometimes wants to stop the program and confirm the execution state at the stage when the statement 1 is completed on the source program. In this case, the computer puts the four sorted instructions into one
The extra instructions 3, 4 are executed because they are executed simultaneously in the cycle.
It will stop at the stage when it has been executed. Therefore, depending on the contents of the instructions 3 and 4, the memory state and the register contents are different from the original statement 1 completion time, and debugging becomes very difficult. Similar difficulties occur in the case of step execution in sentence units.

In debugging, it is possible to rearrange instructions and stop parallel execution so that only one instruction is executed per cycle. In that case, however, the parallel processing capacity of the computer cannot be used at all, and the execution time is particularly long. When debugging a large program, the efficiency of the debugging work itself will be significantly reduced.

As described above, the method of performing parallel processing by the instruction rearrangement method such as list scheduling and software pipelining in the computer having the instruction parallel execution function such as VLIW and superscalar method is effective in terms of speeding up the processing. On the other hand, since multiple instructions are executed simultaneously in one cycle, considering the operability during debugging during program development, it is necessary to correctly execute the execution in the execution unit desired by the user and check the status. However, there is a disadvantage that it causes inconvenience. Further, the method of executing only one instruction per cycle during debugging does not impair the operability of debugging, but the parallel processing capacity of the computer cannot be utilized at all, and the work efficiency of large-scale programs is significantly reduced. was there.

[0011]

Thus, VLIW,
On a computer that has an instruction parallel execution function such as the superscalar method, parallel processing using instruction rearrangement methods such as list scheduling and software pipelining is effective in terms of processing speed, but at the time of program development. Considering the operability at the time of debugging, the instruction group executed in parallel may execute instructions before and after the execution stop point desired by the user on the original program. If the program is stopped after executing such an instruction group, an extra instruction will be executed. For this reason, when the execution of the source program is stopped in units of statements, the states of the memory, registers, etc. at the time of the stop will be different from the original state, and the operability during debugging will be significantly impaired.

In order to avoid such a problem, it is conceivable to execute the instruction sequence equivalent to the source program without executing instruction rearrangement at the time of debugging and execute only one instruction in one cycle by suppressing parallel execution of instructions. . However, with this method, the instruction parallel execution capability of the computer cannot be used at all, and the efficiency of the entire debugging work is significantly reduced, especially for a program with a long execution time.

When actually performing a debugging operation, the place where the user desires to stop the execution depends on the debugging stage and the nature of the program. Even if it is necessary to stop the execution in units of statements at the beginning of debugging, the debugging unit of the user such as a unit of statement (block), a unit of function, or a unit of subroutine changes as the debugging progresses. Therefore, especially when debugging a large-scale program,
It is not a good idea from the viewpoint of debugging efficiency to execute all programs under a certain execution constraint for a certain level of debugging (stopping execution).

The present invention has been made in consideration of such circumstances, and an object of the present invention is, in a computer capable of executing a plurality of instructions in parallel, desired by a user according to his / her debugging stage. Code that can hold the machine state that matches the meaning of the original program when the program is stopped at the execution stop point, and that can execute instruction parallel execution that utilizes the parallel processing capacity of the computer within the range that satisfies this condition It is to provide a code conversion device for converting a program into.

[0015]

According to the present invention, there is provided an instruction execution stoppable point setting section for setting a point at which instruction execution can be temporarily stopped during debugging on a program according to a user's designation, and an execution stoppable point set. , An instruction placement correction unit that corrects the instruction placement constraint so that instructions attributed to different sentences before and after are not executed at the same time, and parallel optimization within the range that satisfies the above instruction placement constraint conditions And an optimizing unit for performing optimization, and outputs the object code of the program designated by the user.

[0016]

According to the present invention, an object code in which instruction scheduling is performed so that instructions before and after a portion where instruction execution may be stopped during debugging is not simultaneously executed in one cycle can be obtained. When the program execution is stopped at the place where execution can be stopped, the program state specified in the original program can be correctly observed, and the source level debugging that was conventionally performed can be performed easily on VLIW and superscalar computers. Can be done. Among the above-mentioned execution stoppable points, it is possible to specify an instruction suitable for a desired debug stage among instructions issued by the user for performing code conversion.

In addition, for a portion not designated by the user as an execution stoppable portion, high-speed execution is possible because optimization such as instruction scheduling performed by a normal VLIW or superscalar computer compiler is performed, so that debugging efficiency is improved. Can be converted into good object code.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a code conversion device (compiler) according to an embodiment of the present invention. This device
Instruction input unit 10, program input unit 11, debug request analysis unit 12, syntax analysis unit 13, debug request recording unit 1
4, an instruction execution stoppable point setting unit 15, an instruction placement correction unit 16, an optimization unit 17, and a code generation unit 18. The instruction execution stoppable point setting unit 15 includes a debug information input unit 151 and an instruction execution stoppable point determination unit 1.
It is composed of 52.

First, from the instruction input section, "cc-gstm"
When an instruction such as "t (program name)" is issued, the source program read by the program input unit 11 is converted into an intermediate text through the syntax analysis unit 13, and the debug request analysis unit 12 determines that it is a compilation target. To see if there is a debug request for the program. When there is a debug request, the fact that there is a debug request is recorded in the debug request recording unit 14. If the debug option is set, that information is also stored in the debug request recording unit. The debug request is represented by -g in the above instruction, and stmt (statement unit)
Is the debug option. Other than this, as will be described later, blk (block unit), func (function unit)
Etc. can be specified. The user specifies the instruction execution stoppable position described later by this debug option. If there is a debug request, it is also necessary to collect the symbolic information used during debugging, but this can be done using the same method as the conventional one.

The instruction execution stoppable point setting section 15 checks the debug request recording section 14 and collects information about the execution stoppable point designated by the user from the debug information input section 151 when a debug request is issued. Here, the debug information can be obtained by examining a debug option switch at the time of compiling, a debug information file also specified at the time of compiling, environment variables in a shell on the OS being used, and the like. From the obtained debug information, the instruction execution stoppable point determination unit 152 determines the instruction execution stoppable point.

The optimization unit 17 analyzes the intermediate text and analyzes the VL.
Various optimization processes for the IW and superscalar processors, that is, instruction rearrangement by list scheduling, loop processing by software pipelining, loop expansion, etc. are executed. At this time, even if the optimization process is performed, control is performed so that the optimization process is performed only when the set instruction execution stoppable position satisfies a predetermined instruction placement constraint condition. By performing the optimizing process, the optimizing process that impairs the instruction placement constraint condition is not performed. In other words, when the user makes a request to debug in sentence units, the optimization that nests the commands that compose each sentence is not performed, and the commands that compose one sentence are one block. To optimize.

The intermediate text output through the above modules is translated into a machine language by the code generator 18 and output as an object program. In the code generation unit, the instruction placement correction unit 16 examines the set execution-stoppable portion and performs instruction placement correction so that the output code satisfies a predetermined instruction placement constraint condition. Specifically, the instruction set in the instruction boundary in the object code determined according to the parallelism of the target VLIW and superscalar computer (for example, in the case of a computer capable of simultaneously executing four instructions, the instruction boundary is four instructions) N between debug units so that the execution-stoppable part is located
Correction is performed by inserting OP.

For example, consider a case where a code is generated for the C language function shown in FIG. 3A in accordance with a user's instruction stoppable point setting. When the target processor is capable of executing four instructions simultaneously, if the user wants to stop the execution on a sentence-by-sentence basis, correction is performed so that the instruction at the beginning of the sentence comes at the beginning of the boundary of four instructions. Specifically, no correction is made when the last instruction of the previous sentence is placed at the boundary of the four-instruction boundary, but when it is placed in the middle, that is, when 4
If it is placed in the first or second instruction of the instruction sequence,
As shown in FIG. 3B, the instruction placement is corrected by inserting NOPs in the remaining third and fourth instructions. Then, although the end of one sentence is corrected in this way, the code for which parallel optimization processing such as instruction scheduling has been performed is output for the other portions.

Further, when the user gives an instruction to stop the execution in block units instead of statements, as the debug stage progresses, the head of the loop or the head of one block comes to the boundary of four instructions. The corrected code is output. At this time, parallel optimization processing is performed inside the loop and inside the block. Similarly, if you specify that you want to stop execution in units of functions / procedures, the start of the function / procedure is corrected so that it is on the boundary of four instructions, and the code optimized in parallel is output inside the function / procedure. . It should be noted that the sentence or function may be corrected so that the end of the sentence or function comes to the boundary.

When the object program generated as described above is executed by the execution unit (not shown), the execution can be stopped at the instruction execution stoppable portion designated by the user, and the portion sandwiched between the execution stoppable portions is usually. Will be executed in parallel. Therefore, if the generated object program is applied to an ordinary debugger, the user can actually stop the program and stop the execution at the point where he / she wants to see the execution state, even though the program includes parallel execution.

[0027]

As described above, according to the present invention, the user can stop the execution in the debug unit designated by himself, and can correctly observe the program state designated by the original program.
In that case, parallel execution is performed in a place where execution stop is not designated, so that more efficient debug processing can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a code conversion device (compiler) according to an embodiment of the present invention.

FIG. 2A is a diagram showing a C language program to be processed by the compiler according to the present embodiment, and FIG. 2B is a diagram showing an example in which the program of FIG.

3A is a diagram showing a C language program to be processed by the compiler according to the present embodiment, and FIG. 3B is an assembler program obtained as a result of compiling the program of FIG. FIG.

[Explanation of symbols]

 10 instruction input unit 11 program input unit 12 debug request analysis unit 13 syntax analysis unit 14 debug request recording unit 15 instruction execution stoppable location setting unit 151 debug information input unit 152 instruction execution stoppable location determination unit 16 instruction placement correction unit 17 optimal Coder 18 Code generator

Claims (1)

[Claims] 1. A code conversion device for converting a program into a code to be executed by an electronic computer system capable of simultaneously executing a plurality of instructions, a means for setting a position where instruction execution can be stopped by user designation, and a set instruction execution. A means for correcting the instruction placement so that the instructions attributed to the program description before and after the haltable point are not executed at the same time, and the set instruction execution haltable point has a predetermined instruction placement constraint. A code conversion device comprising means for generating, according to a corrected instruction arrangement, a code for the electronic computer system to simultaneously execute a plurality of instructions within a range that does not prevent a condition from being satisfied.