JPH0658995A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device in which noise can be generated internally under test mode while facilitating programming of evaluator. CONSTITUTION:A resistor 13, MOS transistors 14, 15, and a resistor 16 are connected in series between a power supply terminal 3 and a ground terminal 4. A test signal Stest of 'H' is fed, under test mode, to a timer 10 which thereby produces a pulse. Output signal from the timer 10 is fed, along with the test signal Stest, to a NAND circuit 11 which then delivers output signals to the gate of a transistor 14 and the gate of a transistor 15 through an inverter 12. The test signal Stest goes 'H' under test mode and when output signal from the timer 10 goes 'H', the transistors 14, 15 are turned ON and a through current i1 flows to cause potential variation at the power supply terminal 3 thus bringing about a pseudo noise applied state at the power supply terminal 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a noise generating circuit.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram schematically showing the relationship between a conventional semiconductor device and its evaluation device. In the figure, 1 is a semiconductor device, and 2 is its evaluation device. In the semiconductor device 1, Vcc is a power supply terminal, GND
Is a ground terminal, AD is an address input terminal, DATA is a data input / output terminal, CE is a terminal to which a chip enable signal for controlling the operation of the semiconductor device 1 is supplied, and OE is an output for controlling the output of the semiconductor device 1. This is a terminal to which an enable signal is supplied. Predetermined terminals of the evaluation device 2 are connected to the terminals of these semiconductor devices 1. Evaluation device 2
The semiconductor device 1 is evaluated by supplying the semiconductor device 1 with the power supply and the signal generated in 1.

FIG. 12 shows a noise test of the semiconductor device 1.
The waveform at the Vcc noise test in which noise is applied to the power supply terminal Vcc is shown. FIG. 12 shows two rates at the time of the function test, FIG. 12A shows an address signal, FIG. 12B shows a power supply potential, and FIG. 12C shows a chip enable signal. The power supply potential is set to V1 during the period of T1,
The period of 2 is set to V2, and the period of T3 is set to V1, whereby pseudo noise is applied to the power supply terminal Vcc, and the Vcc noise test is performed.

FIG. 13 shows a waveform of a noise test of the semiconductor device 1 during a CE bar noise test in which noise is applied to the chip enable terminal CE bar. FIG. 13 shows two rates at the time of the function test, FIG. 13A shows an address signal, FIG. 13B shows a power supply potential, and FIG. 13C shows a chip enable signal. The chip enable signal is set to “L” during the period T4 to put the semiconductor device 1 into the operation mode, and temporarily during the period T5 to apply pseudo noise to the chip enable terminal CE bar, for example. Set to “H” for a period of several nanoseconds, and
The period of 6 is set to "L" to set the original operation mode. By passing the period of T4 → T5 → T6, a CE bar noise test is performed in which one shot pulse noise is applied to the chip enable terminal CE bar during the operation of the semiconductor device 1, that is, while the chip enable signal is “L”. Has been done. The period T7 is the standby period of the semiconductor device 1.

[0005]

Since the conventional semiconductor device noise test is carried out as described above, noise must be generated by the evaluation device 2 (FIG. 12B, FIG.
13C), the setting of the evaluation device 2, that is, the program becomes complicated, and the setting of the noise to be applied must be made in consideration of the function of the hardware.

The present invention has been made in order to solve such a problem, and an object thereof is to provide a semiconductor device which can internally generate noise during a noise test and which facilitates programming of an evaluation device. To do.

[0007]

According to a first aspect of the present invention, a semiconductor device is connected in series between a first power supply terminal and a second power supply terminal which has a lower potential than the first power supply terminal. And a pulse generating circuit connected to the control electrode of the switching element, and drives the switching element with the output pulse of the pulse generating circuit in the test mode.

According to a second aspect of the present invention, there is provided a semiconductor device in which a resistor element and a switching element connected in series between a first power supply terminal and a second power supply terminal having a lower potential than the first power supply terminal. An element and a timer connected to the control electrode of the switching element are provided, and the switching element is driven by the output pulse of the timer in the test mode.

According to a third aspect of the present invention, there is provided a semiconductor device in which a resistor element and a switching element connected in series between a first power supply terminal and a second power supply terminal having a lower potential than the first power supply terminal. An element and an ATD circuit connected to the control electrode of the switching element are provided, and the switching element is driven by the output pulse of the ATD circuit in the test mode.

A semiconductor device according to a fourth aspect of the present invention includes a switching element connected between an external input terminal and a power supply terminal, and a pulse generation circuit connected to a control electrode of the switching element. In the test mode, the switching element is driven by the output pulse of the pulse generating circuit.

A semiconductor device according to a fifth aspect of the present invention includes a switching element connected between an external input terminal and a power supply terminal, and a timer connected to a control electrode of the switching element, and a test device. In the mode, the switching element is controlled by the output pulse of the timer.

A semiconductor device according to a sixth aspect of the present invention comprises a switching element connected between an external input terminal and a power supply terminal, and an ATD circuit connected to a control electrode of the switching element. AT above in test mode
The output pulse of the D circuit controls the switching element.

[0013]

In the invention described in claims 1 to 3,
In the test mode, the switching element is driven by the output pulse of the pulse generating circuit (timer, ATD circuit), and noise is applied to the power supply terminal Vcc.

According to the present invention, the switching element is driven by the output pulse of the pulse generating circuit (timer, ATD circuit) in the test mode and noise is applied to the external input terminal. Become.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 is a connection diagram showing an embodiment of a semiconductor device according to the present invention. In the figure, the power supply terminal (Vc
c) Between the 3 and the ground terminal (GND) 4, a resistor 13 having a high resistance value, a switching element such as a P channel MOS
A transistor 14, a switching element such as an N-channel MOS transistor 15 and a high resistance resistor 16 are connected in series.

Reference numeral 10 is a timer as a pulse generating circuit, and a test signal Stest is supplied to the timer 10 to control its operation. The test signal Stest is "L" in the normal mode and the timer 10 is stopped, while it is "H" in the test mode and the timer 1 is in the stopped state.
0 is in the operating state (see FIG. 2). When the timer 10 is in the operating state, the timer 10 is in synchronization with the cycle T of the address signal (see FIG. 3A) supplied from the evaluation device 2 (see FIG. 11) to the memory (not shown) of the semiconductor device of this example. A pulse having a predetermined pulse width (Ta) is output at a cycle (T). The switching between the normal mode and the test mode is performed by inputting a high voltage (“HH”) to a signal pin that becomes irrelevant during the function test, for example.

The output signal of the timer 10 is supplied to one input terminal of the NAND circuit 11, and the test signal Stest is supplied to the other input terminal of the NAND circuit 11. Then, the output signal of the NAND circuit 11 is supplied to the gate of the transistor 14 as it is and also supplied to the gate of the transistor 15 via the inverter 12.

In the above structure, first, the operation in the normal mode will be described. In the normal mode, the test signal Stest becomes "L" and the timer 10 is stopped.
At this time, the output signal of the NAND circuit 11 becomes "H",
The transistor 14 is turned off. In addition, the inverter 12
Since the output signal of is "L", the transistor 15 is also turned off. Therefore, in the normal mode, the transistors 14 and 15 are both turned off, so that the through current i1 does not flow and no noise is applied to the power supply terminal 3.

Next, the operation in the test mode will be described.
In the test mode, the test signal Stest becomes "H", the timer 10 is in the operating state, and the timer 10 outputs a pulse. At this time, the output signal of the NAND circuit 11 is an inverted signal of the output signal of the timer 10. When the output signal of the timer 10 becomes "L", the output signal of the NAND circuit 11 becomes "H" and the transistor 14 is turned off, and the output signal of the inverter 12 becomes "L" and the transistor 15 is turned off. Becomes Therefore, the power supply terminal 3
The through current i1 does not flow from the ground terminal 4 to the ground terminal 4.

When the output signal of the timer 10 becomes "H", the output signal of the NAND circuit 11 becomes "L" and the transistor 14 is turned on, and the output signal of the inverter 12 becomes "H". 15 is turned on.
Therefore, the through current i1 flows from the power supply terminal 3 to the ground terminal 4. Although not mentioned above, the resistors 13 and 16 are provided as follows.
This is to prevent an overcurrent from flowing at this time.

FIG. 3 shows an example of a waveform diagram in the test mode. FIG. 3 shows two rates at the time of the function test. The same figure A shows the address signal, the same figure B shows the output signal of the timer 10, the same figure C shows the through current i1, and the same figure D shows the potential of the power supply terminal 3. Is. As you can see from Figure 3,
When the output signal of the timer 10 becomes “H”, the through current i
1 flows and the potential of the power supply terminal 3 fluctuates, that is, becomes lower than V1. Therefore, the noise is artificially applied to the power supply terminal 3.

As described above, in this example, the function test can be performed while generating this noise in the test mode, and Vcc noise can be obtained without applying noise from the evaluation device 2 (see FIG. 11) as in the conventional case. The test can be conducted. The pulse generation cycle of the timer 10 is
The circuit can be adjusted to match the test period T. Further, it may be switchable so that measurement can be performed in a plurality of test cycles.

Example 2. FIG. 4 is a connection diagram showing another embodiment of the semiconductor device according to the present invention. 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, reference numeral 18 is an ATD (Adress Trigger Detecti-on) circuit as a pulse generation circuit, and a test signal Stest is supplied to the ATD circuit 18 to control its operation. The test signal Stest is "L" in the normal mode and the ATD circuit 18 is in the stopped state, while it is "H" in the test mode and the ATD.
The circuit 18 becomes active (see FIG. 5). ATD circuit 1
Reference numeral 8 denotes a circuit for generating a one-shot pulse by catching a change in an address signal or a control signal supplied from the outside, for example, in an operating state. Therefore, AT
The D circuit 18 outputs a pulse having a predetermined pulse width (Ta) at a test cycle (T).

The switching between the normal mode and the test mode is performed by inputting a high voltage ("HH") to a signal pin that becomes irrelevant during the function test, as in the example of FIG. The output signal of the ATD circuit 18 is supplied to one input terminal of the NAND circuit 11, and the test signal Stest is supplied to the other input terminal of the NAND circuit 11.
To supply. The other configuration of this example is similar to that of the example of FIG.

In the above configuration, the ATD circuit 18 outputs a pulse similar to that of the timer 10 of the example of FIG. 1, and therefore operates in the same manner as the example of FIG. That is, in the normal mode, the test signal Stest is "L", the ATD circuit 18 is stopped, and the transistors 14 and 15 are both turned off. Therefore, the through current i1 does not flow and no noise is applied to the power supply terminal 3. Also, in test mode, AT
When the output signal of the D circuit 18 is "L", both the transistors 14 and 15 are turned off, so that the through current i1 does not flow. On the other hand, in the test mode, when the output signal of the ATD circuit 18 is "H", both the transistors 14 and 15 are turned on, so that the through current i1 flows.

FIG. 6 shows an example of a waveform diagram in the test mode. FIG. 6 shows two rates at the time of the function test. A in FIG. 6 is an address signal and B in FIG. 6 is AT.
Output signal of D circuit 18, C in the same figure is through current i1, D in the same figure
Is the potential of the power supply terminal 3. As is apparent from FIG. 6, when the output signal of the ATD circuit 18 becomes "H", the through current i1 flows and the potential of the power supply terminal 3 fluctuates, that is, becomes lower than V1. Therefore, the noise is artificially applied to the power supply terminal 3.

As described above, in this example, the function test can be performed while generating this noise in the test mode, and Vcc noise can be obtained without applying noise from the evaluation device 2 (see FIG. 11) as in the conventional case. The test can be conducted.

Example 3. FIG. 7 shows still another embodiment of the semiconductor device according to the present invention. 7, parts corresponding to those in FIG. 1 are designated by the same reference numerals. In the figure, the power supply terminal (Vcc) 3 and the ground terminal (G
ND) 4 and a switching element such as P
Channel MOS transistors 21 and 22 and N-channel MOS transistor 23 are connected in series. The connection point of transistors 22 and 23 is connected to ground terminal 4 via N-channel MOS transistor 24. Further, the gates of the transistors 21 and 24 are connected to the ground terminal 4.

The transistors 21 to 24 form a chip enable signal input buffer circuit 25. The output terminal is derived from the connection point of the transistors 22 and 23.
Further, the gates of the transistors 22 and 23 are commonly connected, and the chip enable terminal 19 (CE bar) as an external input terminal is connected to this connection point. Further, between the power supply terminal 3 and the chip enable terminal 19, a P channel M
The OS transistor 20 is connected. This transistor 2
The output signal of the NAND circuit 11 is supplied to the 0 gate.

Further, 10 is a timer as a pulse generating circuit, and a test signal Stest is supplied to the timer 10 to control its operation. The test signal Stest is "L" in the normal mode and the timer 10 is stopped, while it is "H" in the test mode and the timer 1 is in the stopped state.
0 is in the operating state (see FIG. 2). When in operation, the timer 10 outputs a pulse having a predetermined pulse width (Ta) at a predetermined period (T).

The normal mode and the test mode are switched by, for example, inputting a high voltage ("HH") to a signal pin that becomes irrelevant during the function test. The output signal of the timer 10 is fed to the NAND circuit 11
The NAND circuit 11 supplies the test signal Stest to the other input terminal. Then, the output signal of the NAND circuit 11 is supplied to the gate of the transistor 20.

In the above structure, the operation in the normal mode will be described first. In the normal mode, the test signal Stest becomes "L" and the timer 10 is stopped.
At this time, the output signal of the NAND circuit 11 becomes "H",
The transistor 20 is turned off. Therefore, the through current i
2 does not flow, and no noise is applied to the chip enable terminal 19.

Next, the operation in the test mode will be described.
In the test mode, the test signal Stest becomes "H", the timer 10 is in the operating state, and the timer 10 outputs a pulse. At this time, the output signal of the NAND circuit 11 is an inverted signal of the output signal of the timer 10. When the output signal of the timer 10 becomes "L", the output signal of the NAND circuit 11 becomes "H" and the transistor 20 is turned off, so that the through current i2 does not flow from the power supply terminal 3 to the ground terminal 4. When the output signal of the timer 10 becomes "H", the output signal of the NAND circuit 11 becomes "L" and the transistor 20 is turned on, so that the through current i2 flows from the power supply terminal 3 to the ground terminal 4.

FIG. 8 shows an example of a waveform diagram in the test mode. FIG. 8 shows two rates at the time of the function test. A of FIG. 8 is an address signal, B of FIG. 8 is an output signal of the timer 10, C is a through current i, and D is a chip enable terminal 19. This is the supplied chip enable signal. As is clear from FIG. 8, the timer 10
When the output signal of becomes "H", the through current i2 flows,
The level of the chip enable terminal 19 is from "L" to "H"
It floats up to the side for a moment. Therefore, the noise is artificially applied to the chip enable terminal 19.

As described above, in this example, the function test can be performed while generating this noise in the test mode, and the CE bar noise can be eliminated without applying noise from the evaluation device 2 (see FIG. 11) as in the conventional case. The test can be conducted. The pulse generation cycle of the timer 10 can be adjusted by a circuit so as to match the test cycle T. Further, it may be switchable so that measurement can be performed in a plurality of test cycles.

Example 4. FIG. 9 is a connection diagram showing another embodiment of the semiconductor device according to the present invention. 9, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, reference numeral 18 is an ATD circuit as a pulse generation circuit, and a test signal Stest is supplied to the ATD circuit 18 to control its operation. The test signal Stest is "L" in the normal mode and AT
The D circuit 18 is stopped, while in the test mode it becomes "H" and the ATD circuit 18 is in operation (Fig. 5).
reference). The ATD circuit 18 is a circuit for generating a one-shot pulse by catching a change in an address signal or a control signal supplied from the outside, for example, in an operating state. Therefore, the ATD circuit 18 outputs a pulse having a predetermined pulse width (Ta) at the test cycle (T).

Note that switching between the normal mode and the test mode is performed by inputting a high voltage ("HH") to a signal pin that becomes irrelevant during the function test, as in the example of FIG. The output signal of the ATD circuit 18 is supplied to one input terminal of the NAND circuit 11, and the test signal Stest is supplied to the other input terminal of the NAND circuit 11.
To supply. The other configuration of this example is similar to that of the example of FIG. 7.

In the above configuration, since the ATD circuit 18 outputs the same pulse as that of the timer 10 of the example of FIG. 7, it operates similarly to the example of FIG. That is, in the normal mode, since the transistor 20 is turned off, the through current i2 does not flow and noise is not applied to the chip enable terminal 19. Further, in the test mode, when the output signal of the ATD circuit 18 is "L", the transistor 20 is turned off and the through current i2 does not flow. On the other hand, in the test mode, when the output signal of the ATD circuit 18 is "H", the transistor 20 is turned on and the through current i2 flows.

FIG. 10 shows an example of a waveform diagram in the test mode. FIG. 10 shows two rates at the time of the function test. A of FIG. 10 is an address signal, B of FIG. 10 is an output signal of the ATD circuit 18, C is a through current, and D is a chip enable terminal 19 in FIG. Is a chip enable signal supplied to the. As is clear from FIG. 10,
When the output signal of the ATD circuit 18 becomes "H", the through current i2 flows and the level of the chip enable terminal 19 rises from "L" to "H" for a moment. Therefore, the noise is artificially applied to the chip enable terminal 19.

As described above, in this example, the function test can be performed while generating this noise in the test mode, and the CE bar noise can be obtained without applying noise from the evaluation device 2 (see FIG. 11) as in the conventional case. The test can be conducted.

Example 5. Although the example in which noise is applied to the chip enable terminal 19 is shown in the examples of FIGS. 7 and 9, noise can also be applied to other external input terminals such as an address input terminal in the same manner.

[0042]

According to the first to third aspects of the invention, the first power supply terminal and the second power supply terminal, which has a lower potential than the first power supply terminal, are connected in series. Resistance element and switching element, and pulse generation circuit (timer, ATD circuit) connected to the control electrode of this switching element
And a pulse generation circuit (timer,
Since the switching element can be driven by the output pulse of the ATD circuit) and the noise can be applied to the power supply terminal, the noise at the time of the noise test can be generated internally, and the noise from the evaluation device is not required. This has the effect of making the program easier.

According to the invention described in claims 4 to 6, a switching element connected between the external input terminal and the power supply terminal, and a pulse generating circuit connected to the control electrode of the switching element ( Timer, ATD circuit), the switching element can be driven by the output pulse of the pulse generation circuit in the test mode, and the noise can be applied to the external input terminal. Therefore, the noise during the noise test can be generated internally. There is an effect that the noise of the device or the like is not required and the program of the evaluation device is easy.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a relationship between a test signal and a timer.

FIG. 3 is a diagram showing a waveform of each part of the example of FIG.

FIG. 4 is a connection diagram showing another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a diagram showing a relationship between a test signal and an ATD circuit.

FIG. 6 is a diagram showing waveforms at various portions in the example of FIG.

FIG. 7 is a connection diagram showing another embodiment of the semiconductor device according to the present invention.

8 is a diagram showing a waveform of each part of the example of FIG.

FIG. 9 is a connection diagram showing another embodiment of the semiconductor device according to the present invention.

FIG. 10 is a diagram showing waveforms at various parts in the example of FIG.

FIG. 11 is a schematic diagram showing a relationship between a conventional evaluation device and a semiconductor device.

FIG. 12 is a diagram showing waveforms at various parts during a conventional Vcc noise test.

FIG. 13 is a diagram showing waveforms at various parts during a conventional CE bar noise test.

[Explanation of symbols]

 1 Semiconductor Device 2 Evaluation Device 3 Power Supply Terminal 4 Ground Terminal 10 Timer 13, 16 Resistor 14, 20 P-Channel MOS Transistor 15 N-Channel MOS Transistor 18 ATD Circuit

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[Procedure amendment]

[Submission date] April 26, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

Next, the operation in the test mode will be described.
In the test mode, the test signal Stest becomes "H", the timer 10 is in the operating state, and the timer 10 outputs a pulse. At this time, the output signal of the NAND circuit 11 is an inverted signal of the output signal of the timer 10. When the output signal of the timer 10 becomes "L", the output signal of the NAND circuit 11 becomes "H" and the transistor 20 is turned off, so that the through current i2 does not flow from the power supply terminal 3 to the chip enable terminal 19 . Output signal of timer 10 is "H"
Then, the output signal of the NAND circuit 11 becomes “L” and the transistor 20 is turned on.
A through current i2 flows through the chip enable terminal 19 .

Claims (6)

[Claims] 1. A resistance element and a switching element connected in series between a first power supply terminal and a second power supply terminal having a potential lower than that of the first power supply terminal, and a control electrode of the switching element. And a pulse generating circuit for driving the switching element with an output pulse of the pulse generating circuit in a test mode. 2. A resistance element and a switching element connected in series between a first power supply terminal and a second power supply terminal having a lower potential than the first power supply terminal, and a control electrode of the switching element. And a timer for driving the switching element with an output pulse of the timer in a test mode. 3. A resistance element and a switching element connected in series between a first power supply terminal and a second power supply terminal having a lower potential than the first power supply terminal, and a control electrode of the switching element. And a ATD circuit, and the switching element is driven by an output pulse of the ATD circuit in a test mode. 4. A switching element connected between an external input terminal and a power supply terminal, and a pulse generation circuit connected to a control electrode of the switching element, wherein an output pulse of the pulse generation circuit is provided in a test mode. A semiconductor device driving the switching element. 5. A switching element connected between an external input terminal and a power supply terminal, and a timer connected to a control electrode of the switching element, wherein the switching element is activated by an output pulse of the timer in a test mode. A semiconductor device characterized by controlling. 6. A switching element connected between an external input terminal and a power supply terminal, and an ATD circuit connected to a control electrode of the switching element, wherein the switching is performed by an output pulse of the ATD circuit in a test mode. A semiconductor device characterized by controlling an element.