JPH0658613U - FS signal demodulation circuit - Google Patents

Abstract

(57) [Summary] [Object] To prevent the PLL of the PLL decoding circuit used for demodulating a PS signal from being locked by noise. [Structure] Add a single frequency signal to the PS signal
Input to the L decode circuit. This single frequency is selected so that the output frequency when phase-detected by the carrier wave is out of the band of the PS signal.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an FS signal demodulation circuit, and more particularly to an FS signal demodulation circuit using a PLL decoding circuit.

[0002]

[Prior art]

 FIG. 3 is a block diagram showing the configuration of a conventional circuit of this type. In FIG. 3, 1 is an FS signal input terminal, 2 is a bandpass filter for removing noise mixed in the FS signal, and BPF1 It is represented by. 3 is an amplifier using an operational amplifier, 4 is a coupling capacitor, 5 is a PLL decoding circuit, and 6 is an output terminal for a demodulated signal.

FIG. 4 is a block diagram showing a configuration example of the PLL decoding circuit 5 of FIG. 3, in which 51 is a phase detector, 52 is a voltage controlled oscillator (abbreviated as VCO), and 53 is a low-pass filter (LPF). Reference numeral 54 denotes a bandpass filter (abbreviated as BPF2) that passes the signal frequency band of the FS signal. It is well known that the phase detector 51, the LPF 53, and the VCO 52 form a PLL, and the oscillation phase of the VCO 52 is phase-locked with the phase of the carrier wave of the PS signal added via the coupling capacitor 4. Since the phase detector 51 performs the phase detection of the PS wave with the output of the VCO 52, a voltage having the signal frequency of the PS wave is obtained at the output of the phase detector 51. A demodulated signal is obtained from this voltage through the BPF 54.

As described above, when the PLL decoding circuit 5 is used, a carrier having a sufficiently large amplitude can be generated in the circuit, so that the demodulation sensitivity becomes extremely good. That is, it is possible to obtain a circuit that is strong against level fluctuations, S / N reduction, and the like. For example, good demodulation can be performed even when the carrier wave input of the PS signal is lower than the basic level by about -40 dB.

[0005]

[Problems to be solved by the device]

 The conventional FS signal demodulation circuit as described above is configured as described above, and good demodulation can be expected. However, this characteristic that demodulation sensitivity is good is that even when there is no PS signal input, There is a problem in that the PLL circuit operates due to noise, the output of the VCO 52 is mistakenly recognized as a carrier, and the noise phase-detected by the output of the VCO 52 is mistaken as a signal, as if the P S signal was input.

The present invention has been made to solve such a problem, and an object thereof is to provide a demodulation circuit for an FS signal in which the PLL decoding circuit is not locked by noise.

[0007]

[Means for Solving the Problems]

 The FS signal demodulation circuit according to the present invention constantly applies a voltage of a predetermined frequency to the input of the PLL decoding circuit, and the PLL decoding circuit operates by this voltage even when there is no PS signal input, and does not operate by noise. I did it.

[0008]

【Example】

 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, 7 is an oscillator, 8 is an attenuator, and an amplifier 3 is an output of the BPF 2 and attenuation It becomes a voltage mixer that synthesizes the voltage of the output of the device 8.

FIG. 2 is a diagram showing a design for determining the oscillation frequency of the oscillator 7 according to the present invention. In the figure, 21 indicates the pass band of the BPF 54 (see FIG. 4), and 22 indicates the output of the oscillator 7. Shows the signal frequency generated by being detected by the phase detector 51 (see FIG. 4). Even if the output of the attenuator 8 is relatively high, it does not appear at the output terminal 6 because the signal 22 does not pass through the BPF 54 having the band 21.

When the PS signal is present at the terminal 1, the demodulated signal and the signal indicated by reference numeral 22 in FIG. 2 are superimposed on the output of the phase detector 51. , BPF 54 does not pass, and the circuit shown in FIG. 1 operates as a whole as the circuit shown in FIG. When the PS signal does not exist at the terminal 1, the phase detector 51 always outputs the voltage of the frequency indicated by reference numeral 22 in FIG. 2, so the voltage of this frequency does not pass through the LPF 53, and the output of the LPF 53 is output. Since there is no DC voltage in and it is clear that the PLL circuit is not locked, noise is not mistaken for a signal.

In order to obtain the signal indicated by the reference numeral 22 in FIG. 2 as the output of the phase detector 51, the difference between the oscillation frequency of the oscillator 7 and the carrier frequency of the PS signal is f (FIG. 2) in the + or − direction. See only). Further, the output of the attenuator 8 should be about -45 dB, as long as it can suppress the PLL lock due to noise.

[0012]

[Effect of device]

 As described above, according to the present invention, it is possible to prevent an error in which the PLL of the PLL decoding circuit is locked by noise and erroneously recognizes noise as a signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an oscillation frequency of an oscillator circuit and a PS signal in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional circuit.

FIG. 4 is a block diagram showing a configuration example of a PLL decoding circuit in FIG.

[Explanation of symbols]

 5 PLL Decoding Circuit 7 Oscillator 8 Attenuator 51 Phase Detector 52 VCO

Claims (1)

[Scope of utility model registration request] 1. An oscillator that oscillates a voltage whose frequency difference with respect to a carrier frequency of an FS (frequency shift) signal is larger than a signal frequency band; An FS signal demodulation circuit comprising: a mixer amplifier for synthesizing an FS signal input and the voltage of the attenuator output; and a PLL decoding circuit for inputting the output of the mixer amplifier and performing PLL (phase lock loop) detection. .