JPH0658262B2 - Color graphic data processor - Google Patents

Description

The present invention relates to a color graphic data processing apparatus for processing color code data stored in a color graphic memory.

[Prior Art] In a graphic data processing device equipped with a color graphic display, when it is desired to change a predetermined specific color currently painted on the screen to another color, as the color data among the graphic data composed of a plurality of dots, It is necessary to detect the dot position of the dot to which the color data of the predetermined specific color is added.

Conventionally, as a similar technique for detecting the dot position of such a specific color, there is a technique disclosed in Japanese Patent Publication No. 58-22929. This technique discloses an apparatus for detecting an image position of a specific color tone from each color image signal of three primary colors. This apparatus detects each color image signal of three primary colors of dot positions sequentially scanned on an image. By analyzing, it is possible to detect whether or not the ratio (color tone) of the level of each signal of the three primary colors matches the signal level of the three primary colors separately specified on the image.

[Problems to be Solved by the Invention] However, in this technique, a dot position of an image of a specific color tone is identified by using a color image signal itself that is sequentially generated when forming an image as a color image. Therefore, in order to perform the above-mentioned discrimination, it is necessary to compare the levels of the color image signals of the three primary colors for each of the three primary colors while sequentially scanning each dot position on the image, which requires a long time for detection. There is a problem.

Moreover, in this technology, since the identification is performed by the signal level of the color image signal, the detection can be made only from the image-processed signal, and the graphic is encoded in the color graphic memory. When data is stored, the graphic data itself cannot be identified by internal processing. Therefore, when editing the graphic data stored in the color graphic memory, for example, CP
When U identifies a storage position of color code data of a specific color in the color graphic memory and performs a process of changing this color code data to code data of another color, or the identified storage position When the graphic data is edited with reference to, there is a problem that the process cannot be performed quickly.

An object of the present invention is to quickly identify a storage position of a color code corresponding to a specific display color in a color graphic memory that stores graphic data based on a color code, and to perform processing at high speed based on the storage position. To do so.

[Means for Solving the Problems] Means of the present invention are as follows.

A color graphic display, and a color graphic memory for storing color code data composed of a plurality of color designating elements, which corresponds to each dot of graphic data composed of a plurality of dots displayed on the color graphic display in a one-to-one correspondence Holding means for holding color code data composed of a plurality of color designation elements corresponding to a specific display color, and a predetermined number of color code data corresponding to a predetermined number of dots in the color graphic memory as one unit Reading means for addressing and reading out a predetermined number of color code data at the designated address; color code data read by the reading means and color code data held in the holding means;
Determining means for determining the position of the color code data that matches the color code data held by the holding means in the predetermined number of color code data by comparing each color designating element individually, By the specified address for the color graphic memory and the position determined by the determination means,
The position where the same color code data as the color code data of the specific display color is stored in the color graphic memory is identified.

[Operation] The operation of the means of the present invention is as follows.

The color graphic memory has a one-to-one correspondence with each dot of graphic data composed of a plurality of dots displayed on the color graphic display, and a plurality of color designating elements (corresponding to each color of blue, red, and green in the embodiment). Color code data composed of a plurality of color designating elements corresponding to a specific display color to be identified is stored in the holding means. To do. In this state, the reading means addresses the predetermined number of color code data corresponding to the predetermined number of dots in the color graphic memory as one unit, and reads the predetermined number of color code data at the designated address. Then, the discriminating means compares the read color code data with the color code data held in the holding means individually for each color designating element, so that among the predetermined number of color code data, The position of the color code data that matches the color code data held in the holding means is determined. By this. A position for storing the same color code data as the color code data of the specific display color in the color graphic memory is identified by the designated address and the determined position with respect to the color graphic memory.

Therefore, only by the internal processing operation for the graphic data in the color graphic memory, that is, by addressing the predetermined number of color code data corresponding to the predetermined number of dots in the color graphic memory as one unit, and read out by this designation. By determining the matching position of the color code of the specific color in the predetermined number of color code data, it is possible to identify the storage position of the specific color code in the color graphic memory, which enables high-speed identification processing. In addition, there is an advantage that the color graphic memory can be processed at high speed based on the identified storage location.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows a paint example of a graphic display. The color of area 1 in the outer peripheral portion on the screen is white, the color of area 2 in the central portion is cyan, and the color of area 3 which occupies a part of area 2. Is red. In the case of this embodiment, for example, when it is desired to change the cyan paint portion of the area 2 to another color, the graphic RA described later is used.
Graphic data for 8 dots is read from M (random access memory), and a process for identifying whether or not the color of each dot is the same as cyan, which is the specific color of the area 2, is performed simultaneously with respect to the graphic data of each dot. Therefore, the symbol 4 in FIG. 1 indicates a dot group that undergoes the color identification processing in units of 8 dots.

Next, the circuit configuration will be described with reference to FIGS. 2 and 3. FIG. 2 shows a circuit configuration diagram of a main part of an electronic computer having a graphic display. Color data (3-bit data), that is, a color code of a color to be searched for is input from a CPU (central processing unit) to a color code register 7A in the bus buffer 7 through a data bus when determining a specific color. Set. Then, color discrimination processing is performed by the circuit of FIG. 3 described later. The letters in the figure are the three primary colors blue (BLUE), red (RED), and green (GREE).
N) represents the acronym. Further, each of the bus buffer 7 has an 8-bit capacity B buffer 7B and R buffer 7
C and G buffers 7D are provided, and these buffers 7B, 7C and 7D respectively correspond to BRAM 8A, GRAM 8B and RRAM 8C in the graphic RAM 8.
The 1-byte dot pattern data read from each of the above is set via the data line. BRAM8A, R
The RAM 8B and the GRAM 8C each have a video R having a one-to-one correspondence with each bit of the display screen of the CRT display device.
AM, and each corresponds to the colors of blue, green, and red. Therefore, the bus buffer 7 and the graphic RAM 8 are
As explained in FIG. 3, gate control signals ▲ ▼, ▲
▼ is ignited by the CPU and gate controlled. Further, the graphic RAM 8 is sent to the CP via the address selector 9.
Addressed by the address data output from U to the address bus, BRAM 8A, RRAM 8B, GRA
Each pattern data of M8C is rewritten. Otherwise, the address data output from the CRTC (CRT controller) 10 is applied and addressed through the address selector 9, and the BRAM 8A, RRAM 8B, GR
Each pattern data is read from the AM8C and sent out and displayed on the CRT screen.

The 8-bit parallel data in the B buffer 7B, the R buffer 7C, and the G buffer 7D is sent to the P / S shift register 11, converted into serial dot signals, and sent to the CRT screen via the video circuit 12. It Then, the P / S shift register 11 is applied with the dot clocks D and CLK output from the CRT 10 to perform its conversion operation. Further, the video circuit 12 uses the bit clocks D and C described above.
In addition to LK, the vertical synchronizing signals V, SYC, horizontal synchronizing signals H, SYC further output by the CRTC 10 are also applied to perform a video signal generating operation.

Next, the detailed circuit of the bus buffer 7 will be described with reference to FIG. The specific color data is input from the data bus to the color code status register 7A via the gate circuit G ₁ which is gate-controlled by the gate control signal ▲ ▼.
The output of the blue bit B of the register 7A is applied to the switches SWB0 to SWB7, and the output is "1".
In case of, the output side is connected to the ON terminal, and in case of “0”, the output side is connected to the OFF terminal. The output of the red bit R of the register 7A is applied to the switches SWR0 to SWR7, and when the output is "1", the output side is connected to the ON terminal, and when the output is "0", the output side is connected to the OFF terminal. Further, the output of the green bit G of the register 7A is the switch SW.
It is applied to G7 to SWG0, and when the output is "1", the output side is connected to the ON terminal, and when it is "0", it is connected to the OFF terminal.

On the other hand, B buffer 7B, R buffer 7C, G buffer 7
1-byte dot pattern data is input to D via the gate circuits G ₂ , G ₃ , and G _4, which are both gate-controlled by the gate control signal ▲ ▼. Then, the bit outputs b7 to b0 of the B buffer 7B are input to the input terminals of the corresponding switches SWB7 to SWB0, respectively. Also R
The bit outputs b7 to b0 of the buffer 7C are input to the input terminals of the corresponding switches SWR7 to SWR0, respectively. Further, the bit outputs b7 to b0 of the G buffer 7D are input to the input terminals of the corresponding switches SWG7 to SWG0, respectively.

The OFF terminals of the switches SWB7 to SWB0 are respectively connected to the input sides of the corresponding inverters IB7 to IB0,
Further, each ON terminal is connected to the output side of each of the inverters IB7 to IB0. In addition, switches SWR7 to SWR
Each OFF terminal of 0 corresponds to the corresponding inverter IR7 ...
It is connected to the input side of IR0, and each ON terminal is connected to the output side of the inverters IR7 to IR0. Further, the OFF terminals of the switches SWG7 to SWG0 are respectively
It is connected to the input side of the corresponding inverters IG7 to IG0, and each ON terminal has an inverter IG7 to IG0, respectively.
Is connected to the output side of. And the inverter IB7,
The outputs of IB7 and IG7 are both input to the AND gate A7, and the outputs of the inverters IB6, IR6 and IG6 are input to the AND gate A6. Hereinafter, in the same manner, the three same bits of each inverter respectively correspond to the corresponding AND gate. A
5, A4, A3, A2, A1 and A0 respectively. Then, the 8-bit data output from the AND gates A7 to A0 is sent to the CPU via the data bus, and it is determined once for every 8 bits whether or not there is a dot of a color that matches the specific color.

Next, the operation will be described with reference to FIGS. 4 and 5. First, in the case of a normal display operation, the CPU outputs address data from the address bus to the GRAM 8 via the address selector 9, and the data bus also outputs blue data to the bus buffer 7.
1 byte of each red and green dot pattern data is output. One byte of blue, red, and green dot pattern data input to the GRAM 8 from the bus buffer via the data line is written in the BRAM 8A, RRAM 8B, and GRAM 8C. Then, by repeating the above operation, the dot pattern data for one screen is stored in the BRAM 8A and the RRAM 8 respectively.
When written to B and GRAM8C respectively, the graphic R
The control of AM8 is switched to CRTC10, so CR
The address data output from the TC 10 is input to the graphic RAM 8 via the address selector 9 to be addressed, and one byte, that is, 8-bit pattern data is read from the BRAM 8A, RRAM 8B, and GRAM 8C at a time, and the corresponding B buffer 7B is read. , R buffer 7
The data is input to the C and G buffers 7D, further input to the P / S shift register 11, respectively, converted into serial dot signals, and sent out to the CRT screen through the video circuit 12 to be displayed. Then, when the display processing for 1 byte is completed, the next 1
Byte dot pattern data for each RAM 8A-8C
Read from and display in the same way. The following is a repetition of the above, and when the display contents are changed, the control of the graphic RAM 8 is controlled by the CRCT 10.
To the CPU side, and the contents of the graphic RAM 8 are rewritten.

Next, the operation of discriminating the specific color will be described. Now, for example, it is assumed that a part of the display screen is painted in cyan. Then, since it is desired to change the cyan color to another color, when discriminating the cyan color, the cyan color code (specific color data) is input by a predetermined key operation. That is, as shown in FIG. 4, this cyan is obtained by a color code in which the blue bit is "1", the red bit is "0", and the green bit is "1", and this is entered by key input. . Therefore, this color code "101" is the CPU
Output to the color code status register 7A via the data bus and the gate circuit G ₁ . For this reason,
By the output of the bits B and G of "1" of the register 7A, the respective output sides of the switches SWB7 to SWB0 and SWG7 to SWG0 are both connected to the ON terminal side. Further, by the output of the bit R of "0", the respective output sides of the switches SWR7 to SWR0 are all connected to the OFF terminal side.

On the other hand, as shown in FIG. 4, the B buffer 7B, the R buffer 7C, and the G buffer 7D are now "0101001", respectively.
It is assumed that the dot pattern data of "1", "001101111", and "000011111" have been input. That is, for example, since the data of the bit b7 of each of the buffers 7B, 7C, and 7D is "0", the color of the dot shows black, and the bit b6 shows that the blue buffer 7B has "1", red,
Since the green buffers 7C and 7D are both "0", the color of the dot is blue.

Therefore, the outputs of the bits b7 to b0 of the B buffer 7B are directly input to the corresponding AND gates A7 to A0 via the ON terminals of the switches SWB7 to SWB0. Also R
The output of bits b7 to b0 of the buffer 7C is a switch SW.
Inverter IR7 ~ via the OFF terminal of R7 ~ SWR0
The inverted data “1100100” is input to IR0.
"0" is input to the corresponding AND gates A7 to A0. Further, the outputs of the bits b7 to b0 of the G buffer 7D are directly input to the corresponding AND gates A7 to A0 via the switches SWG7 to SWG0.

Therefore, as can be seen from FIG. 4, the AND gate A
The 3-bit inputs of 7 are "0", "1", and "0", respectively, and therefore their outputs are "0", and the 3-bit inputs of the AND gate A6 are "1" and "1", respectively. ",
The output becomes "0", so that the output becomes "0". Hereinafter, the respective inputs to the AND gates A5 to A0 are as shown in the drawing, and the respective outputs are all "0". Therefore, the outputs of the bits b7 to b0 of the AND gates A7 to A0 are all "0" and are sent to the CPU. Upon receiving this data, the CPU determines from all bits "0" that all the dots are colors other than cyan this time, and proceeds to the determination process for the next 8 bits.

On the other hand, as shown in FIG. 5, dot pattern data “01010101”, “00110011”, and “00” are stored in the B buffer 7B, the R buffer 7C, and the G buffer 7D, respectively.
"001111" was input, the B buffer 7B,
The output of the G buffer 7D is the AND gate A7 to A as it is.
0, and the output of the R buffer 8B is inverted to "11001100", and AND gates A7 to A0.
To enter. Therefore, the 8-bit data output from the AND gates A7 to A0 is "00000100",
Only the output of the AND gate A2 becomes "1" and is sent to the CPU. Therefore, the CPU receives this and determines that the third dot from the lower order side is a cyan color, and performs a process of changing the color to red, for example.

In the above embodiment, the process for discriminating the specific color is set to 8 dots at a time, but the process is not limited to 8 dots as long as it is a process of plural dots of 2 dots or more.

According to the present invention, only the internal processing operation for the graphic data in the color graphics memory, that is,
Address designation with a predetermined number of color code data corresponding to a predetermined number of dots in the color graphic memory as one unit, and determination of a matching position of a color code of a specific color in the predetermined number of color code data read by this designation. By the discrimination, it is possible to discriminate the storage position of the specific color code in the color graphics memory, which enables high-speed discrimination processing.
There is an advantage that the color graphics memory can be processed at high speed based on the identified storage location.

[Brief description of drawings]

FIG. 1 is a diagram showing a display example of a graphic display according to an embodiment of the present invention, FIG. 2 is a block circuit diagram of a main portion, FIG. 3 is a detailed circuit diagram of a bus buffer 7, FIGS. The figure is a diagram for explaining the operation. 7 ... Bus buffer, 7A ... Color code status register, 7B, 7C, 7D ... Buffer, 8 ... Graphic RAM, 10 ... CRT controller, 11 ...
… P / S shift register, 12 …… Video circuit, SWB
7 to SWB0, SWR7 to SWR0, SWG7 to SWG
0 ... switch, IB7 to IB0, IR7 to IR0, I
G7 to IG0 ... Inverter, A7 to A0 ... AND gate.

Claims (1)

[Claims] 1. A color graphic display and color code data composed of a plurality of color designating elements corresponding to each dot of graphic data composed of a plurality of dots displayed on the color graphic display on a one-to-one basis. A color graphic memory, holding means for holding color code data composed of a plurality of color designating elements corresponding to a specific display color, and a predetermined number of color code data corresponding to a predetermined number of dots in the color graphic memory. Is designated as one unit, and a reading means for reading out a predetermined number of color code data at the designated address, each color code data read by the reading means and the color code data held in the holding means,
Determining means for determining the position of the color code data that matches the color code data held by the holding means in the predetermined number of color code data by comparing each color designating element individually, By the specified address for the color graphic memory and the position determined by the determination means,
A color graphic data processing device characterized in that a position where the same color code data as the color code data of the specific display color is stored in the color graphic memory is identified.