JPH0654428B2 - Memory Address Generation Method for Bit-Map Display Device - Google Patents

Description

The present invention relates to a memory address generation system in a bitmap display device using a CRT (cathode ray tube) controller.

[Prior Art] Conventionally, a bitmap display device using a CRT controller has been constructed as shown in FIG. 5 or FIG. In FIG. 5, a CRT controller is shown.
The row address signal from (1) is used to read the attribute data for each row from the attribute memory (2), and the row address signal and raster address signal from the CRT controller (1) are input to the conversion circuit (3) as an address generator. After reading the dot pattern data for each scanning line in the corresponding row from the image memory (4) with the address signal from this conversion circuit (3) and converting this dot pattern data in parallel / serial by the shift register (5). The mixer (6) mixes with the attribute data to obtain a video signal to be output to the CRT (7). Further, in FIG. 6, two CRT controllers (1a) (1b) synchronized with each other generate address signals to the attribute memory (2) and the image memory (4), read corresponding data, and then mix. CRT (7) by mixing in vessel (6)
I was trying to get the video signal to be output to.

[Problems to be Solved by the Invention] As described above, in order to match the address to the attribute memory (2) with the address to the image memory (4), in the conventional example shown in FIG. The conversion circuit (3) is required, and in the conventional example shown in FIG. 6, two CRT controllers (1a) (1b) are required, so that the circuit configuration for generating the memory address becomes complicated. There was a point.

The present invention has been made in view of the above problems, and an object of the present invention is to obtain a memory address generation method in a bit map display device that can simplify the circuit configuration.

[Means for Solving Problems] In the memory address generation method according to the present invention, attribute data in units of rows is read from the attribute memory based on an address signal from the CRT controller, and at the same time, in units of scanning lines in a corresponding row from the image memory. To read the row data of the image memory at the beginning of each row of the attribute memory in a bitmap display device in which dot pattern data is read and these read data are mixed by a mixer to obtain a video signal to a CRT. Is stored in advance as data, the row address data is read from the attribute memory at a timing before the data display period, and the row address data is used as the address signal of the image memory. is there.

[Operation] A row address for reading the row data of the image memory is stored in advance at the beginning of each row of the attribute memory as data. When an address signal for display is sent from the CRT controller to the attribute memory, the attribute data in units of rows is sent from the attribute memory to the mixer. The row address data stored in the attribute memory is read at a timing before the data display period by the timing signal from the CRT controller, and this row address data is sent to the image memory as an address signal. On the other hand, C
A raster address signal is sent from the RT controller to the image memory. Therefore, the dot pattern data for each scanning line within the row address read out from the attribute memory is read out from the image memory and sent to the mixer, which is mixed with the attribute data and output to the CRT. The signal is obtained. Therefore, a special circuit (for example, a conversion circuit) such as an address generator for generating the row address signal of the image memory
Becomes unnecessary.

[Embodiment] FIG. 1 is a block diagram showing an embodiment for realizing the memory address generation system according to the present invention. The same parts as those in FIGS. 5 and 6 are designated by the same reference numerals.

In FIG. 1, (1) is a general-purpose LSI for controlling a cathode ray tube.
This CRT controller (1) is a CRT controller formed by
Address signal to attribute memory (2) via (0) and dual port R via raster address bus (11)
The raster address signals are sent to the image memory (4) composed of AM (random access memory). In the image memory (4), one dot (bright spot) on the display screen is one
It consists of a bit map memory corresponding to bits, and has m columns in the horizontal direction (eg 80 columns) and n rows in the vertical direction as shown in FIG.
The area is divided into m × n (80 × 40) divided areas (for example, 40 rows), and this one divided area corresponds to one word.

The attribute memory (2) is the image memory
Blink (blink) corresponding to each section area of (4), reverse
Stores attribute data such as (reverse), underline, and brightness (luminance) in 1-word units m × n
1 × which has a partitioned area (for example, 80 × 40) and stores the row address (n ₁ , n ₂ , ... N _n ) for reading the row data of the image memory (4) at the beginning of each row as data 1 ×
It has n (eg 1 × 40) divided areas, and as a whole (m + 1)
It has a divided area (81 × 40) of × n.

A latch circuit (13) and a mixer (6) are coupled to the attribute memory (2) via a data bus (12), and the latch circuit (13) is a data display period from the CRT controller (1). By the timing signal before (for example, a display timing signal), latch the row address data (for example, n ₁ ) stored at the beginning of the row of the attribute memory (2),
This row address data is sent to the image memory (4) as an address signal. Image memory (4)
The serial data output side of is connected to the mixer (6) via a shift register (5). The mixer (6) mixes the dot pattern data from the image memory (4) with the attribute data from the attribute memory (2) to obtain a video signal, and outputs the video signal from a CRT (cathode ray tube) (7). ).

Next, the operation of the above embodiment will be described with reference to FIG. 3 and FIG. The image memory (4) and the attribute memory (2) store dot pattern data and corresponding attribute data in each area of the m × n section under the control of a CPU (central processing unit) not shown. At this time, in the head section of each line of the attribute memory (2), as shown in FIG. 2, line address data (n ₁ , n ₂ , ... N _n ) for reading out the line data of the image memory (4) is stored. It is stored in advance.

Next, the display mode will be described. In this display mode, the image memory (4) formed by the dual port RAM is used in the transfer mode. Therefore, when the start address is set in the image memory (4), the image memory (4) sequentially outputs the image data in a predetermined bit unit every time the shift clock is input. In the display mode, first, predetermined row data is read from the attribute memory (2) by an address signal from the CRT controller (1). At this time, the display timing signal from the CRT controller (1) is as shown in FIG. 3 (a), and the row address and C read from the attribute memory (2)
Image data is read from the image memory (4) by the raster address from the RT controller (1),
This image data goes through the shift register (5) and the mixer
Since it is output to the CRT (7) via (6), the actual display timing is as shown in FIG. That is, as shown in FIG. 3 (a), the display timing signal from the CRT controller (1) changes from the L level to the H level from t ₁ o'clock to t ₂ o'clock which is one word time (display period). Row address data ni (i = 1, 2, ... N) stored at the beginning of the corresponding row in the attribute memory (2) (for example, “L ₄ , L ₃ , L ₂ , L ₁ , L ₀ ”) is read and the same figure (c)
It is output at the timing shown in (4), is latched by the latch circuit (13), and this row address data "L _{4 to} L ₀ " is sent to the image memory (4) as a row address.

On the other hand, since the raster addresses “R ₃ , R ₂ , R ₁ , R ₀ ” are sent from the CRT controller (1) to the image memory (4) via the raster address bus (11), the start address is It looks like Figure 4. In this figure,
“S ₅ , S ₄ , S ₃ , S ₂ , S ₁ , S ₀ ” is a horizontal scroll start address stored in the scroll register in the CRT controller (1).

After t ₂ o'clock at the start of the display period, m columns of the row address “L _{4 to} L ₀ ” (for example, n _1st row) from the attribute memory (2).
Attribute data (80 words) is sequentially read and input to the mixer (6). On the other hand, from the image memory (4), every raster address “R ₃ , R ₂ , R ₁ , R ₀ ” in each corresponding row address “L _{4 to} L ₀ ” (n _1st row) (each scanning line) The dot pattern data is read out and input to the mixer (6) via the shift register (5). When the display of one scanning line is completed on the CRT (7) by the video signal output from the mixer (6), the display timing signal is changed from H level to L level at t ₃ as shown in FIG. 3 (a). Change to level and then 47
Changes from t ₄ at L level has passed word to H level, t ₄ 1 word elapsed t ₅ o'clock o'clock, row address "L ₄ ~L _{0" (1} line m) following rasters in In accordance with the address, the CRT (7) shifts to the display for the next one scanning line in the same manner as described above. In this way, the row address “L _{4 to} L ₀ ” (n
_{When the} reading and display by all raster addresses in the ( _1st row) (equivalent to 16 scanning lines, for example) are completed, CR
T is incremented by the address signal from the controller (1) 1 (+1) row address data "L ₄ ~L _0" (e.g., n ₂ line) is read from the attribute memory (2) a latch circuit (13 ). Therefore, the row address data “L _{4 to} L ₀ ” (n _2nd row) is sent to the image memory (4) as a row address, and from the image memory (4) within n ₂ rows in the same manner as described above. The image data (dot pattern data) for each scanning line is read out, and the attribute data in 1 word units in the n ₂ rows is read out from the attribute memory (2). ) And CR as a video signal
It is output at T (7). Image memory
The data at the corresponding address in (4) and the attribute memory (2) is displayed on the CRT (7) by the raster scan method.

[Effects of the Invention] As described above, the memory address generating method in the bitmap display device according to the present invention stores the row address for reading the row data of the image memory in advance at the beginning of each row of the attribute memory as data. The row address data stored in the attribute memory was read at a timing before the data display period and used as an address signal for reading the row data to the image memory. Therefore, unlike the conventional case, a special circuit such as an address generator for generating the row address signal of the image memory is not required, and the circuit structure can be simplified as compared with the conventional case. Further, when the screen is scrolled, it is not necessary to rewrite all the dot pattern data in the image memory by the CRT controller as in the past, and it is only necessary to rewrite the line address of the attribute memory. All functions such as interlace and non-interlace can be applied to the image memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus for realizing an embodiment of a memory address generation system according to the present invention, FIG. 2 is an explanatory view for explaining the structures of an attribute memory and an image memory, and FIG. 3 shows a display timing. FIG. 4 is a timing chart, FIG. 4 is an explanatory diagram for explaining the contents of the start address (16 bits), and FIGS. 5 and 6 are block diagrams of an apparatus for realizing the conventional method. (1) …… CRT controller, (2) …… Attribute memory, (4) …… Image memory, (6) …… Mixer, (7)…
CRT, (13) Latch circuit, n _{1 to} n _n Row address data (address signal).

Claims (2)

[Claims] 1. Attribute data for each line is read from an attribute memory based on an address signal from a CRT controller, dot pattern data for each scanning line in a corresponding line is read from an image memory, and these read data are read by a mixer. Mixed and CRT
In a bit map display device adapted to obtain a video signal to, a row address for reading row data of the image memory is stored in advance at the beginning of each row of the attribute memory as data, and the row address before the data display period is stored. A memory address generation method in a bit map display device, wherein row address data is read from the attribute memory at a timing and the row address data is used as an address signal of the image memory. 2. The bit map according to claim 1, wherein the image memory is a dual port RAM, and the row address stored in advance in the attribute memory is a start address for starting the dual port RAM in the transfer mode. Memory address generation method for display device.