JPH0653320A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the length of a wiring connecting points disposed in an oblique direction by employing a channel region wiring at an oblique angle to a side of the semiconductor chip. CONSTITUTION:A wiring 1 is formed along lines of a rhombic lattice composed of a first imaginary line 2 in the Z1 direction and a second imaginary line 3 in the Z2 direction, both at an oblique angle to a side of the semiconductor chip. A wiring pattern 1a in the Z1 direction and that 1b in the Z2 direction are disposed at an angle of 45 deg. and 135 deg. to a side of the semiconductor chip, respectively, with an insulating film in-between. Further, an imaginary line connecting the start point A and end point B of the wiring 1 is formed at an angle of 20-70 deg., 110-160 deg., 200-250 deg. or 290-340 deg. to a side of the semiconductor chip. This shortens the length of a wiring connecting points disposed in an oblique direction and reduces the wiring load, promoting high speed operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a wiring layout of the semiconductor device.

In recent years, with the increase in the speed and performance of LSIs, not only the basic delay of only the logic circuit (gate) portion but also the speed increase of the load delay in which the wiring load is attached to the gate (the shortening of the load wiring length) has become possible. Is required. For this reason, the load wiring length has been shortened due to the miniaturization of patterns, the high integration, and the like, but at present, further speedup is required.

[0003]

2. Description of the Related Art FIG. 4 is a plan view showing a conventional wiring layout. In a semiconductor device, for example, when wiring between a plurality of gates G arranged in a matrix,
As for the wiring direction (channel), as shown in FIG. 4 (a), the wirings are arranged in the horizontal and vertical directions parallel to the respective sides of the rectangular chip, that is, in the X and Y directions.

Therefore, when connecting the gates G in the diagonal direction, the pattern in the X direction and the pattern in the Y direction are used as shown by the chain double-dashed line. When wiring the gates G in the diagonal direction,
As shown in (b), it is composed of only a horizontal direction (X direction) pattern 41 and a vertical direction (Y direction) pattern 42, and these are arranged via an insulating film (not shown), and a contact hole is formed. It is connected through 43.

The wiring length in this case is determined by the sum of the length in the vertical direction and the length in the horizontal direction. For example, as shown in FIG. 4 (b), when the direction from the point A to the point B is oblique to the side of the chip, the length L of the wiring 40 arranged at these points is When asked, it becomes as follows. However, A
The XY coordinate of the point is (X _A , Y _A ), and the XY coordinate of the point B is (X
_B , Y _B ).

L = | X _A −X _B | + | Y _A −Y _B | (1) Note that the lattice line formed by virtual lines in the X and Y directions (vertical and horizontal) has a pitch in the X direction of dx. , The pitch in the Y direction is d
y, and dx and dy are not necessarily set equal.

[0007]

By the way, it is necessary not only to reduce the delay of the signal of the gate section with the increase in the speed and performance of the LSI, but also to reduce the delay due to the impedance of the wiring connecting the gates. There is.

However, when the wiring is formed only by the X-direction channel region and the Y-direction channel region as described above, the wiring length L becomes too long and the impedance becomes large when the starting point and the ending point of the wiring are separated. However, there is a problem that it hinders the speedup.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device capable of shortening the wiring length.

[0010]

[Means for Solving the Problems]
As illustrated in FIG. 2, the first conductor pattern 1a and the second conductor pattern 1b, which are respectively disposed on the upper and lower layers with the insulating film interposed, are arranged on the side of the square semiconductor chip 10 by 4
The semiconductor chip is arranged in the directions of 5 ° and 135 °, and the direction from the starting point A to the ending point B of the wiring 1 formed by at least one of the first conductor pattern 1a and the second conductor pattern 1b is the semiconductor chip. 20 ° to one side of 10
~ 70 °, 110 ° -160 °, 200 ° -250 °,
This is achieved by a semiconductor device characterized by being inclined to any of 290 ° to 340 °.

Alternatively, the first wiring 1 is arranged along a grid line that is oblique to the side of the square semiconductor chip 10.
And a second wiring 40 formed along the vertical and horizontal lattice lines parallel to the respective sides of the semiconductor chip 10.

Alternatively, as illustrated in FIG. 3, a plurality of gates formed on a square semiconductor chip are wired in a direction parallel to a direction parallel to the sides of the semiconductor chip,
A first wiring channel region connecting between the gates arranged in the direction of the side of the conductor chip, and wiring obliquely to the side of the semiconductor chip, and obliquely to the side of the semiconductor chip. And a second wiring channel region that connects the gates located to each other.

[0013]

[Operation] According to the present invention, since the wiring 1 in the diagonal channel region with respect to the side of the semiconductor chip 10 is adopted, the wiring length connecting the points arranged in the diagonal direction is shortened,
The wiring load is reduced and the speedup is further promoted.

When the diagonal wiring 1 is composed of the conductive patterns 1a and 1b inclined at 45 ° and 135 ° with respect to the side of the semiconductor chip 10, 20 ° with respect to the side. ~ 70 °, 110-160 °, 200 °
It is clear from Table 1 described later that it is most effective for the wiring that connects two points in the directions of ˜250 ° or 290 ° to 340 °.

Further, since the wiring 1 formed by the diagonal channels and the wiring 40 formed by the vertical and horizontal channels are present together, the most effective wiring can be achieved by forming the wiring by selecting the channel in the direction which can be shortened. Become.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a wiring layout showing an embodiment of the present invention.

In FIG. 1A, reference numeral 1 is a part of wiring formed in the semiconductor device, and the wiring direction (channel) of this wiring 1
Are formed along a lattice line having diamond-shaped eyes formed by a first virtual line 2 in the Z ₁ direction and a second virtual line 3 in the Z ₂ direction that are oblique to the sides of the semiconductor chip. .

Of the wiring 1, the wiring pattern 1a in the Z ₁ direction and the wiring pattern 1b in the Z ₂ direction are formed via an insulating film (not shown), and these are formed via a contact hole 4. The contact hole 4 has a height that can be ignored.

By the way, the first imaginary line 2 and the second imaginary line 3 in this case are inclined at θ and 180 ° −θ with respect to one side, and a plurality of them are drawn at equal intervals. This is a line drawn, and the distance d ₁ between the first virtual line 2 and the second virtual line 3
The intervals d ₂ of the _two are equal. If these intersections are connected by a vertical line and a horizontal line, as shown in FIG. 1B, a third virtual line 5 in the X direction and a fourth virtual line 6 in the Y direction parallel to the sides of the semiconductor chip. Vertical and horizontal grid lines are formed, which correspond to the conventional XY wiring directions shown in FIG. 4 (b).

In this case, the distance d between the third virtual lines 5
distance _x and the fourth virtual line 6 d _y will be determined with the first virtual line 2 by a second virtual line 3. Next, the shortest length of the wiring formed along the above-mentioned diagonal channel will be determined based on FIGS. 1 (a) and 1 (b).

First, let A be the starting point and B be the ending point of the wiring.
These are displayed by the coordinates of the grid lines in the X direction and the Y direction, and are set as point A (X _A , Y _B ) and point B (X _B , Y _B ). In this case, if the distance in the X direction between the two points is X ₀ , then X ₀ = |
X _A −X _B |, and if the distance in the Y direction is Y ₀ , then Y ₀
= | Y _A -Y _B | become.

If θ = tan ⁻¹ (d _y / d _x ), then the shortest length L ₁ between points A and B along the diagonal channel is determined as follows. When X ₀ ≧ Y ₀ L ₁ = X ₀ / cos θ (2) When X ₀ ≦ Y ₀ L ₁ = Y ₀ / sin θ (3) According to this, when d _y = d _x , Ie Z ₁ direction and Z ₂
If the inclination of the direction is 45 ° and 135 °, X ₀ ≧
When Y ₀ , L ₁ = √ (2X ₀ ² ), and when X ₀ ≦ Y ₀ , L ₁ = √ (2Y ₀ ² ).

On the other hand, when the wiring length L ₂ based on the vertical and horizontal channels is obtained, L ₂ = | X _A −X _B | + |
Y _A -Y _B | become. Therefore, the inclinations θ in the Z ₁ direction and the Z ₂ direction with respect to one side of the semiconductor chip are 45 ° and 1 respectively.
Assuming that the wiring length is 35 °, the wiring length from the point A as shown in FIG. 2 to the point B surrounded by a circle is diagonal (Z ₁ / Z
₂ ) The wiring length L ₁ along the channel and the wiring length L ₂ along the vertical and horizontal (X / Y) channels are both calculated based on the equations (1) to (3). The start point (point A) is fixed at the origin (0, 0) of the XY coordinates, and the position of the end point (point B) is variable.

And L₁, L₂The unit of
The results are shown in Table 1, and Z₁/ Z₂Cha
Signal wiring length L in the channel₁And signal wiring on X / Y channels
Long L ₂When comparing the effective areas of, the positive direction on the X-axis is the reference
Then, from the point A, approximately 20 ° to 70 °, 110 ° to 16
B point (end point) such as within the range of inclination of 0 °
For L₁≧ L₂And the diagonal channel is effective
It can be seen that it is. Also, not shown in figures and tables
About 200 ° -250 °, 290 ° -340 °
Can be shortened by wiring the diagonal channels.

On the contrary, when there is a point B (end point) such as in the other range, the conventional vertical and horizontal directions (X /
It can be seen that the Y) channel can shorten the wiring length between point A and point A.

[0026]

[Table 1]

As described above, the diagonal wiring is not always effective at all wiring points, and it is most effective if the X / Y direction channel region and the Z ₁ / Z ₂ channel region are used together.

For example, as shown in FIG. 3, four block regions 11 to 14 closed in the semiconductor chip 10 are provided.
When a gate circuit is formed in each of the four block regions 11 to 14, the four block regions 11 to 14 are wired as vertical and horizontal (X / Y) wiring channel regions, and a part of the wiring connecting the block regions 11 to 14 is obliquely connected. It is also possible to apply diagonal wiring as the (Z ₁ / Z ₂ ) wiring channel region. In the vertical and horizontal channel regions, the wiring 40 in the direction as shown in FIG. 4 is formed.

In this example, the effect of the diagonal wiring channel is greater when connecting two points in the diagonal direction such as the block areas 11 and 14 in the diagonal direction. On the contrary, when connecting between the block regions 11 and 13 in the vertical direction or the horizontal direction, the opposite effect is obtained, so that an X / Y wiring channel for inter-block connection may be used together.

As a result, if the diagonal wiring channel is used only within the effective range, the wiring length can be shortened significantly, and
It can be seen that SI can be speeded up and highly integrated. In addition,
When wiring the logic circuits (gates) together, LS
With the I gate arranged, the vertical and horizontal channels and the diagonal channels may be assigned to more optimal locations, and then the gates may be connected in this order.

Further, the wiring layout of the diagonal channels may be limited to the wiring portion not related to the signal wiring channel, for example, the bias voltage supply line, the address line of the memory section or the element connection wiring in the gate.

Further, when the wiring is oblique, if the bulk element connected to this wiring is also formed in the same direction, the wiring can be connected easily. By the way, in the above-described embodiment, the case where the XY regions are separated has been described, but one wiring layer in the vertical direction or the horizontal direction may be added to the diagonal wiring formed of the two conductive patterns, or the vertical and horizontal directions may be added. Two layers of wiring in the direction may be added, and an insulating film may be formed between the wirings. For example, in the case of forming a diagonal wiring of 45 ° and 135 °, the wiring length may be shortened by laminating wiring monks in at least one direction of 90 ° and 180 °.

In addition, when the above-mentioned diagonal wiring is crawled as a thick power wiring, if there are thin signal lines above and below the power wiring, the stress of the film of the power wiring may add to the signal line and cause disconnection. In that region, stress can be suppressed by arranging the power supply wiring in parallel with the signal line.

In the above-described embodiment, the pitch d of each of the first line 2 and the second line 3 in the Z ₁ and Z ₂ directions.
_{Although 1} and d ₂ are the same, different pitches may be used.

[0035]

As described above, according to the present invention, since the wiring in the diagonal channel region is used with respect to the side of the semiconductor chip, the wiring length connecting the diagonally arranged points can be shortened. Therefore, the wiring load can be reduced and the speedup can be promoted.

If the diagonal wiring is composed of a conductive pattern inclined at 45 ° and 135 ° with respect to one side of the semiconductor chip, 20 ° with respect to that side.
Most effective for wiring connecting two points in the directions of -70 °, 110 ° -160 °, 200 ° -250 ° or 290 ° -340 °.

Further, according to the present invention, since the wiring of the diagonal channel and the wiring of the vertical and horizontal channels coexist, the most effective wiring can be formed by selecting the channel in the direction which can be shortened. Will be possible.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a wiring path of a device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a start point and an end point of a wiring route of the device of one embodiment of the present invention.

FIG. 3 is a plan view showing a layout of an apparatus according to an embodiment of the present invention.

FIG. 4 is a plan view showing a conventional wiring layout.

[Explanation of symbols]

 1 Wiring 2 1st line 3 2nd line 4 Contact hole 5 3rd line 6 4th line 10 Semiconductor chip 11-14 Block area

Claims (3)

[Claims] 1. A first conductor pattern (1a) and a second conductor pattern (1b), which are respectively arranged in upper and lower layers with an insulating film interposed therebetween, have an angle of 45 ° with respect to one side of a square semiconductor chip (10). And a wiring (1) arranged in the direction of 135 ° and formed by at least one of the first conductor pattern (1a) and the second conductor pattern (1b).
The direction from the starting point (A) to the ending point (B) of the semiconductor chip (10) is 20 ° to 70 °, 110 to 110
A semiconductor device, which is inclined at any of 160 °, 200 ° to 250 °, and 290 ° to 340 °. 2. A first wiring (1) arranged along a grid line oblique to a side of a square semiconductor chip (10).
And a second wiring (40) formed along vertical and horizontal lattice lines parallel to each side of the semiconductor chip (10). 3. A plurality of gates formed on a rectangular semiconductor chip, and between the gates arranged in a direction perpendicular to a direction parallel to a side of the semiconductor chip and arranged in a direction of a side of the conductor chip. And a second wiring channel region that connects between the gates that are diagonally connected to the sides of the semiconductor chip and that are located diagonally to the sides of the semiconductor chip. A semiconductor device comprising: