JPH0652947B2 - Descrambler - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a descramble apparatus having a function of receiving a scrambled (encrypted) television signal and descrambled (decrypted) the television signal.

[Technical background of the invention]

In recent years, scramble transmission has attracted attention as one of the transmission modes of television signals. This is to prevent unauthorized viewing by anyone other than the specified person and transform and transmit the television signal. The receiving side can obtain a normal image only by preparing a special descrambler for decoding. it can.

Although various scrambling methods for television signals have been proposed, one of the methods will be described below as an intra-line rotation method. The in-line rotation method is based on the NTS on the transmitting side as shown in Fig. 9 (a).
The video period p of the C video signal 91 is divided into two at arbitrary points and replaced, and a digital sync signal 93 giving an absolute address to the horizontal sync portion 92 is added, and the scramble signal 96 is transformed into the format shown in FIG. 9 (b). As. At this time, the information on the division points is transmitted together with another system, for example, audio data. Here, the address x of the division point is given in units of 108 blocks obtained by dividing the video period into 108 equal parts. The video period p is exchanged at the upper division point x, but blocks for address x-1 and x are newly prepared as margins 94 and 95 for re-decoding to be performed by the receiving side. A margin 94 is added before the address x, and a margin 95 is added after the address x-1. When the scrambled video signal is digitized and processed on the receiving side, sampling is usually performed at 4 _sc ( _sc : color subcarrier frequency). Therefore, the
As shown in Fig. 10 (a), one horizontal period is 910 depending on sample points.
It will be divided into equal parts. The absolute address corresponds to this sample point, so that the address x in block units takes a value for every 7th address such as 140th address, 147th address, ..., 903th address, 910th address.

FIG. 10 (b) is an enlarged view of the digital synchronizing signal 93 added to the horizontal synchronizing portion 92. The digital synchronizing signal 93 is inserted in the addresses 19 to 64, its frequency is 4/5 _sc , and has 7 cycles. Since the above-mentioned address x is grasped with reference to this digital synchronization signal 93, if the address of the digital synchronization signal 93 is correctly detected on the receiving side, the decoding point address read from the division point address x sent together with the audio signal. y (see FIG. 9 (b)) can also be known accurately, and the scramble signal 96 can be properly decoded without causing a hue shift or the like. In addition to the digital synchronization signal 93, the horizontal synchronization portion 97 of the scramble signal 96 is transmitted once per frame, and the frame synchronization signal 98 serving as a frame synchronization reference signal and the scrambling timing are changed. Occasionally, a scramble timing signal 99, which is transmitted once every horizontal period over one frame and serves as a switching reference signal for various scramble data, is added.

The scrambled signal described in detail above is based on the decoding point information y read from the division point information x on the receiving side, and the video period p
Are replaced, the margins 94 and 95 and the digital synchronizing signal 93 are removed, and the synchronizing signal 92 is replaced, and the data is decoded as shown in FIG. 9 (c).

[Problems of background technology]

As described above, in order to properly descramble the scrambled signal 96, it is necessary to accurately detect the digital synchronization signal 93 and grasp the decoding point y. If this is not done, a hue shift or the like will occur on the projected image receiving screen. Therefore, at the present time when scrambled transmission is becoming widespread, a descrambler having a highly accurate synchronization detection circuit which is low in cost, has no adjustment, and is suitable for a digital IC is desired.

[Object of the Invention]

The present invention has been made in view of the above demands, and an object of the present invention is to provide a descrambling device having an accurate descrambling function.

[Outline of Invention]

In order to achieve the above object, the present invention first enhances the detection accuracy of a horizontal synchronization signal that is a reference thereof before digital synchronization detection. Specifically, the width and periodicity of the horizontal sync signal portion of the composite sync signal separated from the video signal are judged, and this is recognized as a horizontal sync signal only when certain conditions are met, and a proper horizontal sync signal is obtained. . In the present invention, the precision of the detection itself of the digital synchronization signal is improved by using the highly accurate horizontal synchronization signal thus obtained for the digital synchronization detection. Further, according to the present invention, the continuity of the phase shift between the phase information for specifying the decoding point at the time of descrambling and the phase of the absolute address obtained by the digital sync signal detection is judged, and the decoding point is accurately grasped and the proper data is detected. Guarantee scrambling.

Example of Invention

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a decoding circuit 10 of a descrambling device according to the present invention.
It is a block diagram showing a 0 portion.

The scrambled video signal 96 is band-limited by the low pass filter (LPF) 1 and then supplied to the A / D conversion circuit 2.
Here, sampling and quantization are performed and the digital scrambled video signal 3 is output. The sampling frequency _{s in} this case is _s = 4 _sc , and the sampling phase is synchronized with the absolute address of the digital synchronizing signal. The clock 4 which gives the sampling timing is generated by the clock generation circuit 5, and the A / D conversion circuit 2 and the decoding circuit 1 are provided.
It is supplied to 00 and used as a reference for circuit operation. The digital scramble video signal 3 is supplied to the clamp calculation circuit 6 and clamp error calculation is performed at the timing of the burst gate pulse 8 output from the timing generation circuit 7, and the D / A conversion circuit 10 is supplied as the digital clamp control signal 9.
Is supplied to. The burst gate pulse 8 gives the timing of color burst integration for detecting the magnitude of the pedestal level in the clamp calculation circuit 6, and has a width of 3 cycles of color burst, that is, 12 samples. The D / A conversion circuit 10 D / A converts the input digital clamp control signal 9 and outputs it as an analog clamp control signal 11. The clamp control signal 11 is added as a voltage to the scramble signal 96 to be clamped.

The digital scrambled video signal 3 is sent to the PLL arithmetic circuit 1
A PLL error calculation is performed with the digital synchronization reference signal 14 at the timing of the digital synchronization gate pulse 13 that is supplied to 2 and output from the timing generation circuit 7. The digital synchronization gate pulse 13 gives the timing of the phase error integration for detecting the phase of the digital synchronization signal 93 in the PLL arithmetic circuit 12, and the digital synchronization signal 3
It has a width of one cycle, that is, 15 samples. The digital synchronization reference signal 14 is obtained by dividing the clock 4 by 5 by the frequency dividing circuit 51, and its phase is 19 which is the absolute address of the digital synchronization signal.
It corresponds to the street address, 24, 29, etc. The digital PLL control signal 15 output from the PLL arithmetic circuit 12 is converted into an analog signal 17 via the D / A conversion circuit 16 and supplied to the clock generation circuit 5. The clock generation circuit 5 outputs the clock 4 whose phase is controlled by the analogized control signal 17. As a result, the sampling phase matches the absolute address of the digital sync signal 93.

The scrambled video signal 96 is also supplied to the sync separation circuit 18, where the sync separation is performed and the composite sync signal 19 is output. The composite sync signal 19 is further supplied to a horizontal sync detection circuit 20 where horizontal sync is detected and a horizontal sync detection pulse 21 is output. The horizontal synchronizing signal 21 is supplied to the timing generating circuit 7, where the burst gate pulse 8, the digital synchronizing gate pulse 13, and the digital synchronizing timing pulse 22 are generated and output. The digital sync timing pulse 22 is a gate pulse for detecting the first digital sync signal 93, and it detects the first falling edge of the digital sync signal 93, which is address 22.
It is designed to fall near the address (see Fig. 10 (e)).

The digital scramble video signal 3, the digital sync reference signal 14 and the digital sync timing pulse 22 are supplied to the digital sync detection circuit 23, the absolute address 24 is detected, and the descramble reference signal 24 is output (10th).
(See Figure (h)). The descramble reference signal 24 is supplied to the phase comparison circuit 25 and output from the horizontal write counter 26.
The phase is compared with the signal 27 at the address 24. When the phases are out of phase, the phase control signal 28 is supplied to the horizontal writing counter 26,
The phase shift of the 24th address signal 27 output from the horizontal writing counter 26 is corrected.

A decoding point address (y) signal 30 is supplied to the horizontal read counter 29 from another system, and a read address 31 for descrambling is output. The horizontal read counter 29 is controlled by the phase control signal 32 from the horizontal write counter 26 so that both counters operate in synchronization.

The digital scrambled video signal 3 is supplied to the 2H memory 33. Here, the digital scrambled video signal 3 has a write address 34 supplied from the horizontal write counter 26.
Are written by the read address 31 supplied from the horizontal read counter 29, and the video period p is replaced again.

By the way, the digital synchronization detection circuit 23 detects the frame synchronization signal 98 added to the horizontal synchronization portion 97 of the digital scrambled video signal 3, and outputs the frame synchronization detection signal 35, which serves as a frame synchronization reference signal, to the phase comparison circuit 36. Supply. A frame synchronization reference signal 38 is also supplied from the frame counter 37 to the phase comparison circuit 36, and phase comparison is performed between the frame synchronization detection signals 35. If there is a phase shift as a result of comparison, the frame synchronization reference signal 38
The comparator circuit 36 supplies the phase control signal 39 to the frame counter 37 to correct the phase of the signal. The frequency 2 output from the horizontal writing counter 26 is applied to the frame counter 37.
An input signal 40 of _H ( _H : horizontal frequency) is supplied.

Now, the horizontal writing counter 26 and the frame counter
Both outputs 41 and 42 of 37 are supplied to the synchronizing signal generating circuit 43. The synchronization signal generation circuit 43 generates a synchronization signal 44 and supplies it to the synchronization replacement circuit 45. The reassigned video signal 46 output from the 2H memory 33 is also guided to the synchronization reassignment circuit 45. Since the digital synchronization signal 93 remains in the video signal 46, the synchronization reassignment circuit 45 reassigns the digital synchronization signal 93 and the synchronization signal 92,
It outputs a proper digital NTSC video signal 47. The video signal 47 is converted into an analog NTSC video signal 49 via the D / A converter 48, and is interpolated by passing through the LPE 50 in the next stage, and is output in a decoded state.

The above is the outline of the descrambling device according to the embodiment of the present invention. Next, a highly accurate address detection method, which is a characteristic part of the present invention, will be described in detail.

FIG. 2 is a block diagram showing an embodiment of the horizontal sync detection circuit 20 according to the present invention. The pulse width detection circuit 201 detects the width detection pulse 202 from the composite sync signal 19 separated from the scrambled video signal 96 by using the clock 4, and outputs this to the period measurement circuit 203. The period measurement circuit 203 outputs the detection pulse 204 to the timing generation circuit 213,
The count value 205 by the built-in counter at the time of obtaining this detection pulse 204 is output to the period value integration circuit 206. The timing generation circuit 213 outputs a timing signal 207 required for period value integration and a timing signal 208 required for the determination circuit 212 based on the detection pulse 204. The cycle value integration circuit 206 integrates the count value 205 input based on the timing signal 207, and outputs the average value signal 209 indicating the average value of the input measurement data to the difference calculation circuit 210. Since the count value 205 is input to the difference calculation circuit 210, the difference calculation between the average value 209 and the count value 205 is performed here, and the difference signal 211 indicating the difference result is output to the determination circuit 212. The determination circuit 212 determines the difference signal 211
Is detected by the timing signal 208 having a predetermined phase relationship with the detection pulse 204, and the horizontal synchronization detection pulse 21 is output only when the absolute value is smaller than the predetermined value.

Next, the operation of this embodiment will be described with reference to the timing charts shown in FIGS. The pulse width detection circuit 201 counts the pulse width of the composite synchronizing signal 19 shown in FIG. 3 in the period of "1" with the clock 4 and when the pulse of "1" continues for about 1 microsecond, it is shown in FIG. The width detection pulse 202 is output at the timing. The cycle measuring circuit 203 outputs the detection pulse 204 at the timing shown in FIG. 4 when the width detection pulse 202 is continuously input at a predetermined cycle as shown in FIG. In the above operation of the cycle measuring circuit 203, the cycle is measured by counting the clock 4 with the built-in 10-stage counter, and the cycle corresponding range is Is set to. Therefore, the detection pulse 204 is obtained only for the width pulse 202 which is continuously generated and within the period corresponding range. However, in FIG. 4, a indicates omission and b indicates noise. Further, the cycle measuring circuit 203 outputs a count value 205 indicating the count value of the built-in 10-stage counter at the time when the detection pulse 204 is obtained, and this count value 205 is
It is the cycle measurement data of the width detection pulse 202 measured in units of clock 4 with a 10-bit digital signal. In addition,
The clock 4, the detection pulse 204, and the count value 205 indicating the period measurement data have the timing relationship shown in FIG.

The period value integration circuit 206 has an LPE (low pass filter) characteristic, integrates the input count value 205 indicating the period measurement data, and outputs an input measurement data average value signal 209 indicating the average value of the measurement data. The average value signal 209 and the count value 205 indicating the cycle measurement data are input to the difference calculation circuit 210, where the difference between the two is calculated. The decision circuit 212 takes the absolute value of the difference signal 211, and its value is in timing with the detection pulse 204 and the timing pulse 208 shown in FIG.
The horizontal sync detection pulse is detected at the timing shown in FIG. 5 only when the absolute value is smaller than the predetermined value.
21 is output. In addition, from FIG. 5, the horizontal synchronization effect pulse 21
When a predetermined condition is satisfied, is obtained 2 clocks after the detection pulse 204 in units of 4 clocks.

According to this embodiment, the width detection pulse 20
2, the continuity and periodicity of the width detection pulse 202 are measured to detect the detection pulse 204 and the count value 205 indicating the period measurement data.
To obtain a difference signal 211 indicating the difference between the count value 205 and an average value signal 209 indicating the average value of the period of the horizontal synchronizing signal obtained by integrating this count value 205, and the magnitude of this difference signal is predetermined. When the horizontal sync detection pulse 21 is output only when the value is smaller than the value of, the horizontal sync signal can be detected with high accuracy. In addition, it is guaranteed that the horizontal synchronization detection pulse 21 has the same accuracy in the above-mentioned period corresponding range.

Now, the horizontal synchronizing signal 21 detected with high accuracy as described above is supplied to the timing generating circuit 7. This causes the timing generator 7 to generate a very accurate digital sync timing pulse 22.

FIG. 6 shows a block diagram of the digital sync detection circuit 23 to which the digital sync timing pulse 22 is supplied, and FIG. 7 shows a concrete circuit block diagram thereof. The digital scrambled video signal 3 is guided to the comparison circuit 231 in the digital synchronization detection circuit 23, and the slice level 232 having a predetermined value.
(See FIG. 10 (b)) and is output as a 1-bit digital slice signal 233 (see FIG. 10 (d)).

The digital slice signal 233 is supplied to the gate signal generation circuit 234, and is guided to the NAND 2341 together with the digital sync timing pulse 22 as shown in FIG. As a result, the output 2342 of the first falling NAND 2341 of the digital synchronization signal 93
It is detected as the rising edge (see FIG. 10 (f)) and is supplied to the flip-flop 2343. The output 235 of the flip-flop 2343 is supplied to the address detection circuit 236. The digital synchronization reference signal 14 is supplied as a reset pulse 237 to the reset terminal of the flip-flop 2343 in a state delayed by one sampling period by the latch 2361 in the address detection circuit 236. Therefore, the output 235 of the flip-flop 2343
Contains only one pulse of the digital synchronization reference signal 14 (see FIG. 10 (g)). Therefore, if the logical product of the output 235 of the flip-flop 2343 and the digital synchronization reference signal 14 is obtained by AND 2362, the output is an absolute address.
It is the descramble reference signal 24 that gives the address. If the descrambling reference signal 24 and the phase of the horizontal writing counter 26 are matched, the address y of the descrambling point can be accurately matched.

FIG. 8 is a specific circuit example of the phase comparison circuit 25. If the descrambling reference signal 24 and the address signal 27 supplied from the horizontal writing counter 26 are in phase, the AND signal 251
Since the counter 252 is reset by the output of the above, the phase control signal 28 is not output. Conversely, the descrambling reference signal
When the 24 and the 24th address signal 27 supplied from the horizontal writing counter 26 are out of phase, the AND 253 counts the counter 252 with the phase of the descrambling reference signal 24.

When this phase shift continues 16 times, the output of AND 254, that is, the phase control signal 28 is output, and the horizontal write counter 26
Is aligned with the phase of the descramble reference signal 24. Since the continuity of the phase shift is determined by the counter 252 in this manner, it is prevented that the phase shift is erroneously determined due to a weak electric field or noise.

〔The invention's effect〕

As described above, according to the present invention, the horizontal sync detection circuit 20 detects the width and periodicity of the composite sync signal 19, so that the horizontal sync signal 21 can be detected very accurately. Since the digital sync detection circuit 23 operates based on the horizontal sync signal 21, the absolute address can be detected with high accuracy. In addition, since the phase comparison circuit 25 judges the continuity of the phase shift between the absolute address and the phase of the horizontal writing counter 26 which gives the division point for switching the video period, the phase of the horizontal writing counter 26 is pulled in, so that it is weak. Very precise and stable division points can be detected even with respect to electric fields and noise, and thus descrambling can be achieved with good performance.

Since these functions are all processed by digital signals, the circuit scale is very small.

As described above, according to the present invention, there is provided a decoding circuit which can carry out the address detection required when descrambling the in-line rotation system, which is one of the scrambling systems, with high accuracy and at a low cost because it is suitable for the digital IC. It is possible to provide a descrambler having the same.

[Brief description of drawings]

FIG. 1 is a circuit block diagram centering on a decoding circuit portion of a descrambler according to the present invention, FIG. 2 is a circuit block diagram of a horizontal synchronization detecting circuit according to the present invention, and FIGS.
FIG. 7 is a pulse waveform diagram for explaining the operation of the sync detection circuit, FIG. 6 is a block diagram of the digital sync detection circuit according to the present invention, and FIG. 7 is a gate signal generation circuit and address detection circuit according to the present invention. FIG. 8 is a specific circuit diagram of the phase comparator according to the present invention, and FIG. 9 is a schematic signal waveform diagram for explaining the in-line rotation system.
FIG. 10 is a signal waveform diagram for explaining the address detecting method in the present invention. 2 ... A / D converter, 3 ... Digital scrambled video signal, 4 ... Clock, 7 ... Timing generation circuit, 14 ... Digital sync reference signal, 18 ... Sync separation circuit, 19 ... Composite sync signal , 20 ... horizontal sync detection circuit, 21 ... horizontal sync signal, 22 ... digital sync timing pulse, 23 ... digital sync detection circuit, 24 ... descramble reference signal, 25 ... phase comparison circuit, 26 ... Horizontal write counter, 27 ... 24 address signal, 28 ... Phase control signal, 29 ... Horizontal read counter, 31 ... Read address, 34 ... Write address, 51 ... Divider circuit, 91 ... Video Signal, 93 …… Digital sync signal, 96 …… Scrambled video signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukinori Kudo 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Stock Company Toshiba Yokohama Metal Factory (72) Masaki Nakagawa 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Stock Association Company Toshiba Yokohama metal factory (72) Inventor Naoki Kawai 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Technology Research Institute of Japan Broadcasting Corporation (72) Inventor Takeshi Kimura 1-10-11 Kinuta, Setagaya-ku, Tokyo Broadcasting Technology Research Institute, Japan Broadcasting Corporation

Claims (2)

[Claims] 1. A pattern signal in which one horizontal period is equally divided, addresses are given to respective equal points, and the signals are divided at a predetermined address in the pattern period and the order is changed in this pattern period. An input end to which a scrambled video signal having a horizontal sync signal having an absolute reference address signal having a predetermined width and a period for detecting an absolute reference address serving as a reference for synchronously counting the addresses is input; A clock generation circuit for outputting a clock for sampling the scrambled video signal; an A / D conversion circuit for analog-digital converting the scrambled video signal and outputting a digital scrambled video signal sampled by the clock; Horizontal sync detection that outputs a horizontal sync detection signal when the horizontal sync signal is detected from a video signal Path, a timing generation circuit that outputs a digital synchronization timing signal for detecting the absolute reference address at a timing based on the horizontal synchronization detection signal, and a frequency dividing circuit that outputs a digital synchronization reference signal obtained by dividing the clock. And a digital sync detection circuit which is supplied with the digital scrambled video signal, the digital sync timing signal and the digital sync reference signal, and which extracts the digital sync reference signal corresponding to the absolute reference address and outputs it as a descramble reference signal. A memory that stores the digital scrambled video signal and outputs the digital scrambled video signal that has been re-swapped, an input end to which a read change signal corresponding to the predetermined address is input, and a phase control signal that controls the phase. , Writing in synchronization with the absolute reference address Address, a horizontal write counter, a horizontal read counter that outputs a read address according to the read change signal in synchronization with the horizontal write counter, and the digital scrambled video signal is written to the memory by the write address. Writing / reading means for reading from the memory by the reading / reading address, and a phase of the write address corresponding to the absolute reference address output from the horizontal write counter and the descrambling reference signal are compared, A phase comparison circuit for outputting the phase control signal for synchronizing the output of the horizontal write counter with the descrambling reference signal to the horizontal write counter when the shift occurs continuously a predetermined number of times. Descrambling device. 2. A synchronization detecting circuit, which outputs a digital slice signal obtained by slicing the digital scrambled video signal at a predetermined reference level and converting it into a pulse waveform, and gates the digital slice signal with the digital synchronization timing signal. A gate signal generation circuit for outputting a gate signal for detecting a digital synchronization reference signal corresponding to a predetermined absolute address in the digital synchronization reference signal, and the descrambling reference for gated the digital synchronization reference signal by the gate signal. The descrambling device according to claim 1, further comprising an address detection circuit that outputs a signal.