JPH0652507B2 - Microcomputer development equipment - Google Patents

Description

The present invention relates to a microcomputer developing apparatus, and more particularly to a microcomputer developing apparatus used for software development and the like.

[Conventional technology]

Nowadays, the functions required of microcomputers are complicated and diversified, and the program size tends to increase.

For this reason, it is becoming increasingly common to develop programs with the size of the address space limit of the target microcomputer. Therefore, the address space of the target microcomputer is often exceeded during program development. In such a case, it is often the case that logic debugging is performed for the time being, and after verification, the program size is reduced.

The conventional microcomputer development device is premised on the program development up to the address space of the target microcomputer.

Generally, in a microcomputer development device, a user memory may not be mounted in all address spaces of a target microcomputer at the time of system development. Therefore, an emulation memory and a user system which the development device has in this address space. It has a memory mapping function that can be arbitrarily allocated to the user memory included in, the guard memory that prohibits the operation of the emulator processor, and the like.

An example of a conventional microcomputer development apparatus having a mapping memory as a memory mapping function is shown in FIG.

In this microcomputer development device, first, the mapping memory 5 is set in advance by the supervisor processor 1.
In addition, mapping information indicating which memory of the user memory 7 and the emulation memory 8 can be accessed is written for each address corresponding to the entire address space of the target microcomputer. For example, "1000" to "1FFF" and "3000" to "3FFF" are allocated to the emulation memory by "1", and "2000" to "2FFF" are allocated to the user memory. Write "0" to indicate. The operation in this case is that the address selector 3 selects the address signal AD ₁ from the supervisor processor 1 by the address select signal S _AD , and each address of the mapping memory 5 according to the address signal AD ₁ and the output data DT ₁ of the supervisor processor 1. Mapping information is written in. At this time, the buffer circuit 4 is in the inactive state.

During the emulation operation, the address select signal S _AD
Address signal A from emulator processor 2
D ₂ is selected and the buffer circuit 4 becomes active. Therefore, the address signal A from the emulator processor 2
D ₂ is output to the mapping memory 5, the user memory 7 and the emulation memory 8 via the address selector 3 and the buffer circuit 4.

The previously written mapping information is output from the mapping memory 5, and the chip select signal end of the user memory 7 or the emulation memory 8 becomes active according to the memory select signal S _M. As a result, the emulation memory 8 accesses the addresses "1000" to "1FFF" and "3000" to "3FFF", and the user memory 7 accesses the addresses "2000" to "2FFF" according to the preset mapping information. It will be possible.

[Problems to be solved by the invention]

Since the conventional microcomputer development apparatus described above is configured to access the user memory 7 or the emulation memory 8 according to preset mapping information, this mapping information cannot be changed during emulation. The address space of the target microcomputer may be exceeded at the time of development. In this case, the operation of the emulator processor 2 is stopped once and the overloaded program is reloaded, or the program size is targeted. It is necessary to reduce the size to fit in the address space of the microcomputer and perform emulation again, which is cumbersome, time consuming, and cannot be emulated in a timely manner.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor development device capable of expanding an address space, facilitating emulation operation, reducing time, and enabling timely emulation.

[Means for solving problems]

A development device for a microcomputer of the present invention includes a user memory and an emulation memory that are accessible by a user memory select signal and an emulation memory select signal, respectively, and write and read a predetermined main program and data by sharing them with a predetermined address. Mapping information that defines the allocation of the user memory and the emulation memory for each address is stored in advance, and a mapping memory that outputs the mapping information of a corresponding address by an address signal and a switching signal is generated under a predetermined condition. A switching signal generator, which outputs an extended memory select signal when the switching signal is input, and which outputs the extended memory select signal when the switching signal is not input, in accordance with the mapping information from the mapping memory. A memory select circuit for outputting a Direct signal or emulation memory select signal, the composed expanded memory select signal by enabling access certain subprograms and data include an expansion memory to write and read with respect to a predetermined address.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The supervisor processor 1 outputs the address select signal S _AD and the address signal AD ₁ and inputs / outputs the data DT ₁ to control the system.

The emulator processor 2 outputs the address signal AD ₂ and the switching signal Sc at the time of interrupt processing and inputs / outputs the data DT ₂ to control emulation.

The address selector 3 selects and outputs either the address signal AD ₁ or AD _{2 according to} the address select signal S _AD .

The buffer circuit 4 temporarily holds the address signals AD ₁ and AD ₂ and the data DT ₁ and DT ₂ .

The mapping memory 5 uses the user memory 7 for each address according to the address signal AD ₁ from the address selector 3 and the data DT ₁ from the supervisor processor 1.
Also, mapping information that defines allocation to the emulation memory is stored in advance, and mapping information of a corresponding address is output according to the address signal from the address selector 3.

The memory select circuit 6 is composed of gate circuits G _{1 to} G ₃ , and when the switching signal Sc is input, it outputs an extended memory select signal CS ₃ equivalent to this switching signal Sc, and the switching signal Sc is not input. In this case, the user memory select signal ▲ ▼ ₁ or the emulation memory select signal C according to the mapping information from the mapping memory 5.
Output S ₂ .

The user memory 7 and the emulation memory 8 can be accessed by the user memory select signal CS ₁ and the emulation memory select signal CS ₂ , respectively, and a predetermined main program and data are assigned to a predetermined address for writing and reading, respectively. .

Extended memory 9, be accessible by the extended memory select signal CS _3, performs writing, reading a predetermined sub programs and data to a predetermined address.

Next, the operation of this embodiment will be described.

First, before emulation, the supervisor processor 1 writes mapping information for each address in the mapping memory 5 in the same manner as in the conventional example, and allocates each address area to the user memory 7 and the emulation memory 8.

On the other hand, the interrupt processing routine is written in the address of the expansion memory 9 corresponding to the predetermined address of the mapping memory 5. For example, when the addresses “1000” to “1FFF” are assigned to the emulation memory 8, the interrupt processing routine is written in the addresses “1000” to “1FFF” in the extension memory 9.

Next, the memory switching operation during emulation will be described. First, the address selector 3 selects the address signal AD ₂ from the emulator processor 2 by the address select signal S _AD , and the buffer circuit 4
Becomes active.

When the emulator processor 2 is not in the interrupt process, the switching signal Sc generated during the interrupt process is the inactive level "0", so the output of the memory select circuit 6, the user memory select signal ▲ ▼ ₁ and the emulation memory select signal CS ₂ is both a value written in advance in the mapping memory 5 is output as it is.
That is, “0” is output to the address assigned to the user memory 7, and “1” is output to the address assigned to the emulation memory 8.

Here, when the emulator processor 2 enters the interrupt process and the control is transferred to the interrupt process, the switching signal Sc becomes the active level "1". This allows the user memory select signal ▲
▼ ₁ becomes “1” and the emulation memory select signal CS ₂ becomes “0”. As a result, the user memory 7 and the emulation memory 8 are deselected and the extended memory 9 is selected and accessible. Then, the interrupt processing routine written in the extension memory 9 is accessed and the interrupt processing is performed. This state continues when the switching signal Sc is "1", that is, while the emulator processor 2 is in the process of interrupting.

Then, when the interrupt processing of the emulator processor 2 is completed and the switching signal Sc becomes “0”, the user memory select signal ▲ ▼ ₁ and the emulation memory select signal CS ₂ output the values previously written in the mapping memory 5 again. Then, the emulation state is as it was initially set.

In this way, the emulation memory 8 and the expansion memory 9 can be used in an overlapping manner for the addresses "1000" to "1FFF", and the address space can be expanded.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In this embodiment, when a jump instruction at a certain address of the emulator processor 1 is accessed to a jump table area preset in the user memory 7 or the emulation memory 8, a subroutine in the extension memory 9 is accessed, The switching signal generator 10 is provided so that the main program on the user memory 7 or the emulation memory 8 is accessed when the jump instruction is accessed.

For example, "1000" to "1FFF" on the emulation memory 8 and the extension memory 9 are used as the jump table area. Among them, the 1000th address of the emulation memory 8
“JMP3” is added to the 1003 address and the 1003 address of the expansion memory 9, respectively.
The instruction "000" is written in the address match detector 11 at address 1003 and the address match circuit 12 at address 1000 to generate address match detection signals.

When the address signal AD ₂ from the emulator processor ₂ reaches the address of address 1003 during emulation,
The output signal of the address coincidence detector 11 becomes an active level, the flip-flop 13 outputs the switching signal Sc ', and the address of address 3000 of the extension memory 9 in which the subroutine exists is accessed. Also emulator processor 2
When the address signal AD ₂ from the address becomes the address of 1000, the output signal of the address coincidence detector 12 becomes active level, and the address of 3000 of the emulation memory 8 in which the main routine exists is accessed.

In this way, since the address area of address 3000 can be used by overlapping the emulation memory 8 and the expansion memory 9, the address space can be expanded.

FIG. 3 shows a state in which the address spaces of the emulation memory 8 and the expansion memory 9 of these embodiments are allocated.

〔The invention's effect〕

As described above, according to the present invention, by providing the expansion memory that enables access to a predetermined address by a switching signal generated during interrupt processing or under a specific condition, the target microcomputer Even if the address space is exceeded, the address space can be expanded without the complicated operation of stopping the operation of the emulator processor or reloading the program, and the effect of shortening the emulation time can be achieved. is there.

[Brief description of drawings]

1 and 2 are block diagrams showing first and second embodiments of the present invention, respectively, and FIGS. 3 (a) and 3 (b) are respectively first diagrams.
FIG. 4 is a block diagram showing an example of a conventional microcomputer development apparatus, and FIG. 4 is an allocation diagram of the address space of the emulation memory and the extension memory of the second embodiment. 1 ... Supervisor processor, 2 ... Emulator processor, 3 ... Address selector, 4 ... Buffer circuit, 5 ... Mapping memory, 6 ... Memory select circuit, 7 ... User memory, 8 ... Emulation memory, 9 ...... Expansion memory, 10 ...... Switching signal generator, 1
1,12 ...... address match detector 13 ...... _flip-flop, G 1 ~G ₃ ...... gate circuit.

Claims (1)

[Claims] 1. A user memory and an emulation memory which are accessible by a user memory select signal and an emulation memory select signal, respectively, and write and read a predetermined main program and data to and from a predetermined address, respectively, and the above-mentioned for each address. A mapping memory that stores in advance mapping information that defines the allocation of the user memory and the emulation memory, and outputs the mapping information of a corresponding address according to an address signal, and a switching signal generation unit that generates a switching signal under a predetermined condition. When the switching signal is input, the extended memory select signal is output, and when the switching signal is not input, the user memory select signal or the emulation is performed according to the mapping information from the mapping memory. Development of a microcomputer including a memory select circuit for outputting a memory select signal, and an extended memory accessible by the extended memory select signal for writing and reading a predetermined subprogram and data at a predetermined address apparatus.