JPH06509917A - Standardizable self-route assignment non-blocking message exchange and route assignment network - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Standardizable self-route assignment)/Blocking message exchange and route assignment failure twerk The present invention provides a method for determining which one of the plurality of input terminals r to which one of the plurality of output terminals r Allocate routes for messages to one destination in an efficient and cost-effective manner Concerning self-routed non-blocking exchange/stem.

Background of the invention As data transfer increases in complexity, to a location or from one area of one computing device to another. The number of messages is increasing. Therefore, there are many manual terminals. Route a message from any one output terminal to any one specific one of a number of output terminals. Any stem/stem or its subsumbones that can facilitate the It is essential. The invention described herein provides fast route allocation for such message messages. (make it nJ-capable with little overhead.

The present invention employs a return network and allows different types of switching networks to be used. switch can be used and works well in broadcast communication mode. s network or by relying on multiple buses and control devices. Reduces the number of required switches, 11 self-routes use the 1-to-1 algorithm Eliminates the need for pre-processing overlays in order to

Self-route algorithms route messages to desired locations at the switch level. uses information contained in the message itself to assign routes.

+990 1EEE (Volume 78 No. 1) Tobagi Nyoru FastP acket 5w1tch Architectures for Br.

ad-Band Integrated 5 services DigitalN Traditional self-route allocation algorithms such as those described in et-WorksJ Rhythm does not dictate how those algorithms can actually work and how the algorithm works when using a ClO3 type network. It doesn't explain how you can go to heaven.

For large networks, to realize the NXN message exchange system The C1os network reduces the number of switches required for Park is preferred. For example, the CLOOS net issued to payne U.S. Pat. No. 4,696, which refers to work and relocatable networks. See No. ゜000.

The invention described herein simplifies all of these concepts.

The switch uses a standard crossbar network, Cl0s network, tailored to the compact implementation. network or a variant of the ETAS network that uses multiple buses. The rule is determined by the fCrt of the switch and the type of switch used. The type of -1411 will also change depending on the implementation form. explained in detailed description As stated above, the preferred implementation is to employs a return network for all blocking messages that are message back to the source, ie, the sending node. Route allocation system Due to the nature of the body and the configuration of the exchange network, it is necessary to explain from the human node to the output node. There is no overhead or up-front cost to route messages through the Almost no processing is required.

Brief description of the drawing FIG. 1 is a two-dimensional layout of switches in an NXN crossbar.

Figure 2 shows the block diagram of the trap network to remove the access hc1 conflict. FIG.

FIG. 3 is a layout of a second implementation of the nXm crossbar.

Figure 4 shows the layout of an nXm crossbar with associated return circuitry. 58 is a schematic diagram of a 2×2 crossbar switch.

FIG. 5b is a diagram of a gate level implementation of the switch described in FIG. 5a.

Figure 6a (i), (ii) and (1st item) are 2x2 broadcast notifications (, 3 of 1 switch). There are two possible modes of operation.

FIG. 68 is a diagram of a gate-level implementation of a broadcast switch.

FIG. 7 is an electronic level diagram of one implementation of a crossbar switch.

FIG. 8 is a diagram of a 36x36Clos network.

FIG. 9 is a diagram of a 16XI6clos network.

Figure 10 shows a non-blocking n rXn rffl self-run with return network. -) This is the layout of the assigned C1os network.

[111a, b and C are the input terminals and output terminals of the crossbar used in FIG. It is a line diagram of a terminal.

FIG. 12 is a schematic diagram of a truly non-blocking bus implementation according to the present invention. .

FIG. 13 shows a finite shape of a vine bus control device for use with the invention as described in FIG. Status 1! FIG. 11 is a block 11 diagram of the machine model.

FIG. 14 shows a 2n-1 diagram for use with inventions such as those described with reference to FIG. Data bus control employed in one of the data bus controller blocks 1 is a detailed schematic diagram of a device block; FIG.

Figure 15 is a diagram of a complete 4x4 crossbar with associated return network. .

The present invention has a plurality of stages, and at least the first stage and the last stage are called "units". A message transmission system consisting of multiple crossbars called teaches a truly non-blocking switching network for use in first Each crossbar in the stage has a header with a source address and a destination address; Exchange messages with one associated turn signal tIR means for each can do. The crossbar has a plurality of manual terminals n and a plurality of output terminals m. and the m human input terminals are logical strings labeled I-m and 1 to n, respectively, The switches are connected by an nXm array of 2x2 switches organized into logical rows. The switch is connected between the n input sources and the output terminal of mgJ. Sui The switch first determines that the source address of the message is the column address of the switch. Second, the turn signal must match the preceding switch with the matching column address. Based on the sign of the two events that it has not already been reset by the Set to bus mode or exchange mode.

Each crossbar 1 at the final stage, that is, a "unit" has m crossbars at the final stage. Each of the first stages has a human input gtJ4r and n output terminals. It has a size and organization similar to a crossbar. Each stage is the first stage and the last stage. Enter some number r, which is the number of crossbars. Each crossbar of the first stage The m output terminals of - are connected to the final stage crossbar via one or more intermediate stages. Routes are assigned to m manual terminals. For each output terminal of the first stage, the first For messages sent to subsequent stages via the output terminals of a stage, the return path There is.

Various things related to 9 base 7 stems and electronic base systems. We will explain the return route in various forms. In addition, during the bus space we remove a large number of switches I will also explain the interludes.

Detailed description of the invention Here, we will perform local control of a 2x2 switch composed of various networks. Both of them are based on the idea that it is okay to adopt a self-route allocation algorithm to I've included a few w-matches that I keep in mind. When executing this, the input terminal f − and all output terminals, and the connections between those terminals. is not unnecessary. When using a median loss bar, N input, M output net A total of NM 2×2 switches would be required for the workpiece. Sui The function of the switch is relatively mediocre, and the design layout is very conventional. , so even if such a network were realized electronically, , even when realized optically, it can be easily manufactured. C1os type truly non-blocking Even the number of switches can be reduced considerably by using a switching network. Using the 0-bus design reduces the number of required switches even further. It is possible to do that. This cost savings is due to the ability to scale the inventive concepts described here. To direct power.

For example, a 36X36 network that uses a straight loss bar design Then 1296 2x2 switches would be required. C1os network Using this design, only 1188 switches would be required.

When moving to a 128x128 design, there are 16,384 switches. However, in the case of the C1os design, the necessary There are probably only 9936 switches.

An additional important part of this series of inventions is the use of a return network. return The network is about to be routed to an already occupied output terminal Works to return messages. This re-route assignment, i.e. the re-route assignment This is automatic, especially in large networks, when messages are passed through It takes less than the timeout to notify the sending mate that you are not present. do not have. (Timeout is a counter that waits some increment longer than the maximum delay. is a timer and detects that time has elapsed or that the counter is full. When this happens, a new action begins. ) Before making this explanation, we should first define some terms.

The first definition is ``to become a truly non-blocking network (TNB).'' cormorant. A truly non-blocking network allows any message to pass through. such that no rearrangement of existing conditions is required. To do so, see below. A set of features is required, including: (1) Configuring appropriate network switches for all required connections; (11) Guarantee that conflicts do not occur (multiple input terminals have the same output Conflicts occur when connecting to power terminals), (iii) Conflicts If , only one connection is fulfilled while other requests are kept waiting? (1v) In the case of a broadcast communication network, the control equipment shall be notified. It shall also be possible to connect a single source to multiple output terminals depending on the location. stomach.

The inventive concept described in this application is that the TNB uses distributed local route allocation. How can practical implementations be configured for fast, wide-bandwidth applications? Show what you can do. (Although the inventive concept is primarily oriented toward electrical exchange, Using optical interchange offers additional benefits, such as not requiring separate lines for Obtainable. ) Generally, a crossbar switch has a set of input terminals of equal number or rectangular shape. is a two-dimensional array of squares or rectangles that persists in an unequal number of output terminals. I can think. Therefore, for N input terminals and M output terminals, The crossbar has NM intersections, and the combination of input terminals and output terminals is 1:l. Connections can be formed simultaneously using a non-blocking method. Actually, that Besides using an array of switches, each switch representing an intersection methods are also being used. These methods include, e.g. , a bus ordering algorithm used to simplify the secondary complexity of switches and controls. The optical configuration uses a cross-product matrix multiplication architecture. I am using it. The first method presented here is a switch-level It uses design.

TNBs that require fewer switches than required by the crossbar may initially , rA 5tud! by C1oS! / of Non-Blocking Sw itChing NetworksJ (Bell System Techn. ical Journal, 32+, published in 1953, pages 406-424) proposed inside. A typical C1os network (CN) is an odd-numbered network, e.g. The total size of the desired NXN is Constructed as a modular design employing multiple crossbars that are significantly smaller than the has been done. In other words, the switches that are likely to be needed in the C1os network. When the crossbar of equivalent size is NXN, the number of crossbars is N×~l’N. There will be.

(See previous section.) Also, from a three-stage network, place the center stage with another three-stage CN. By switching, a network with three installations can be configured.

In the NXN C1os network, when rn=N, the human power stage is nXm If the second stage is composed of one crossbar with a size of m+rX The third stage is composed of r crossbars, and the third stage is r + m x n crossbars. It is known that it is composed of Sequence the size of one crossbar ( n+m+r). If m≧2n-1, C1os The network is truly horn blocking. CN is true if m<2n-1 Although it is not a non-pro 1 king, it may be possible to relocate it to non-blocking.

Interrupt messages to relocate your network when you need output devices. σf placement in horn blocking, in that it may be required to cut It is particularly undesirable to make the network possible. Therefore, long duration or For applications that require long messages, interruptions are highly undesirable. Not good.

Reference is first made to FIG. 1, where a simple loss bar network (10) is shown.

The network has input terminals l to n and output terminals l to m as shown. , 2X2 switches each at multiple points in one matrix, i.e. 1 ．． It may be labeled as 1 to n1m. Switch as described below The column address is what is compared to the message ladder, so set the switch to may be labeled only by column address.

Figure 8 shows the C1os net associated with a 36x36 array from input terminal to output terminal. Show the work. This network consists of six 6X11 crossbars in column l and 11 6x6 crossbars in row 2 and 6 more 11x6 crossbars in row 3. It consists of a crossbar. Therefore, the input of the signal line 81 is a switch, That is, the first upper signal line of the crossbar 84 in column 2, row l leads to the intersection 82. 83 and again lead to the output terminal 86 of the same crossbar by switch 85. Is that the input end of crossbar 88? -87 is considered to be connected. At this point, enter The power is cross-switched by one of the six switches on the crossbar 88 of that column. It only needs to be routed to one of the six output terminals of bar 88. here, When transferring a message from input terminal 81 to one of the output terminals of crossbar 88 The reader will see that three intersections are associated with it.

Also, a CI o s network is usually a row of the square root of N (labeled Although there is no central crossbar, it is configured to have m rows of central crossbars) x 3 columns. Also note that there are. Divide the central part into three parts according to the teachings of C1os This allows you to expand your network and further reduce the number of switches.

Next, according to Design 20, resolve conflicts before connection request conflicts occur. Refer to FIG. 2, which uses a trap network method for removal. this design is avoided by the present invention. In Figure 2, inputs 1 to n are connected to a parallel classification network. 21 and to a comparator stage 22 for classification. Comparator stage 22 to the replication router stage 23 along with each message to be passed.

The replication router stage 23 routes the message to the signal line 24 before reaching the classification network a. is returned to the input terminal via 25 and the message is routed according to which method is desired. It will be processed accordingly. For example, return the message header itself to the input node. and then route the message header and message to a buffer, or for messages that may require retransmission at some other point. Another consideration of the number of children may be desired. Therefore, the crossbar 27 Each message that has been routed through a switch is routed through a switch. The switch is set according to the command that specifies the output address. explained here Using the teachings of Such an implementation is unnecessary.

switch Before moving on to the description of the algorithm for self-route assignment, let us introduce a space that can be used with this device. Please provide a description of the switch or at least its functionality here (you can refer to them later). This is because the explanation would be more or less complicated.

Although the invention is well suited to optical switches, only an electronic version is shown. but , the optical switch is flexible, and what route is taken for the return signal after it is determined. It should be obvious to those skilled in the art that it is also possible to pass Hikari Sui Connecting devices allow you to enjoy faster communications, greater bandwidth, and more. Became iJ Noh. Also, do not require a message to obtain a return route assignment. Therefore, even the return network described here can be avoided using optical switches. It would be Kiro.

In Figure 58, a basic 2x2 switch 50 has two input terminals IN+ and IN2. , it can be seen that it has two output terminals OUT+ and 0UT2. The switch is , typically can be set to bus mode or exchange mote. Under pass mode, the The r-j lines 51 and 52 are closed, and the signal lines 53 and 54 are opened. with exchange mote is the opposite.

FIG. 5b shows the switch 50 in the form of a logic diagram. At input 55 "Change" controls whether the sweet tip is in pass mode or exchange mode. Ru. Therefore, when the human power for 55 is O, OUTl is open to INI. OUT2 is closed to IN2, OUT2 is open to IN2, and IN2 is closed to IN2. It is closed to I. When 55 is 1, the opposite is true. 0tJT I is open to IN2, and 0UT2 is open to INI.

Referring now to FIG. 68, three operating modes i of logical connections for a broadcast communication switch.

11 and 111 are shown. In mode 1, one input is connected to both output terminals. It seems to connect. In mode 11, the human power terminal is connected to the output terminal in the straight direction. Continue. In mode 111, the input terminals connect to the output terminals in the cross direction.

A gate-level implementation of such a switch is shown in FIG. 6b.

That is, if the input 66 is O and the human power 65 is high (i.e., NJ), Then, the output of a' becomes b instead of a, and the output of b' becomes a instead of b, so This is a switching condition. Input 66 is 01 or low, and output 65 is also low. In some cases, a broadcast bus condition occurs in which both outputs are b.

Similarly, if human power 66 is high and H output 65 is low, input b goes to a'. Then, the human input signal also passes to the output terminal b'. Both 66 and 65 are high , the output of a' becomes b and the output of b' becomes b, so one more A broadcast communication article f'1 appears.

If desired, the switch may be redesigned to eliminate the circular message clause ('I). stomach. The same can be said for the gate-level realization form of the switch explained earlier. Therefore, this switch may be configured in other ways, as is well known to those skilled in the art. .

When setting the switch or not setting it, or when setting the switch The invention requires reference to the intended address of the message. seek Accordingly, the device 70 described with reference to FIG. 7 includes a 2×2 switch SW. A similar device is required. Crossbar switch installed! 17o is the address Human data including data is received via data lines 71 and 72. Into a holistic form of realization Therefore, either series or parallel manpower may be desired. In any case, the data will Delay buffers 73a and 73b are provided before reaching the switch SW. message The address label part of is read into the address comparator 74 connected to the signal line 75. ratio The signal output from the comparator 74 to the signal line 75 is such that the switch address is the destination address. positive if it matches the appropriate part of the The positive signal on such signal line 75 is Latch the toggle door 8. In this way, the AND gate 78 connects to the signal line 76. or reset by a signal from signal 177. Then, the control output supplies the human power C to the switch SW. The C signal further includes 77a The output of is changed from "turn" to "/-turn" by the AND gate 78 in the latched state. change to Therefore, all subsequent switches receive the changed turn signal. to continue the message along the column. Various different schemes for this switch are readily within the skill of those skilled in the art. It could be developed. This particular design is based on the network and algorithm described. Although the system is preferred, variations will be apparent to those skilled in the art. For example, here It would be possible to remove signal line 76 without destroying the functionality described. to hope Depending on the situation, there may be parallel input paths. Departing from the invention described in the claims Many other variations could be constructed without departing from this.

Basic self-route assignment algorithm See Figure 1. All switches are initially configured to either pass or switch . When you start making any connections, all switches are in one mode or the other. should be set to . In the preferred embodiment, the default setting is exchange. (rare If desired, reverse all initial IgI settings and make appropriate adjustments to accommodate the reverse order. You will be able to perform the adjustment. Such adjustments are primarily made by It will invert the input line. The switch itself requires a redesign. be exposed. ) When a message reaches any switch, the header containing the destination address is The route is assigned along the line corresponding to the source that sent the message. follow In other words, if a message is sent manually from node l, the message is along the switches (L I), (1, 2), (1, 3), ... 11 (+, m) The routes are assigned accordingly. Accompanying the message, for convenience of explanation, here There is a separate activity signal called "turn". The label on the switch, the message ,; the destination address in the message's destination at each switch reached. Compare with Toshi・Mata. If they are the same and the 11 turn signal is high, then The switch is set to pass mode, for example, and the turn signal is reset by the switch. (See Figure 7). Destination label (title ml) matches the switch address If not, or if the turn signal is low, the switch is in the initial mode (preferred mode). In the preferred embodiment, it remains in case exchange mode). That is, from node 1 If the message should be transferred to power node 3, switch 1, 1 connects it to line a'. Along with this, I was told to replace the switch with switch 1.2. The turn signal is along this line It continues to advance, so it has not been reset (II). Because no match is occurring , the switch remains in the exchange state.

When connected to switches 1 and 2, the message heading is again compared to the switch address. compared. Discrepancy found again and turn signal not reset as well Then the message is exchanged again along line a'2 to switch 1.3. Metsuse When the page reaches switches 1 and 3, the turn signal is reset. address is When a control signal is supplied to the switch SW (see Figure 7) due to a match, the switch The digit changes to a path, and the message header and subsequent message are input to input line a'2. The signal is then transferred to the output line b'3 of switches 1 and 3. The same control signal C is a turn signal Reset it vice versa.

When a message is complete, the entire network is set to a given message sizing. Resetting turn signals, including resetting them all at once at control intervals determined based on There are several ways to do this. However, the inventive concepts presented here are numerous. It works through a global or path message reset technique and will not be discussed in detail here. I won't reveal it.

Next, a network 30 with almost the same layout as the network in Fig. Please refer to FIG. 3 which shows. The difference is that each human-powered node can simultaneously In comparison, each human-powered node has its The message is broadcast across all rows of switches. those bulletins The transmission lines are designated as VA routes 31-34.

return network An important concept to eliminate the need for conflict resolution devices is That is, a return network is provided for each input line. Simplified implementation is a diagram showing a crossbar network 40 and an associated return network 41. This will be explained with reference to 4. For each node 42 or input line, an output terminal and An input line is provided. Changes are also required in the header. conflict To route the found message back to its source, enter the destination address and source address. both are required. Each should also have an independent turn signal . Go to 2. The first part of the goo should contain the destination address in the preferred embodiment. be. That is, for a message from node 1, it is among the outputs of 1 to m. This is rlJ. If everything is going properly, the header should look like we described above. Find the appropriate output terminal by yourself. However, if the destination output line is already in use, If so, the goo switches to the return network 41. For example, using input line 1 The human power node 42 that uses the human power line 2 and the second human power node that uses the human power line 2 are output nodes. requested a connection to node 3 (therefore, sending the message with the header to node 3 ) Consider a case. For example, the ladder from the second 7-de and the node 42 If two of the headers from the second node are clocked out at the same time, the The header from node 42 reaches switches 2 and 3 before the header from node 42 does. Therefore , switch 2.3 (in the preferred embodiment) by the header from the second node is set to pass mode and therefore the header from node 42 (input IiI+) When it reaches node 2.3, it connects to the return network 41 via switch 2+n. Herut? I+1 won.

When switching back, the switch in the network will have the source address part of the heading and its associated Look only at the turf signal. The source sent the message request, so the source In this case, it should be in use when receiving a request coming back via line 44. It's not possible. In order to get there, the message is from Switch T to Swift S. I'm going through the process. Route assignment through switches in the return network is Regarding sending addresses that are only reset when the address matches the original address. A separate turn signal (exactly the same as in the forward network) However, the turf signal is then transmitted by the rudder to its mate. along one of the long horizontal tracks of the crossbar (if any) along with the sage. Reset it through the switch on the return switch wire (light angle wire) until it returns to the first (See Figure 15). (Turnoy, No. 1 goes to the crossbar on the next step. If the route is being routed back, the turn signal will be processed on a lower stage. It must change again before it can change. ) 4x47 rays of complete switch 150 and associated return network. Please refer to FIG. 15 (or FIG. 4). Node 2 sends message M. If at the same time node l sends a message M, then in this diagram M and By following the labels of M, both the crossbar and the return network 151 The route assignments passing through can be tracked. (In addition, on the right side of the broken line 153, If you use a different turn signal method than that described in the preferred embodiment, switch The switch may be permanently shorted. ) (Also, the crossbar passes the crossbar of the subsequent stage.) There is no need to return the output from line 1 unless a message is received back from the loss bar. Therefore, the return network and the return network from the topmost switch in the crossbar It is also possible to exclude the connection of the lower right corner of the workpiece to the switch. ,) Clos implementation form This self-route assignment algorithm uses rnxm crosses in the first stage and the third stage. bar, and the second stage includes rn=N+mrxr crossbars. It may be applied to a NXN C1os network. Also, TNB is an issue. Therefore, m≧2n-1.

Traditionally, the problem of self-route crossbar networks is solved in a distributed manner. , 10 requests, routed to addresses at different crossbars in the third stage. Replacement of requests, such as requests assigned (to route messages), is Routes are assigned from crossbars with different power stages. For example, the work of Lin et al.

o-Dimensional 0ptical C1os Interconn ection Network and Its UsesJ(AI) plie dOptics, Vol. 27, No. 9, May 1, 1988, +731-1741 (page). However, this method replaces or redistributes all n requests at the same time. This is not possible with the self-route allocation distribution scheme used by the present invention. Can not.

The self-route assignment method described above works well for crossbars, but C1 unsuitable for OS networks. Nonproz regarding C1os network An important inventive aspect of performing Kinobu self-route allocation is the Selecting the crossbar to use when routing requests through the second stage It's there. Therefore, in the first n shared crossbars of the second stage crossbars, When conflicts are detected, these messages are sent to the remaining n− Routes are reassigned using one crossbar.

A “greedy” self for multistage or C1os networks Route assignment algorithm Next, we introduce a crossbar similar to the network shown in Figure 8, but smaller. - See Figure 9, which shows the network. Each input l1C1 has one address , +6XI6Clos network, the address is 2 It is from oooo to 1111 (however, in decimal notation it is from 1 to 1 as shown in the figure). 6). The destination addresses in column C3 have the same indication and C3 also has the same number of clocks. It consists of a suba switch. According to the requirements of C1os network , C2 has a larger number of smaller crossbar switches. (column C1 and and C3 crossbars have a size of nX2n-1). Regarding preferred embodiments For convenience, the number of crossbar switches in CI and C3 is not a power of 2. (so r is not a power of 2), then you should increase the number until you reach a power of 2. be.

Therefore, for the preferred embodiment, in the case of 4 digits, the number of bits and the number of bits per address are It can be seen that Bell is l log, r l.

Also, in the preferred embodiment, the switch is considered unlatched, so , all switches are in the bus position.

When any message arrives at any switch, the first column A header containing the destination address according to the self-route assignment algorithm described in Assign the route. The destination address consists of llog2r l bits. log of the lossbar address and the local destination address inside each crossbar It consists of two parts: 2n l bits. This alignment is the first l log, r is performed only for l bits.

To the message! Go to the desired address in the first of the intermediate switches in column C2. (flog, r　l　, for example, 00-1) The output terminal is in use. When you issue the message, the path to the desired column C3 crossbar switch will be established. The route is assigned to the next intermediate switch until the route is obtained. Therefore, the route assignment The algorithm is greedy in the sense that it can use any unused column for (prime number). In the example shown in FIG. 9, address oo-1 is vacant; The connection made to the second stage crossbar at 91 is C2. This crossbar Another message is coming in via 92 requesting -. they illustrate If they are heading to different final crossbars via tracks 93 and 94 as shown in No problem, but if not, the second passing message should be Pro 1 King and its This must be re-routed. This is greedy algorithm (algorithm) ) was created.

The key to resolving conflicts at each stage is conflict detection and The solution is the use of a crossbar with a return network. Danju and Dan 3 Conflicting requests are true input request conflicts (two input requests with the same output). (specifying the source address), the source node is returned to the source node. However, the first The second stage, i.e. the second column, caused by the sharing of crossbars in the second stage. Detect conflicts with their labeled crossbars and then, when the return header is received, the usage in the remaining crossbar of the second column is Solved by scanning possible connections. So, in the worst case, the request is Before reaching the (2n-1)th output terminal f-, the stage 1, that is, the CI cross The output end r of n@ of the bar will be scanned.

In other words, there are two possible forms of IO funflict. The first one occurs due to direct personnel conflicts in the first or third stage. this is , 2 or more "-manpower is the same output address of the third stage or subaddress of the first stage This is considered to be a case where a request is made. They are as explained in the single crossbar case. This is handled by conflict resolution. The second type of conflict is the middle row. caused by the sharing of crossbars in the request to scan the n-1 unused crossbars.

Due to their multi-stage conflict, the second stage, i.e. the middle stage, and the third stage The crossbar 20 in the column indicates that when a portion of the message is sent, Sends response back to source to confirm route assignment route is available A return path must be created so that the In this way, multiple A multi-tier network behaves more like a router than a pure interconnection network. do.

Figure 1 depicts such a system including a return network and an extra return path. See 0.

Similarly, when using an optical switch, light must pass through to reach the destination node. You can go in the opposite direction via the same opening switch you used before, so you can take the return route. You can also remove it. In addition, the return route will be opened at the same location as the sending route. Electronic switches can also eliminate the need for a return network or separate return path system. It should be noted that

The crossbar 18 to ra constitutes the first stage, and Ib to 2n-1b constitutes the second stage. is established, and the third stage is established from IC to rc. Refer to FIG. 15, respectively. A return network similar to the one described in detail! It has 02. crossbar For each connection such as line +03 between, there is a return line such as l03r. Figure 15 and see the line +03r there to n river.

For ease of explanation, the network includes a first stage, such as 150 in FIG. Assume that a 4x4 crossbar is provided. Output terminal 1 is the second stage It reaches the crossbar of i, reaches the second crossbar at the output terminal, and so on. Ru. The track returning from the first crossbar of the second stage becomes track +03r, The track returning from the second crossbar becomes track 104r, and the third crossbar of the second stage The track returning from the subbar becomes the return track 105r, which connects to the fourth crossbar of the second stage. Their return line will be 106r.

Considering the two-metuseno state of the crossbar 150 explained earlier, two Is the page M and M the output end? -3, message M2's This means that the goal has been reached. M is returned. M, is the third crossbar of the second stage Assume that it was not reached via . Therefore, M returns via line 105r. will be done. Switch 3 in the first row is still held in bus mode. and non-work messages pass through it to return network l-route assignments. be done. The return network returns the message to node 2. (All switches are , once the message has changed from the initial state, if the message blocks at the final stage It should be held in that state for the maximum delay required to return to . )So Here, M, passes through the second row and returns to the network via the fourth column switch. The route is assigned and the return network uses the return address to send the header to the node. 2. In the following explanation, the destination address is set in an incremental manner. and resend the header.

Figure 1189 Figures 11b and 1c show the crossbars used in each of the MIO crossbars. The number of lines to be constructed is shown in detail.

The remaining details are used in the next or subsequent second stage when the original selection is thwarted. The problem is how to scan the crossbar. The message is from When you return to the node, simply increment the destination address in the heading and reset the header. then try the next switch in the second stage. However, that increment is Executed only for the first part of the address. Therefore, for example (see Figure 9) (assuming that the circuit has a return network a), the output node is Receive address 000 and send a message to the receiving node at oooo. If you want The next attempt will be made via line 01 of crossbar 95.

This causes the header to appear on C2, where the switch is looking at the second part of the destination address. Since the message is sent to the second crossbar (not shown), it will be sent to the correct stage 3. In other words, crossbar 1 of C3 In this case, route v1 is applied to crossbar 96. Ru. If we try the third crossbar in stage 3, the second part of the destination address changes. Therefore, if the output address is oooo, the message will still be sent. Then, the route X hits the crossbar 96.

Using the bus Alternative to C1os net 7-ri with an intermediate stage or set of stages consisting of a crossbar It is possible to use the bus to route messages. this Embodiments further reduce the number of switches, but the patent version features a bus controller. The complexity increases.

The same 1 has a crossbar from 1 to r, and has a return screw for both the first stage and the third stage. j＋　) Network that involves work! 12, which shows 20. UyJIO As in the case of , the return line is different from the output terminal as explained with reference to Figure 15. Although it is located on the opposite side, it is mounted near the transmission line. This figure and Figure 1 The difference with 0 is 2n-1 control bags [11211 to 1212. ,−, is here That is. Each control i! One set of bus control bags ffi+21. ．． ~1 21.

However, the algorithm does not operate on the type shown in Figure 10 for this structure. It works almost the same way. Therefore, node 1 of crossbar 123 sends The signal or message sent to the data bus control bag [+1121 Connects to 1°. The message is output from 1 to 2n-1 output terminals of the crossbar 124. Assuming you are heading towards one of the buses, the message will be on the tracks inside that one set of buses. Try 1. The “in use” signal set by the V output of the bus 1 on track a. If no signal is present, the message enters the bus line at output terminal W. Those■ The output terminals of and W are bidirectional (i.e., pair input and output terminals as desired) power terminals, therefore may be 2v and 2w).

If this bus line is in use, the message is returned to node 1, incremented, and It is retransmitted to the next control 1 device via path 2 (not shown). Next control device 112 +2 (not shown, but connected in series next) is connected to the crossbar in the same way. 124 of that first data/bus controller line l that connects to . This means that line 2n-1 of crossbar 1231 is tried and the data bus controller Place! 1121712. and its line 1 continues until the attempted connection is attempted. It is thought that If still not successful, try resetting the header in the next increment. The cycle can be restarted by trying the line l. Cancel the message or This concept involves sending the signal backwards past the input node for later retransmission. Suggestive modifications will be apparent to those skilled in the art without departing from the scope of the invention.

(Also, in the figure, there is a single person output line between the bus and the crossbar 124r, It should be noted that there is a pair of input and output lines between the crossbar 124. be. You can use any method to do this, but all the clocks in one stage This is to indicate that it is considered preferable for the bus to connect to the bus in the same way. be).

Next, for completeness, the data/bus controller will be described. First, Control device! II see FIG. 14 showing +40. This is essentially 12 in Figure 12. FIG. 2 is an exploded view of a box labeled 1°. However, this diagram , the first stage crossbar and each of their return networks. (but also shows variations of the embodiment, such as using a demultiplexer) . Input data coming in via line 141 sees the first part of the destination address. The request is demultiplexed by one of the bus controllers, e.g. is sent to the control bag ffi+. Therefore, the bus control device 1 converts the message into data. occupies data bus 1 in order to send data via the data line to data bus l. Must be. To do this, the device first checks that data bus 1 is in use. However, in order to determine whether it is a sake cup, the state of the bus state l is checked. This is the line of state l It is carried out on the road. If data bus 1 is not in use, bus controller II Set/Reset III to a high signal or other suitable signal to the bus 1 state line. to be applied.

If the status is in use, the bus controller l has a wired OR connection to line 142. reroute the request from the response line. Messages return via network This return message is tagged with a turn signal to help you find your way back. . As explained in the previous implementation, the intermediate level, i.e. the second stage cross Such a turn signal for the return coming from the bar means that each track is connected to the return network. This was unnecessary because the appropriate address was reached.

FSM of bus controller 1. Person jJ: Parallel human power data/hetsugu bus, bus status (0/I), and next stage response Answer (Next Stage Re5ponse), single data equal to bus width packet, usually a helag bit, and the source address returned from the next stage. destination address. Human data/header is always routed) and two reserved bits for allocation. Including cuts.

2, il: data bus, parallel output header/data to next stage, corresponding to bus status line Return response (Response B) containing 1 bit ack) line (available or unavailable) and next stage response (Next Stage- source/destination information that may be obtained from the response.

Note that the bus line has three states (low, high, and high level) to distinguish between no signal and O value signal. It should be noted that the

3. State transition: IF Input Data/Header bit = On/'First bit indicates a header or message packet'/ ^ND Busjtatus = I/' bus is occupied, i.e. in use l/TH EN Re5ponse-Back = 0! Input Data/Head er:/'Send not-available signal in response' /LSE Responses (Back = I! Input Data/Header near '1/Busjtatus that responds and sends an available signal = I/' bus status 1/ELSE IF Input Dat to set the state in use and reserve the bus line a/Header bit = 10/” after the source receives an available signal Received message packet'/Data Bus = Input Data /Header/'Output bus = Input bus - Data transmission 1/ IF Input Data/) leader bit = II/’Message Special code for ending the bus '/THEN Bus,, 5tatus = 0/' Release the bus l/Data-Bus = XXXμ bus in high impedance state This implementation when allocating routes through the 1st/2nd stage back to the source node Note that we assume that the code operates in two modes. First, source The request header packet is sent out by the request header packet. The response received from the router is negative. If so, resend the headers until a connection is established. Second, if a positive response is received In this case, the north node connects all latching switches in the crossbar or The message is sent in packet form until the bus is freed.

Delay by route Bus space Self-route assignment Set route assignment route in C1os network. Only the average delay at startup is considered. Flatness in the first and third stages As before, the uniform delay is (n+1) for the xl realization, and for the x2 realization Regarding the state, it is n/2. The second stage delay is not so simple. day Resolving conflicts using data/bus controller architectures Consider delays. As can be seen from Figure 14, determining the availability of a connection is 1A. (Access time) = (log, r+k), where 10g2r is the is the multiplexer delay and k is the delay in the bus control and response logic FSM. This is a constant due to the timing delay. In the worst case, all n unused blocks in the second stage If the loss bar is scanned, this delay tA is repeated at most zero times. subordinate Therefore, in this implementation mode, the worst case scenario when setting up routes for route assignment is The delay in this case is 0(2n+nlog,r). Set up routes for route assignments Once the exchange has been completed, there is no need to resolve the conflict any further, reducing the exchange delay. is smaller. Since the optimal value of r = n = ~/''i near, the route for route assignment is The worst case delay when setting up is O(~侃(2+log,~’W>> (only O(~M) in case of normal route allocation delay). switch vergilo It is assumed that the optical system will have less delay than the electronic system when realizing .

8 direction Fig, 7 Fig, 2 Fig, 7 Copy and translation of written amendment) Submission (Article 184-8 of the Patent Law) 1. Viewing patent applications No. PCT/US92106651 2. Name of the invention Standardizable self-route non-blocking message exchange and route-assignment network twerk 3. Patent applicant Address: Honeywell, Minneapolis, Minnesota 55408, United States Brother (no street address) Name K Honeywell e Incorporated Representative Atlas, Michael Bee Nationality: United States of America Fragrance Tameike Building 8th floor Inside Yamakawa International Patent Office FIG. 7 is an electronic level diagram of one implementation of a crossbar switch.

FIG. 8 is a diagram of a 36X36Cl os network.

FIG. 9 is a diagram of a 16X18 CIos network.

Figure 1O shows non-provoking nrXnr self-route assignment with return network. This is a layout of the C1os network.

Figures 11a, b, and C show the input and output terminals of the crossbar used in Figure 10. FIG.

FIG. 12 is a schematic diagram of a truly non-blocking bus implementation according to the present invention. .

FIG. 13 shows a finite shape of a vine bus control device for use with the invention as described in FIG. FIG. 2 is a block diagram of a physical machine model.

FIG. 14 shows 2n-1 devices for use with the invention as described with reference to FIG. A data bus controller block employed in one of the data bus controller blocks. Figure 3 is a detailed schematic diagram of the lock;

Figure 15 is a diagram of a complete 4x4 crossbar with associated return network. .

FIG. 16 shows one message implementation of the present invention having a header portion H and a data portion. FIG. 2 is an example block diagram.

The present invention has a plurality of stages, and at least the first stage and the last stage are called "units". With a message sending system consisting of multiple crossbars called Teach a truly non-blocking switching network for use.

Each crossbar in the first stage has a header with source and destination addresses. - and one associated turn signal el! Mebuse with one means can be exchanged. A crossbar has multiple input terminals and multiple output terminals. m, and the m input terminals are labeled I-m and 1=n, respectively. connected by an nXm array of 2x2 switches organized into logical columns and logicalities. Re, , Il++lA-, PCT/Us 92106651 International Search Report

Claims (21)

[Claims] 1. It has multiple stages, at least the first stage and the last stage are called "units". the crossbars in the first stage; each of the source and destination addresses and the associated turn signal sign. means for exchanging messages each having an accompanying header. The crossbar has a plurality of input terminals n and a plurality of output terminals m. The input terminals of connected by an n×m array of 2×2 switches organized in rows and A switch is connected between the n input sources and the m output terminals, and The switch first determines that the source address in the message header is the switch's column address. second, the destination whose turn signal has a matching column address; Based on the sign of two events: it has not already been reset by a row switch. can be set to pass mode or exchange mode, and each crossbar of the final stage, In other words, each "unit" has m input terminals and n input terminals in the final stage crossbar. A crossbar of similar size to each crossbar of the first stage except that it has an output terminal. Each of the stages has a crossbar in the first stage and the last stage. are arranged such that there is some number r that is the number of -, and each of the first stages The m output terminals of each crossbar are connected to the final stage crossbar via one or more intermediate stages. Routes are assigned to the m input terminals of the loss bar, and for each output terminal of the first stage, a return signal for messages sent to subsequent stages via the output terminal of said first stage; A truly non-standard system for use as a message sending system where there are multiple routes. Blocking exchange network. 2. Outputs from output terminals 1 to m are transferred to units 1 to m in the next stage, and The return path from the stage unit is to the same crossbar from which it occurred. Go back, enter the input terminals of the same row numbers 1 to m, and connect them to the crossbar of the unit in the previous row. 2. The message transmission system of claim 1 leading to a switch in row 1. 3. The route that a message takes through the system is called the message path, and When a 2x2 switch is configured for said one message path, they A return path can be formed in the opposite direction through the switch. 1. The message transmission system described in 1. 4. The return route is set by the switch at the same time the message route is set. 4. The message transmission system according to claim 3, wherein the message transmission system is configured through duplication of a set of electronic paths that are transmitted. Tem. 5. A 2x2 switch is an optical switch also called a light valve. 4. The message transmission system according to claim 3, wherein the message transmission system is configured to enable message transmission. 6. The intermediate stage has a single output from each unit of the preceding stage, i.e. from each crossbar. It consists of multiple units connected to the power terminal, and each unit in the intermediate stage is composed of a plurality of data/bus control devices 1 to r, and each of the control devices Each is in data and control communication with the bus, and each controller in one stage is the same 1 to r buses, each bus connected to one crossbar of the succeeding stage. 2. The message transmission system according to claim 1. 7. An intermediate stage has multiple crossbars connected to a single output terminal from each crossbar of the preceding stage. It consists of a crossbar and multiple crossbars that can be labeled from 1 to 2n-1. and r input terminals and r output terminals of each of said crossbars. is the crossbar of each preceding stage and the crossbar of each succeeding stage. 2. The message transmission system of claim 1, wherein said crossbar is connected to said crossbar. 8. The output from output terminals 1 to m transfers to units 1 to m in the next stage, and The return path from the unit in the stage is the same crossbar from which it occurred. Return to , enter the input terminals of the same row numbers 1 to m, and connect the crossbar of the unit in the previous row. 2. The message transmission system of claim 1, wherein the message transmission system is connected to a switch in row 1 of the message transmission system. 9. The output from output terminals 1 to m transfers to units 1 to m in the next stage, and The return path from the unit in the stage is the same crossbar from which it occurred. Return to , enter the input terminals of the same row numbers 1 to m, and connect the crossbar of the unit in the previous row. 8. The message transmission system of claim 7, wherein the message transmission system is connected to a switch in row 1 of the message transmission system. 10. The route a message takes through a network is called the message route. , when the 2×2 switch is configured for the one message path, configured to form a return path in the opposite direction through those switches 7. The message transmission system according to claim 6. 11. The route a message takes through a system can also be called a message path. Specifically, when the 2x2 switch is configured for one message path, it The claim is configured so that a return path can be formed in the opposite direction through these switches. Message transmission system according to item 7. 12. The return path is the same as established by the message sent from the source node. 4. The message sending system of claim 3, wherein the message sending system utilizes the same switch settings. 13. The return route is set up by the switch at the same time that the message route is set up. Claims constructed through replication of a set of electronic paths set by switches defined by Message transmission system according to item 11. 14. A 2x2 switch is an optical switch also called a light valve. 11. The message transmission system according to claim 10, wherein the message transmission system is configured to enable message transmission. 15. A 2x2 switch is an optical switch also called a light valve. 12. The message transmission system according to claim 11, wherein the message transmission system is configured to enable message transmission. 16. The message transmission system of claim 6, wherein there are three stages. 17. The message transmission system of claim 7, wherein there are three stages. 18. Inputs from each data/bus control device to each bus indicate whether the bus is in use or not. It consists of a control communication path that sets a signal to determine the status, and leads to the bus. A data communication path is a claim for communicating messages to and from that bus. Message transmission system according to item 6. 19. The control communication path is the minimum required for message headers to return to the bus. 19. The apparatus according to claim 18, wherein the apparatus is maintained in an in-use state for a duration longer than a large delay time. Message sending system. 20. The message of claim 1, wherein the 2x2 switch is a broadcast switch. transmission system. 21. A switch set from its default state by a message header will is also greater than or equal to the maximum delay required for message headers to return to that switch. 2. The message sending of claim 1, wherein the non-default settings are maintained for a duration of . system.