JPH0650778B2 - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereofInfo
- Publication number
- JPH0650778B2 JPH0650778B2 JP18211685A JP18211685A JPH0650778B2 JP H0650778 B2 JPH0650778 B2 JP H0650778B2 JP 18211685 A JP18211685 A JP 18211685A JP 18211685 A JP18211685 A JP 18211685A JP H0650778 B2 JPH0650778 B2 JP H0650778B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- semiconductor layer
- impurity
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000012535 impurity Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 6
- 229910004613 CdTe Inorganic materials 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 2
- 239000006104 solid solution Substances 0.000 claims 2
- AQCDIIAORKRFCD-UHFFFAOYSA-N cadmium selenide Chemical compound [Cd]=[Se] AQCDIIAORKRFCD-UHFFFAOYSA-N 0.000 description 12
- 238000007740 vapor deposition Methods 0.000 description 7
- 239000002245 particle Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000001771 vacuum deposition Methods 0.000 description 3
- WUPHOULIZUERAE-UHFFFAOYSA-N 3-(oxolan-2-yl)propanoic acid Chemical compound OC(=O)CCC1CCCO1 WUPHOULIZUERAE-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052980 cadmium sulfide Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005685 electric field effect Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は薄膜トランジスタに関するものであり、特にそ
のリーク電流が少ない優れた薄膜トランジスタを提供す
るものである。Description: TECHNICAL FIELD The present invention relates to a thin film transistor, and particularly to an excellent thin film transistor having a small leak current.
従来の技術 薄膜トランジスタは、ソースとドレイン電極間の導電体
の電気伝導度を導電体と接する絶縁物層を介して設けら
れた第３の電極（ゲート電極）に印加する電圧によって
制御するいわゆる電界効果型トランジスタとして知られ
ている。従来の薄膜トランジスタの構成の一例を第４図
に示す。ガラス等の絶縁性基板１上に数ミクロンから数
千ミクロンの所定の幅と長さを有するクロム，金，アル
ミニウム等の金属からなるゲート電極２が設けられてお
り、この電極をおおって厚さ数千オングストロームで二
酸化シリコン（SiO2）や窒化シリコン（Si3N4）や酸化
アルミニウム（Al2O3）や酸化タンタル（Ta2O5）等から
なる絶縁物層３が設けられており、ゲート電極２上の絶
縁物層３表面に硫化カドミウム（CdS）やセレン化カド
ミウム（CdSe）等の半導体層４が設けられ、この半導体
層に接して数ミクロンから数十ミクロンの所定の間隔を
隔ててソース電極５およびドレイン電極６が設けられて
いる。2. Description of the Related Art In a thin film transistor, a so-called electric field effect in which the electric conductivity of a conductor between a source electrode and a drain electrode is controlled by a voltage applied to a third electrode (gate electrode) provided through an insulator layer in contact with the conductor Type transistors are known. An example of the structure of a conventional thin film transistor is shown in FIG. A gate electrode 2 made of a metal such as chromium, gold, or aluminum having a predetermined width and length of several microns to several thousands microns is provided on an insulating substrate 1 made of glass or the like. An insulator layer 3 made of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ) or the like is provided at a thickness of several thousand angstroms. A semiconductor layer 4 such as cadmium sulfide (CdS) or cadmium selenide (CdSe) is provided on the surface of the insulator layer 3 on the gate electrode 2, and the semiconductor layer 4 is in contact with the semiconductor layer at a predetermined interval of several microns to several tens of microns. A source electrode 5 and a drain electrode 6 are provided.
半導体層４は真空蒸着法で形成されるが、多結晶体であ
り、平均粒径が数１００〜数１０００Åの多くの粒子か
ら成っている。その各粒子間にはキャリアの移動を阻止
するような界面電位が存在している。製造において蒸着
条件や熱処理条件のわずかな変化により粒径や組成が変
化し、したがって界面電位の大きさも変わり薄膜トラン
ジスタのドレイン電流が変動することが知られている。
特開昭５９−９４４６０号公報には、上記のようなドレ
イン電流の変動のない、ドレイン電流の大きな安定な薄
膜トランジスタを均一に再現性よく容易に得られる方法
を示している。すなわち、半導体層４が、たとえばCdSe
蒸着膜のようなｎ型の導電性を有する場合、多結晶粒子
間の界面電位を低下させる作用を有するｎ型の導電性を
与える不純物たとえばＩｕを適当量添加して、熱処理条
件を制御することにより、所望のドレイン電流を容易に
再現性よく得ることができる技術である。The semiconductor layer 4 is formed by a vacuum vapor deposition method and is a polycrystal, and is composed of many particles having an average particle size of several hundred to several thousand Å. There is an interfacial potential that prevents the movement of carriers between the particles. It is known that a slight change in vapor deposition conditions or heat treatment conditions in manufacturing changes the particle size and composition, and thus changes the magnitude of the interfacial potential and changes the drain current of the thin film transistor.
Japanese Unexamined Patent Publication No. 59-94460 discloses a method of easily obtaining a stable thin film transistor having a large drain current without the above-mentioned fluctuation of the drain current, with good reproducibility. That is, the semiconductor layer 4 is, for example, CdSe.
When the film has n-type conductivity such as a vapor-deposited film, an appropriate amount of an impurity, such as Iu, which gives an n-type conductivity having an action of lowering the interfacial potential between polycrystalline particles is added to control heat treatment conditions. Is a technique by which a desired drain current can be easily obtained with good reproducibility.
発明が解決しようとする問題点 薄膜トランジスタの半導体層のうち、ゲートの電位の影
響を受けてコンダクタンスが変化する領域は、絶縁層と
の界面から数十オングストロームの厚さの部分である。
したがって、薄膜トランジスタのリーク電流の観点から
すれば、半導体層の厚さは、理想的には数十オングスト
ロームであれば、リーク電流の少ないＯＮ−ＯＦＦ比の
大きい薄膜トランジスタが実現できる。しかし、半導体
層を数十オングストロームの厚さに制御して形成するの
は実用上困難であるだけでなく、その形成された膜の結
晶性に問題が生じたり、半導体層の表面への各種イオン
の吸着等の効果がより顕著にあらわれて、ドレイン電流
の制御上好ましくない。しかし、一方で、従来技術で述
べたように、ドレイン電流が大きく安定した薄膜トラン
ジスタを得るために、たとえばｎ型の半導体層に、さら
にｎ型の不純物を適量ドープする技術があり、薄膜トラ
ンジスタのリーク電流の観点からすれば、半導体層の固
有の伝導度がドーピングによって大きくなっており、そ
のためリーク電流が大きくなって好ましくない。Problems to be Solved by the Invention In a semiconductor layer of a thin film transistor, a region where the conductance changes under the influence of the gate potential is a portion having a thickness of several tens of angstroms from an interface with an insulating layer.
Therefore, from the viewpoint of the leak current of the thin film transistor, if the thickness of the semiconductor layer is ideally several tens of angstroms, a thin film transistor with a small leak current and a large ON-OFF ratio can be realized. However, it is not practically difficult to form a semiconductor layer with a thickness of several tens of angstroms, and a problem occurs in the crystallinity of the formed film, and various ions on the surface of the semiconductor layer are generated. The effect such as the adsorption of is more prominent, which is not preferable in controlling the drain current. However, on the other hand, as described in the prior art, in order to obtain a thin film transistor in which the drain current is large and stable, for example, there is a technique in which an n-type semiconductor layer is further doped with an appropriate amount of n-type impurities. From this point of view, the intrinsic conductivity of the semiconductor layer is increased due to the doping, and therefore the leakage current is increased, which is not preferable.
問題点を解決するための手段 先に述べたように、薄膜トランジスタとしての機能を主
に果すところいわゆるチャンネル部は絶縁層と半導体層
の界面から半導体層の数十オングストロームの領域であ
り、不純物のドーピングによって多結晶粒子間の界面電
位を低下させる領域は、その領域だけでよい。従来技術
においてはその領域以外も不純物がドーピングされるこ
とによって多少低抵抗化し、リーク電流となっている。As described above, the so-called channel portion that mainly functions as a thin film transistor is a region of several tens of angstroms of the semiconductor layer from the interface between the insulating layer and the semiconductor layer, and the doping of impurities is performed. The region in which the interfacial potential between the polycrystalline particles is lowered by is only that region. In the prior art, the resistance is somewhat lowered by doping impurities other than that region, resulting in a leak current.
上記のような問題点を解決するために、本発明において
は、半導体層が半導体層と同じ導電型の不純物を添加し
た第１層と異なる導電型の不純物を添加した第２層とか
らなる構成を特徴とした薄膜トランジスタを提案する。In order to solve the above problems, in the present invention, the semiconductor layer is composed of a first layer to which an impurity of the same conductivity type as that of the semiconductor layer is added and a second layer to which an impurity of a different conductivity type is added. Is proposed.
上記の目的を達成するためには、以下の工程によって薄
膜トランジスタを製造すればよい。In order to achieve the above object, the thin film transistor may be manufactured by the following steps.
(a)絶縁基板上にゲート電極、続いて絶縁層を形成する
工程 (b)前記ゲート絶縁層上に以下に形成する半導体層と同
じ導電型の不純物を適量真空蒸着によって供給する工程 (c)半導体層を真空蒸着によって形成する工程 (d)前記半導体層とことなる導電型の不純物を半導体層
の表面に適量真空蒸着によって供給する工程 (e)ソース・ドレイン電極を形成する工程 (f)前記薄膜トランジスタを非酸化性ガスもしくは真空
雰囲気中で熱処理する工程 作用 本発明の薄膜トランジスタの半導体層のうちその半導体
層と同じ導電型の不純物が適量添加された第１の半導体
層は、特開昭６９−０４４６０号公報に記載されている
ように、多結晶の粒子界の界面電位を低下させ、安定し
た大きなドレイン電流を再現性よく得るために必要な層
であり、ゲート電極からの電界効果は、主にこの層のコ
ンダクタンスを変化させて薄膜トランジスタの機能を果
たすチャンネル部であり、第２の半導体層は、従来の構
成において薄膜トランジスタのＯＦＦ時のリーク電流の
大きな原因となっていたが、第１の半導体層の導電型と
は異なる導電型の不純物を適量添加することによって高
抵抗化し、リーク電流を低減する作用がある。(a) a step of forming a gate electrode on an insulating substrate and subsequently an insulating layer (b) a step of supplying an appropriate amount of impurities of the same conductivity type as a semiconductor layer to be formed below on the gate insulating layer by vacuum vapor deposition (c) A step of forming a semiconductor layer by vacuum vapor deposition (d) a step of supplying an appropriate amount of impurities of a conductive type which is different from the semiconductor layer to the surface of the semiconductor layer by vacuum vapor deposition (e) a step of forming source / drain electrodes (f) the above The step of heat-treating the thin film transistor in a non-oxidizing gas or a vacuum atmosphere. Action Among the semiconductor layers of the thin film transistor of the present invention, the first semiconductor layer to which an appropriate amount of impurities of the same conductivity type as that of the semiconductor layer is added is disclosed in JP-A-69- As described in JP-A-04460, it is a layer necessary for lowering the interfacial potential of a polycrystalline grain boundary and obtaining a stable large drain current with good reproducibility. The field effect of is a channel portion that mainly functions as a thin film transistor by changing the conductance of this layer, and the second semiconductor layer is a major cause of the leak current when the thin film transistor is OFF in the conventional configuration. However, by adding an appropriate amount of impurities of a conductivity type different from that of the first semiconductor layer, the resistance is increased and the leak current is reduced.
また、先に述べた(a)〜(f)の製造工程によって、厚さに
して数十オングストロームに制御された第１の半導体層
が実現される。Further, by the manufacturing steps (a) to (f) described above, the first semiconductor layer whose thickness is controlled to several tens of angstroms is realized.
詳細には本発明によれば、薄膜トランジスタの半導体層
を形成する工程(c)の前に、その半導体層と同じ導電型
の不純物を供給する工程(b)を、そのあとに半導体層と
異なる導電型の不純物を供給する工程(d)を設け、適当
な熱処理工程(f)によってそれぞれの不純物を半導体層
の絶縁層との界面側及び半導体層の表面側より拡散させ
ると、不純物の相互拡散が生じ界面側は半導体層の導電
型でより高濃度な層が形成されて好適なチャンネル部と
なり、表面側から内側に向っては異なる導電型の不純物
によって補償された高抵抗な層が形成されその結果とし
て本発明の構成が実現できる。More specifically, according to the present invention, before the step (c) of forming the semiconductor layer of the thin film transistor, the step (b) of supplying impurities of the same conductivity type as the semiconductor layer is performed, and thereafter, the step of supplying a different conductivity from that of the semiconductor layer is performed. When the step (d) of supplying the impurity of the type is provided and each impurity is diffused from the interface side of the semiconductor layer with the insulating layer and the surface side of the semiconductor layer by the appropriate heat treatment step (f), the mutual diffusion of the impurities is caused. A high-concentration layer having a conductivity type of the semiconductor layer is formed on the interface side to form a suitable channel portion, and a high resistance layer compensated by impurities of different conductivity types is formed from the surface side toward the inside. As a result, the configuration of the present invention can be realized.
実施例 本発明の一実施例による薄膜トランジスタの断面図を第
１図に示している。ガラス基板１上にアルミニウムなど
からなるゲート電極２があり、前記ゲート電極２上に、
Ta2O5あるいはAl2O5あるいはAl−Ta−Ｏなどの絶縁層３
がある。さらに前記絶縁層３の上にInやAlあるいはGa等
が不純物として添加された数十オングストロームから百
オングストローム程度の厚さのCdSe層４−ａがありまた
さらにその上にはCuが不純物として添加されたCdSe層４
−ｂが設けられ、これらの半導体層に接して数ミクロン
から数十ミクロンの所定の間隔を隔ててソース電極５お
よびドレイン電極６が設けられた構成である。CdSe薄膜
は、本来ｎ型の導電型を示し、不純物のIn,AlあるいはG
a等の不純物は、ドナー不純物であるためにCdSe薄膜多
結晶体の粒界電位障壁を低下させるが、不純物のCuは、
深いアクセプター不純物であるために、外因性あるいは
内因性のドナー不純物を補償するためにCdSe薄膜が高抵
抗化する。したがって、ゲート電極からの電界効果によ
って影響をうけるCdSe半導体層４−ａ以外のCdSe半導体
層４−ｂがCuによって高抵抗化されているためにリーク
電流が低減され、ＯＮ−ＯＦＦ比の大きな薄膜トランジ
スタが実現できる。以上のような薄膜トランジスタを製
造するための実施例の一例を第２図示しており、以下に
その説明をする。Example FIG. 1 is a sectional view of a thin film transistor according to an example of the present invention. There is a gate electrode 2 made of aluminum or the like on a glass substrate 1, and on the gate electrode 2,
Insulating layer 3 such as Ta 2 O 5 or Al 2 O 5 or Al-Ta-O
There is. Further, there is a CdSe layer 4-a having a thickness of several tens angstroms to 100 angstroms in which In, Al, Ga or the like is added as an impurity on the insulating layer 3, and further Cu is added as an impurity on the CdSe layer 4-a. CdSe layer 4
-B is provided, and the source electrode 5 and the drain electrode 6 are provided in contact with these semiconductor layers at a predetermined interval of several microns to several tens of microns. The CdSe thin film originally shows an n-type conductivity type and contains impurities such as In, Al or G
Impurities such as a lower the grain boundary potential barrier of the CdSe thin-film polycrystal because they are donor impurities, but the impurity Cu is
Since it is a deep acceptor impurity, the CdSe thin film has a high resistance to compensate for an extrinsic or intrinsic donor impurity. Therefore, since the CdSe semiconductor layer 4-b other than the CdSe semiconductor layer 4-a that is affected by the electric field effect from the gate electrode is made high in resistance by Cu, the leak current is reduced, and the thin film transistor having a large ON-OFF ratio. Can be realized. A second example of the embodiment for manufacturing the above-described thin film transistor is shown in the second drawing, and the description will be given below.
(a)ガラス基板１上にAlを抵抗加熱真空蒸着法によって
数百オングストロームの厚さに蒸着し、フォトエッチン
グによってゲート電極パターン２を形成する。つづいて
AlとTaの複合ターゲットを１０〜３０％の酸素ガスを含
んだアルゴンガス中でスパッターすることによってAl−
Ta−Ｏ絶縁膜３をメタルマスクによって選択的に形成す
る。(a) Al is vapor-deposited on the glass substrate 1 by resistance heating vacuum vapor deposition to a thickness of several hundred angstroms, and the gate electrode pattern 2 is formed by photoetching. Continued
By sputtering a composite target of Al and Ta in an argon gas containing 10 to 30% oxygen gas, Al-
The Ta-O insulating film 3 is selectively formed using a metal mask.
(b)抵抗加熱真空蒸着法によってIn４−ａ′を数〜数十
オングストロームの厚さにメタルマスクによって選択的
に形成する。(b) In4-a 'is selectively formed with a metal mask to a thickness of several to several tens of angstroms by a resistance heating vacuum deposition method.
(c)抵抗加熱真空蒸着法によってCdSe層４−ｂ′を数百
〜数千オングストロームの厚さにメタルマスクによって
選択的に形成する。(c) A CdSe layer 4-b 'is selectively formed by a resistance heating vacuum deposition method to a thickness of several hundred to several thousand angstroms by a metal mask.
(d)抵抗加熱真空蒸着法によってCu４−ｃ′を数〜数十
オングストロームの厚さにメタルマスクによって選択的
に形成する。(d) Cu4-c 'is selectively formed with a metal mask to a thickness of several to several tens of angstroms by a resistance heating vacuum deposition method.
(e)抵抗加熱真空蒸着法によってAlを数千オングストロ
ームの厚さに蒸着し、リフトオフ法によってソース電極
５及びドレイン電極６を形成する。(e) Al is vapor-deposited to a thickness of several thousand angstroms by the resistance heating vacuum vapor deposition method, and the source electrode 5 and the drain electrode 6 are formed by the lift-off method.
(f)非酸化性ガスもしくは真空雰囲気中、３００℃〜４
００℃の温度で熱処理することによって第１図の構成の
薄膜トランジスタを得る。(f) 300 ° C to 4 in non-oxidizing gas or vacuum atmosphere
A thin film transistor having the structure shown in FIG. 1 is obtained by heat treatment at a temperature of 00 ° C.
以上に説明した製造プロセスにおいて、(c)及び(d)にか
えて、特願昭６９−６４０７３号に記述されている方
法、すなわち、あらかじめ蒸着源のCdSeにCuを仕込んで
おき蒸着るつぼの温度コントロールによって４−ｂ′層
及び４−ｃ′層を形成する方法も有効である。In the manufacturing process described above, the method described in Japanese Patent Application No. 69-64073 instead of (c) and (d), that is, the temperature of the evaporation crucible after Cu is previously charged in CdSe as the evaporation source. A method of forming a 4-b 'layer and a 4-c' layer by control is also effective.
実際に作製された薄膜トランジスタのゲート電圧１０Ｖ
の時のドレイン−ソース間電圧に対するドレイン電流の
変化を第３図に示している。図中Ａに示す破線のデータ
は、従来構成（第４図）で製造方法としては前記(d)の
工程を用いない薄膜トランジスタによって得られたもの
であり、図中Ｂに示す実線のデータは、本発明の構成
（第１図）で製造方法として先に述べた本発明の方法に
よって作製された薄膜トランジスタによって得られたも
のである。第３図から明らかなように本発明によってリ
ーク電流の低減がなされている。Gate voltage of actually manufactured thin film transistor 10V
FIG. 3 shows the change in drain current with respect to the drain-source voltage at the time. The broken line data shown in A in the figure is obtained by a thin film transistor which does not use the step (d) as a manufacturing method in the conventional configuration (FIG. 4), and the solid line data shown in B in the figure is It is obtained by the thin film transistor manufactured by the method of the present invention described above as the manufacturing method in the configuration of the present invention (FIG. 1). As is clear from FIG. 3, the present invention reduces the leak current.
発明の効果 本発明の構成及び製造方法によって得られた薄膜トラン
ジスタは、ドレイン電流のチャンネル部以外を高抵抗化
することによって、従来得られるドレイン電流を維持し
たまま、リーク電流を低減でき、結果として、ドレイン
電流が大きく安定しかつリーク電流の少ない薄膜トラン
ジスタを再現性よく得るために貢献するものである。The thin film transistor obtained by the configuration and manufacturing method of the present invention, by increasing the resistance other than the channel portion of the drain current, while maintaining the conventionally obtained drain current, it is possible to reduce the leakage current, as a result, This contributes to obtaining a thin film transistor having a large drain current and being stable and having a small leak current with good reproducibility.
第１図は本発明の一実施例における薄膜トランジスタの
断面図、第２図は本発明の一実施例における薄膜トラン
ジスタの製造方法を説明するための図、第３図は本発明
及び従来構成の薄膜トランジスタの特性図、第４図は従
来の薄膜トランジスタの断面図である。 １……絶縁基板、２……ゲート電極、３……絶縁層、４
……半導体層、５……ソース電極、６……ドレイン電
極。FIG. 1 is a sectional view of a thin film transistor according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention, and FIG. FIG. 4 is a sectional view of a conventional thin film transistor. 1 ... Insulating substrate, 2 ... Gate electrode, 3 ... Insulating layer, 4
...... Semiconductor layer, 5 ...... Source electrode, 6 ...... Drain electrode.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 野村 幸治 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 小川 久仁 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Nomura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Kuni Ogawa, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.
Claims (4)
記ゲート電極上に前記ゲート電極をおおうように設けら
れたゲート絶縁層と、前記ゲート絶縁層上に不純物の添
加された第１の半導体層と、前記半導体層上に前記不純
物とは異なる導電型を示す効果を持つ不純物が添加され
た第２の半導体層と、前記半導体層に接続されたソース
電極とドレイン電極とよりなり、前記第１の半導体層が
Ａｌ，Ｇａ，Ｉｎのうちの１種類を不純物として添加さ
れたII−VI族化合物半導体よりなり、前記第２の半導体
層がＣｕを不純物として添加されたII−VI族化合物半導
体よりなることを特徴とする薄膜トランジスタ。1. A gate electrode provided on an insulating substrate, a gate insulating layer provided on the gate electrode so as to cover the gate electrode, and a first impurity-doped first insulating layer on the gate insulating layer. A semiconductor layer, a second semiconductor layer to which an impurity having a conductivity type different from that of the impurity is added, and a source electrode and a drain electrode connected to the semiconductor layer, The first semiconductor layer is made of a II-VI group compound semiconductor doped with one of Al, Ga and In as an impurity, and the second semiconductor layer is made of a II-VI group compound doped with Cu as an impurity. A thin film transistor comprising a semiconductor.
ｅ，ＣｄＴｅ及びそれらの固溶体であることを特徴とす
る特許請求の範囲第１項記載の薄膜トランジスタ。2. A II-VI group compound semiconductor is CdS, CdS.
The thin film transistor according to claim 1, which is e, CdTe, or a solid solution thereof.
成する工程と、前記ゲート電極上に前記ゲート電極をお
おうようにゲート絶縁層を形成する工程と、Ａｌ，Ｇ
ａ，Ｉｎの何れかの第１の不純物を堆積する工程と、II
−VI族化合物半導体層を形成する工程と、Ｃｕの第２の
不純物を堆積する工程と、前記II−VI族化合物半導体に
接続するソース電極及びドレイン電極を形成する工程
と、前記第１及び第２の不純物を前記半導体層に拡散す
るための熱処理工程とよりなることを特徴とする薄膜ト
ランジスタの製造方法。3. A step of forming a gate electrode provided on an insulator substrate, a step of forming a gate insulating layer on the gate electrode so as to cover the gate electrode, Al, G
depositing a first impurity of a or In; II
Forming a group-VI compound semiconductor layer, depositing a second impurity of Cu, forming a source electrode and a drain electrode connected to the group II-VI compound semiconductor, 2. A method of manufacturing a thin film transistor, comprising a heat treatment step for diffusing the impurity of 2 into the semiconductor layer.
ｅ，ＣｄＴｅ及びそれらの固溶体であることを特徴とす
る特許請求の範囲第３項記載の薄膜トランジスタの製造
方法。4. A II-VI group compound semiconductor is CdS, CdS.
The method for manufacturing a thin film transistor according to claim 3, wherein the thin film transistor is e, CdTe, or a solid solution thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18211685A JPH0650778B2 (en) | 1985-08-20 | 1985-08-20 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18211685A JPH0650778B2 (en) | 1985-08-20 | 1985-08-20 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6242564A JPS6242564A (en) | 1987-02-24 |
| JPH0650778B2 true JPH0650778B2 (en) | 1994-06-29 |
Family
ID=16112612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18211685A Expired - Lifetime JPH0650778B2 (en) | 1985-08-20 | 1985-08-20 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0650778B2 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2751164B2 (en) * | 1987-10-05 | 1998-05-18 | 松下電器産業株式会社 | Method for manufacturing thin film transistor |
| JPH0834313B2 (en) * | 1989-10-09 | 1996-03-29 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP4194436B2 (en) | 2003-07-14 | 2008-12-10 | キヤノン株式会社 | Field effect organic transistor |
| US20070178710A1 (en) * | 2003-08-18 | 2007-08-02 | 3M Innovative Properties Company | Method for sealing thin film transistors |
| JP4727684B2 (en) * | 2007-03-27 | 2011-07-20 | 富士フイルム株式会社 | Thin film field effect transistor and display device using the same |
| JP2008276212A (en) * | 2007-04-05 | 2008-11-13 | Fujifilm Corp | Organic electroluminescent display device |
| JP2008276211A (en) * | 2007-04-05 | 2008-11-13 | Fujifilm Corp | Organic electroluminescent display device and patterning method |
| JP2009031742A (en) * | 2007-04-10 | 2009-02-12 | Fujifilm Corp | Organic electroluminescence display device |
| JP5339772B2 (en) * | 2007-06-11 | 2013-11-13 | 富士フイルム株式会社 | Electronic display |
| JP5489423B2 (en) * | 2007-09-21 | 2014-05-14 | 富士フイルム株式会社 | Radiation imaging device |
| JP5512078B2 (en) * | 2007-11-22 | 2014-06-04 | 富士フイルム株式会社 | Image forming apparatus |
| JP5191247B2 (en) * | 2008-02-06 | 2013-05-08 | 富士フイルム株式会社 | Thin film field effect transistor and display device using the same |
-
1985
- 1985-08-20 JP JP18211685A patent/JPH0650778B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6242564A (en) | 1987-02-24 |
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