JPH0650498B2 - Multiprocessor system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system suitable for enabling flexible destination selection in communication between processors.

[Conventional technology]

The control method in the conventional multiprocessor system is
Since the purpose is to distribute the execution of the program to each processor, 1
An operation command is issued from one processor to another processor. That is, conventionally, no consideration has been given to issuing operation commands to a plurality of processors at the same time.

[Problems to be Solved by the Invention]

When a control method according to the above-mentioned conventional technique, that is, a control method in which one processor issues an operation command to another one processor, is issued from one processor to all other plural processors, It requires a time slot (a basic unit of time for a command). In this case, if a plurality of processors only share the execution of the program, there arises a problem that the overhead becomes large. Further, when a plurality of processors share the control, a problem occurs that a transient state occurs over a plurality of time slots in the system as a whole. Even when one of the plurality of processors shares the execution of the program and the other one shares the control, the same problem as described above occurs.

An object of the present invention is, when issuing an operation command from one processor to a plurality of other processors, at the same time, a plurality of arbitrary destination processors can be executed without causing the problem of overhead and the problem of putting the system in a transient state. It is to provide a multiprocessor system that issues an operation command by designating.

[Means for Solving the Problems]

The object is to provide a system bus having a common signal line (hereinafter referred to as a common signal line) to which a plurality of processors are connected, each processor having its own identification number, and from one processor to another processor. In a multiprocessor system that simultaneously transmits an operation command and an identification number command that specifies the target processor of the operation command via a common signal line on the system bus, the common signal line that transmits the operation command and the identification number command is different A common signal line for another identification number modification information is provided in the system bus, and each processor receives the identification number modification information and the identification number command sent simultaneously with the operation command through the system bus. Register, the received identification number command, the received identification number modification information, and its own identification number By providing the hardware circuit that determines whether the processor is achieved.

[Action]

As the modification information, for example, as described in claim 2, the destination individual designation information, the broadcast information, the function definition information for supporting a partial mask of the identification number, and the accompanying information represented by the mask pattern are divided. In order to specify the case where the identification number specifies only one processor, all the processors, the part of the identification number matches, the case where the identification number is a certain number or more, etc. It can be used as information, and an arbitrary group of a plurality of processors can be designated and operated simultaneously.

In this operation processing, since the modification information is sent through an independent common signal line, it can be processed by all hardware and high speed processing is possible. Further, the other information can be received only when it is determined that the other information is necessary by the modification information received from the independent common signal line, and unnecessary information need not be received. The load on is reduced.

Further, since the modification information is transmitted and received between the processors through the common signal line on the system bus, and each processor has a circuit for judging the modification information, any one of the plurality of processors can be the transmission processor. . That is, it is possible to construct a multiprocessor system in which all the processors operate equally.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention. In this system, four processors (BPUs) 1, 2, 3, 4 that operate independently,
A main memory (MS) 5 and an input / output device control mechanism (IOC) 6 such as a disk or printer are connected to each other via a system bus 7. The system bus 7 is composed of an address line 8, a data line 9, a function line 10 and an identification number modification information line 11. Access from each of the processors 1 to 4 to the main memory 5 or the input / output control mechanism 6 is performed using the address line 8, the data line 9 and the function line 10. In this case, the function line 10 indicates a read or write access, and data is read or written from the address designated by the address line 8 via the data line 9. On the other hand, the operation command between the processors is the address line 8 and the function line 10.
Together with the identification number modification information line 11. In this case, the function line 10 is used to specify that it is an operation command between processors, and the address line 8
Specify the identification number with. Further, the identification number modification information line 11
By defining the usage of the identification number by, each processor determines whether or not it should operate.

FIG. 2 is a configuration diagram of the identification number information line. In this embodiment, the BRDCST bit, the MSK bit, the FU
It consists of N bits and a PARA bit group of 4 bits.

If the BRDCST bit is "1", it means broadcast,
All the processors 1 to 4 on the system bus 7 start operating at the same time. If the MSK bit is "1", PA
It indicates that the bit string shown in RA is used as a pattern for masking the identification number. Each of the processors 1 to 4 on the system bus 7 compares the identification number designated by the address line 8 with a portion of its own identification number which is not masked by the mask pattern,
If they match, the operation is performed.

Further, when the FUN bit is "1", it indicates that the bit string shown in PARA is an operation symbol. That is, for example, when the bit string shown in PARA indicates “>”, each of the processors 1 to 4 compares its own identification number with the identification number on the address line, and operates when the former is larger than the latter. To do.

When all the bits on the identification number modification information line 11 are “0”, only the processor designated by the identification number on the address line 8 operates.

FIG. 3 is a detailed configuration diagram of a main part of each processor. In the figure
Reference numerals 20 and 21 denote function line transmission and reception registers, and 22 and 23 denote address transmission and reception registers, respectively. Also, 24 and 25 are data transmission / reception registers, 26,
Reference numeral 27 indicates a register for transmitting and receiving identification number modification information. 28
Is a circuit for generating its own identification number, 29 is a comparator for comparing its own identification number with the identification number stored in the address reception register 23, and 30 is its own identification number and address reception register
23 shows a computing unit that performs computation with the identification number stored in 23.

When a certain processor activates the main memory 5 or the input / output control device 6, the function transmission register 20 designates a write or read function, and the address transmission register 22 designates an address. In the case of write, at the same time as this, the data transmission register
The data to be written is specified by 24. In the case of reading, the data reception register 25 receives the data coming via the system bus 7. When a processor issues an operation command to another processor, the function transmission register 20 specifies that it is an inter-processor operation command, and the address transmission register 22 specifies the identification number. Further, the identification number modification information transmission register 26 informs another processor of how to use the identification number.

On the other hand, when the processor detects that the inter-processor operation command function is designated by the contents of the function reception register 21, it interprets the identification number by the contents of the identification number modification information reception register 27 and determines whether or not it operates. Is determined.

For example, when the BRDCST bit which is 1 input of the 3-input OR gate 31 which outputs an operation command signal to another circuit in the processor becomes "1"(broadcast; all processors operate simultaneously), the signal "1" Is given as an operation command signal to other circuits via the OR gate 31 regardless of the contents of the address reception register 23.

When the MSK bit applied to the enable terminal E of the comparator 29 becomes "1", the output of the comparator 29 is validated, and the output of its own identification number generation circuit 28 and the reception identification number of the address reception register 23 become Are respectively masked by the PARA bid group and then compared. If the comparison results match, the "1" signal is transmitted to another circuit through the gate 31.

When the FUN bit given to the enable terminal E of the arithmetic unit 30 becomes "1", the output of the arithmetic unit 30 is validated and the arithmetic unit 30 is operated by the PARA bit group input to the F terminal.
The arithmetic expression of is specified. Then, the arithmetic unit 30 calculates its own identification number and the reception identification number of the address reception register 23 by the above arithmetic expression, and when the arithmetic result is "true", that is, when its own processor operates, it is "1". The signal is transmitted to another circuit through the gate 31.

It goes without saying that the modification information is not limited to the broadcast information described in the embodiments.

〔The invention's effect〕

According to the present invention, it is possible to simultaneously specify various combinations of processors in an inter-processor operation command without the occurrence of overhead or a transient state, and it is possible to control a multiprocessor with a high degree of freedom. In addition, the multiprocessor system to which the present control method is applied has an effect that the operation speed is increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a block diagram of a modification information line, and FIG. 3 is a detailed block diagram of a main part of the processor shown in FIG. 1 to 4 ... Processor, 5 ... Main memory, 6 ... Input / output control mechanism, 7 ... System bus, 8 ... Address line, 9 ... Data line, 10 ... Function line, 11 ... Modification information Line, 20 …… Function transmission register, 21 …… Function line reception register,
22 …… Address transmission register, 23 …… Address reception register, 24 …… Data transmission register, 25 …… Data reception register, 26 …… Modification information transmission register, 27 …… Modification information reception register, 28 …… Identification number generation Circuit, 29 …… Comparator, 30 …… Computer, 31 …… OR gate.

Front Page Continuation (72) Inventor Terumitsu Obama 5-2-1 Omika-cho, Hitachi City, Ibaraki Pref., Within Hiritsu Process Computer Engineering Co., Ltd. (56) References JP-A 61-45647 (JP, A) JP-A Sho 62-263562 (JP, A) JP-A-58-19953 (JP, A)

Claims (2)

[Claims] 1. A system bus having a common signal line to which a plurality of processors are connected (hereinafter referred to as a common signal line) is provided, and each processor has its own identification number and one processor to another processor. On the other hand, in a multiprocessor system that simultaneously transmits an operation command and an identification number command that specifies the target processor of the operation command via a common signal line on the system bus, the common signal line that transmits the operation command and the identification number command is A different common signal line for different identification number modification information is provided in the system bus, and the identification number modification information and the identification number command sent to each processor simultaneously with the operation command are sent to each processor. From the receiving register, the received identification number command, the received identification number modification information, and its own identification number Multiprocessor system characterized by providing a hardware circuit that determines whether the processor. 2. The decoration information according to claim 1, wherein the destination individual designation information, the broadcast information, the function definition information for supporting a partial mask of the identification number, and the accompanying information represented by a mask pattern. A multiprocessor system characterized by being divided into two parts.