JPH0648778B2 - AFC method for satellite broadcasting receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present application relates to satellite broadcast receiving technology, and relates to an indoor receiver called a BS tuner.

(B) Conventional Technology In ordinary satellite broadcasting, an NTSC standard video signal is FM-modulated and transmitted as a 12 GHz band FM video signal.

On the receiving side, after converting the 12 GHz band FM video signal to the 1 GHz band first intermediate frequency signal, 402.78 MHz is further added.
After down-converting to a second intermediate frequency signal in a frequency band including z, FM demodulation is performed and a video signal is output.

The oscillation frequency of the local oscillation circuit for this down conversion is well controlled by the AFC circuit (automatic frequency control circuit).

The AFC operation is performed by a plurality of circuits forming an AFC loop.

Ordinary AFC utilizes the fact that the DC signal level of the sync signal portion of the video signal output from the FM demodulation circuit corresponds to the frequency of the second intermediate frequency signal, detects the level of this DC signal, and performs this detection. As a result, the oscillation frequency of the local oscillator circuit was feedback-controlled (Japanese Patent Laid-Open No. 57-135).
582).

However, the DC signal has a drawback that it is easily affected by drift or the like.

Therefore, a technique has been considered in which the frequency of the second intermediate frequency signal (hereinafter referred to as the second IF signal) is counted and the local oscillation frequency is feedback-controlled by the count data.

This example will be briefly described with reference to FIGS. 12 and 13.

In FIG. 12, (10) is a BS antenna. Reference numeral (11) is an antenna section, which is, for example, a parabolic antenna or a plane antenna. (12) is the first converter. The first converter (12) receives the 12 GHz band satellite broadcast signal (FM).
Video signal) and the output of the internal oscillation circuit (13) are mixed circuit (14)
The FM video signal (first intermediate frequency signal) (first IF signal) in the band of about 1 GHz mixed in is output. The output fluctuation is
It is allowed up to ± 1.5MHz. This fluctuation is due to AFC
It is corrected by the operation.

(16) is a BS tuner. Reference numeral (18) is a second down converter, which converts the first IF signal into a second IF signal of, for example, 402.78 MHz, which is advantageous for multichannelization. (20) and (24) are automatic gain control amplifier circuits. (22) is a mixing circuit.
(26) is a variable oscillating circuit, (28) is a pre-scaler for dividing by 1/2, and (30) is a circuit for PLL loop. This PLL
The loop circuit (30) forms a PLL loop together with the circuits (26) and (28). Microcomputer for tuning (microcomputer) (3
In 2), the frequency division ratio of the program divider built into the PLL loop circuit (30) is switched to switch the receiving channel and also perform AFC for fine tuning. A general PLL loop is disclosed in JP-A-60-7753.
No. 3 (HO4B1 / 16) and the like, which are well known, will not be described.

(34) is an FM demodulation block. Reference numeral (36) is a second IF filter, (38) is an amplifier, and (40) is a PLL type FM demodulation circuit. (42) is an AGC detection circuit that creates an AGC voltage. (44) is an ECL 1/256 divider circuit.

(46) is a counter circuit that directly counts the output signal of the 1/256 divider circuit. The counter circuit (46) controls the reset and count operation periods by the microcomputer (32) and outputs the count data to the microcomputer (32).

(48) is a voice DPSK signal demodulation circuit. (50) is PCM
It is a decoder. This PCM decoder is, for example, TM4218N manufactured by Toshiba Corp., an audio PC of NTSC broadcasting.
Terminal (5) that outputs a signal (N / SYNC) when receiving an M signal
0a). Reference numeral (52) is an audio output circuit which performs digital-analog conversion and which includes a low-pass filter.
Reference numeral (54) is an output encoder of the digital device. (56) is a buffer amplifier. (58) is a low-pass filter / de-emphasis circuit, (60) is a dispersal circuit for removing a triangular wave, and (62) is an output amplifier. (64) is an output processing block. (66) is an output terminal group. (66a) (66b) are audio output terminals, (66c) (66d) are output terminals for optical cable connector for DAT, (66e) are output terminals for bit stream, (66f) are output terminals for pay broadcast decoder, ( 66g) is a video output terminal.

(68) is a sync separation circuit, which extracts the vertical sync signal pulse (V _D ) and outputs it to the microcomputer (32).

The above operation will be described.

This BS tuner (16) has a counter circuit (46) for a predetermined period.
, And input this count data to the microcomputer (32). The microcomputer (32) knows the frequency shift of the second IF signal by comparing this data with the reference data. Then, the microcomputer (32) changes the frequency division ratio of the program divider of the PLL circuit (30) to correct this deviation.

Then, the predetermined period to be counted is determined by the microcomputer (32) from the vertical synchronizing signal (V _D ). This predetermined period (gat
e) is shown in FIG.

FIG. 13A shows the output of the PLL type FM demodulation circuit (40),
(B) is the output of the sync separation circuit (68), (c) is the microcomputer (3
2) Reset signal (C) of the counter circuit (46) output from
l) and (d) are counter operation period designation signals (gate) of the counter circuit (46) output from the microcomputer (32).

The operation will be described with reference to FIG.

The vertical sync signal pulse (V _D ) from the sync separation circuit (68)
When input to the microcomputer (32), the microcomputer (32) outputs a reset signal (Cl). Then, the vertical synchronization blanking period (1024 μsec) (A) outputs a gate signal to allow the counting operation of the counter circuit (46). And period (B)
1) again after pausing the output of this gate signal
A gate signal (gate) is output for (C) during 024 μsec. Then, the microcomputer (32) reads the count data of the counter circuit (46) in the subsequent period (D). Then, in order to remove the influence of the triangular wave which is the energy diffusion signal, the microcomputer (32) outputs four count results of two frame periods (note that the number of inputs is four, but the count period is 4 × 2 = 8).
The value obtained by adding 4) to the reference data value at the time of receiving the NTSC broadcast is compared to detect the “deviation” of the frequency of the second IF signal, and the value of the PLL circuit (30) The AFC operation is performed by changing the circumference ratio.

The counter circuit (46) is operated during the video period as follows.
This is because, in the case of NTSC broadcasting, the average value AFC for transmission is adopted as the main carrier frequency control method. Further, the value of the period (B) in FIG. 13 (d) is changed, for example, to 6 ms, 4 ms, 6 ms, and 8 ms for each field, and the value of the frequency of each part of the screen is detected to determine the brightness. This prevents fluctuations due to variations in size.

In this way, the microcomputer (32)
The average value AFC is performed by controlling the PLL circuit (30). When controlling the PLL circuit (30) for each field, the count results of the past four times are averaged,
The AFC operation may be performed by comparing this with reference data.

Also, in the above example, 4 of the 4 field (2 frame) period
I averaged the results of the two counts, which were 4, 6, 8
It may be a frame period.

In addition, when the BS tuner also receives a satellite broadcast (generally called a high-definition broadcast) obtained by FM-modulating a MUSE signal (a signal obtained by converting a high-definition TV signal developed by NHK by a band technology), MUSE The number of field count values to be averaged in accordance with the period of the signal spread signal is switched from that in the case of the NTSC system. Also, the period for operating the counter circuit (46) is naturally switched to the clamp level period of the MUSE signal in the case of MUSE reception. Regarding the MUSE signal, the magazine "Nikkei Electronics November 2, 1987, published by Nikkei McGraw-Hill Inc.
Japanese Broadcasting Corporation Yuichi Ninomiya "Transmission system for high-definition broadcasting using satellites"
USE "is a well known technique.

However, as shown in FIG. 14, the clamp level period of the MUSE signal is the retrace line period of the NTSC broadcast (1024 μ
This is much shorter than (seconds) (23 μs), and the period for operating the counter circuit is further shorter (15 to 17 μs). Therefore, it is impossible to accurately perform the AFC operation by counting during this period. In other words, when receiving MUSE broadcasting,
The detection accuracy of the deviation "deviation" of the second IF signal per count of the counter circuit is about 17 MHz, which is very high.
It cannot perform C operation.

Therefore, the second IF signal may be directly counted by the counter circuit (46) without using the 1/256 frequency divider (44). But 40
A high-speed counter circuit that counts the 2.78 MHz second IF signal is difficult to make at present and is very expensive.

Further, even if the second IF signal is a signal obtained by dividing the second IF signal by an ECL frequency divider circuit into 1/2 to 1/4, it is difficult to realize counting. Further, if the frequency is further divided, the detection accuracy per count becomes too coarse, which causes a practical problem. This is because the frequency variation of the second IF signal is also divided at the same time. In addition, at the time of 1/2,
If it can count, the detection accuracy per count at that time is about 130 KHz, and at 1/4, it is about 260 KHz.

Therefore, it is possible to perform normal keyed AFC at the time of receiving MUSE. This example is shown in FIG. (70) is M
It is a USE decoder. The decoder (70) outputs a high-definition television signal and also outputs a signal (keyed AFC pulse signal) (P) indicating the clamp level signal period only when the MUSE signal is input.

(72) is a MUSE signal buffer, (72a) is an output terminal, (7
4) is a keyed AFC pulse signal input terminal (high-definition broadcasting compatible terminal), (76) is a sample and hold circuit that samples the clamp level signal, and (78) is A / that converts the value of the sample and hold circuit (76) to a digital value. It is a D converter. The microcomputer (32) receives this A / D when receiving MUSE.
The value from the converter (78) and the reference data for MUSE reception are compared to detect "deviation", and the PLL circuit (30) is controlled to perform the AFC operation.

However, such a circuit samples and holds an analog signal as described above, and the B
It was impossible to realize the high precision and high responsiveness of the S tuner.

(C) Problems to be Solved by the Invention By the way, as described above, the average value AFC is used for transmitting the NTSC signal. According to this average value AFC, as shown in FIG. 16, the corresponding brightness level of the center frequency of the carrier wave fluctuates according to the level of the video signal, so in the conventional example, the AFC operation follows this. In order not to accidentally follow the fluctuation of the video signal level for a short period of time and cause a malfunction,
Both the video period and the vertical synchronization period (AC in FIG. 13 (d)) were used as the counting period.

However, it has been found that in the NTSC transmission of satellite broadcasting, the time constant of the average value AFC is small, and the level fluctuation of the video signal is quickly followed.

The present invention is an AF of a BS tuner adapted for such broadcasting.
It proposes one of the C methods.

For example, in order to properly correspond to the average value AFC, the counter may be operated for one cycle (1/15 seconds) of the energy diffusion signal, but the counter for performing such counting becomes large-scale.

The present invention provides an AFC method that does not have such a problem.

(D) Means for Solving the Problems The present invention mixes the FM video signal converted to the first intermediate frequency with the oscillation signal from the variable oscillating circuit to change the FM video signal to the second intermediate frequency. A satellite for controlling the oscillation frequency of the variable oscillation circuit so as to correct the frequency deviation by converting the frequency of the second intermediate frequency signal to a frequency In the AFC method of the broadcast receiving apparatus, a count period for demodulating the FM video signal of the second intermediate frequency to detect a synchronization component and directly counting by the detection output.
By controlling (B) and (C), the count period is excluded from the vertical blanking period (VB), and the entire video signal period (Y + H) including the horizontal blanking period is divided into n regions. It is characterized in that the value of the frequency shift is detected based on the result of the plurality of counts detected during at least one cycle period of the energy diffusion signal by moving over.

(E) Action The present invention uses the relationship between the video signal period (Y), the horizontal blanking period (H), and the vertical blanking period (VB) shown in FIG. 2 to determine the ratio of the entire screen to the video period (Y). Note that (77%) is similar to the ratio (83%) of the video signal period (Y) and the period (Y + H) in which the video signal period and the horizontal blanking period are combined, and this period (Y + C) Is set as an area for counting, and the counting periods (A) and (C) in this area are set at random. Then, based on this count result, in order to prevent the local fluctuation of the video signal level and the fluctuation due to the energy spread signal, by comparing the average of a plurality of count results of at least one cycle period of the energy spread signal with the reference data, Detects frequency shift.

(F) Embodiment The operation of the present invention will be described with reference to FIG. this is,
FIG. 14 is a diagram showing count periods (A) and (C) at the time of receiving an NTSC signal, similar to FIG. 13 of the conventional example.

That is, the microcomputer detects the timing by the vertical synchronization signal (V _D ) and divides the video signal period (Y + H) including the horizontal blanking period into two equal parts except the vertical blanking period. And
Periods (B ₁ ) and (B ₂ ) are randomly set within a predetermined range so that the count periods (A) and (C) move randomly within the bisected area.

Then, the calculation for AFC is performed from the four count data of the eight periods detected and input in 1/15 seconds.

A BS tuner according to an embodiment of the present invention will be described with reference to FIG. The BS tuner also has a circuit for receiving a MUSE signal.

(80) is a down converter circuit for AFC, 402.78MH
The second IF signal of z is converted to the third IF signal of 24.78 MHz. (82) is an amplifier, (84) is a highly stable oscillation circuit that oscillates at 378 MHz, (86) is a mixing circuit, and (88) is a bandpass amplifier for a 24.78 MHz signal. (90) is a 1/16 divider circuit. (SW
1) is a changeover switch. This switch (SW
1) is connected to the N side when receiving NTSC broadcast.

(92) is a reception mode discrimination circuit, which is used for synchronizing signal and keyed A
Depending on the FC pulse signal, "When receiving NTSC broadcast?"
It determines whether the USE broadcast is received or not, and outputs it to the microcomputer (32), and also switches (SW1) the MU.
When SE is received, it is switched to the M side, and when NTSC is received, it is switched to the N side.

(94) is a counter control pulse generation circuit for NTSC reception, which inputs a synchronizing signal and receives the gate signal (gete) of FIG.
It outputs a clear signal (Cl) and a vertical sync signal (V _D ).

(96) is a counter control pulse generation circuit for MUSE reception, which inputs a keyed AFC pulse (P) to output a second gate signal (gate2), a second clear (Cl2) and a counter data read control signal (V _D Create 2). Then, the selection output circuit (98) selects the signals from the two pulse generation circuits (94) and (96) according to the reception mode and outputs them to the counter circuit (46) and the microcomputer (32).

(100) is an AFC prohibition circuit, and is a switch (SW2) when receiving MUSE and when the AGC voltage is low (weak electric field).
Open to block the input of the read control signal (V _D 2) and prohibit the AFC operation. This is because when receiving a weak electric field,
This is because the reliability of AFC operation is reduced. In addition, NTS
At the time of receiving the C broadcast, even if the second IF signal is a little missing, the AFC does not largely malfunction because the sample time is long.

The above operation will be described with reference to FIG. 1, FIG. 3, and FIG.

When the user selects the receiving channel, the microcomputer (32) outputs the standard division ratio data for receiving the channel.
Output to the LL circuit (30). Then, the frequency division ratio data is received for a while.

Then, after this, the reception discrimination circuit (92) outputs N by the synchronization signal.
If it is determined that the TSC reception mode is set, the selection output circuit (9
8) outputs a clear signal (Cl) [C in FIG. 1] and a gate signal [gate] [d in FIG. 1] to the counter circuit (46) and sends a vertical synchronizing signal (V _D ) to the microcomputer (32). Output. Also, NTS
The microcomputer 32 is also notified that the C reception mode is in effect, and the microcomputer starts the AFC operation for NTSC. The switch (SW1) is connected to the N side.

That is, the microcomputer (32) reads the count data after the count of the counter circuit (46) is finished, performs averaging over four fields and compares it with the reference data for NTSC reception. Then, the "deviation" of the second IF signal is detected, and the frequency division ratio of the PLL circuit (30) is varied to perform the AFC operation as described above.

Also, after tuning, the signal output from the terminal (72a) is input to a MUSE decoder (not shown), and when this MUSE decoder determines that it is a MUSE signal, it is keyed from the terminal (74) of this BS tuner (16). The AFC pulse signal (P) is input. Then, the reception determination circuit (92) determines that it is in the MUSE reception mode based on the keyed AFC pulse signal (P). The switch (SW1) is connected to the M side,
The microcomputer (32) starts the AFC operation for MUSE.

The selection output circuit (98) outputs the second gate signal (gate2) second clear signal (Cl2) control signal (V _D 2) created by the MUSE counter control pulse creation circuit (96).

This signal is shown in FIG. FIG. 4 (a) shows a triangular wave valuable for the MUSE signal. (B) shows a keyed AFC pulse signal output from the MUSE decoder. (C) shows the second clear signal (Cl2), and (d) shows the second gate signal (gate2). (E) shows the control signal (V _D 2).

As can be seen from FIG. 4, the keyed AFC pulse signal output period, which is the clamp level signal period, is the center potential of the triangular wave. Therefore, when the MUSE signal is received, the count data value of the counter circuit (46) does not change for each field due to the influence of the triangular wave. Therefore, even if the count data for one time is logically A without influence of the triangular wave.
Can perform FC operation. However, in reality, due to the deviation at the time of superimposing the triangular wave and the MUSE signal, the detection delay of the keyed AFC pulse signal, etc., it is still necessary to average the two data sampled during at least one week (one frame). Don't

In this conventional example, in order to improve reliability, the AFC operation is performed by comparing the average of four data in the two-frame period with the MUSE receiving reference data. Furthermore, out of these four data, too big,
The microcomputer (32) excludes the distant count data and adopts a safety measure to average them. Also, count data that is too large and far from the reference data may be excluded, and the count data of the past four times may be averaged.

FIG. 5 shows another example. This FIG. 5 is of a type in which a microcomputer (32) creates a clear signal (Cl) and a gate signal (gate) at the time of NTSC reception as in the conventional example of FIG.
The count input to the counter circuit (46) at the time of NTSC reception is also the 1/256 divided signal of the second IF signal.

When the vertical synchronizing signal (V _D ) is input from the sync separation circuit (68), the microcomputer (32) determines that the NTSC broadcast is being received and performs the ASC operation for NTSC. Also, Keyed A
When the FC pulse signal (P) is input, it is determined that the MUSE broadcast is being received, and the AFC operation for MUSE is performed.
When neither signal is input, the AFC operation is stopped. That is, the frequency division ratio of the PLL circuit (30) is not changed and the frequency division ratio is held at the previous value.

Reference numeral (93) is a MUSE broadcast reception determination circuit, which opens the switch (SW3) during MUSE broadcast to prevent erroneous input of the vertical synchronization signal pulse (V _D ). Further, the discrimination circuit (93) switches the switches (SW6) (SW7) (SW1) which are always connected to the N side to the M side during MUSE broadcasting.

(SW4) is a normally closed switch, (SW5) is a normally closed switch, and (102) is a gate pulse generating circuit. This gate pulse generation circuit (102) is a keyed AFC of FIG. 6 (b).
Each time the pulse signal (P) is input, it will be approximately the same as in FIG. 6 (c).
The delayed pulse signal (G) delayed by 1/60 second is output. Then, during the period (G) of FIG. 6 (c), the normally closed switch (S
W4) is opened. Further, the normally open switch (SW5) is closed during the period (G) of FIG. 6 (c). That is, from this switch (SW4) (SW5), the regular keyed AFC pulse signal (P) input at an interval of 60 Hz passes, and the noise pulse is removed.

(97) is the second clear signal (Cl2), the second gate signal (gat
It is a counter control signal creation circuit for MUSE that creates e2). If the counter operation period of the counter circuit (46) is not set accurately, it may cause malfunction of the AFC operation.
In this embodiment, the second gate signal (gate2) period is set by the output of the 10 MHz oscillator circuit (104).

Reference numeral (104) is an oscillation circuit of 10 MHz, which outputs the clock signal of FIG. 7 (b). (106) is a key pulse synchronizing circuit. The key pulse synchronizing circuit (106) is provided with the second clear signal (Cl2) of FIG. 7 (c) at the timing when the clock signal is input after the keyed AFC pulse signal (P) of FIG. 7 (a) is input. Is output. Reference numeral (108) is a counter that is cleared by the second clear signal (Cl2). (110) is a gate signal generating circuit, which is set by the second clear signal (Cl2) and is set to the second of FIG. 7 (d).
Raise the gate signal (gate2). Gate signal generation circuit
(110) outputs the signal (k) of FIG. 7 (e) which permits the operation of the counter (108).

Accordingly, the counter 108 starts counting clock signals. When the counter 108 counts 160 clock signals, it outputs the reset signal (R) of FIG. 7 (f). By this reset signal (R), the gate signal generation circuit (110) causes the second gate signal (gate2) to fall. Further, the gate signal generating circuit (110) sets the signal (k) to the low level to prohibit the operation of the counter (108).

(85) is a highly stable oscillation circuit for producing the third IF signal. (1
12) is a 378MHz oscillation circuit, (114) is a 4MHz crystal (accuracy
It is a circuit for a PLL that incorporates an ECL prescaler equipped with 10 ⁻⁵ ), and the frequency division ratio is fixed. In this way, PL
By forming an L loop and controlling the oscillator circuit (112), the oscillation frequency fluctuation was suppressed to within ± 37.8 KHz.

It should be noted that this BS tuner may also take measures against weak electric field reception of MUSE broadcasting. For example, similarly to the previous example, the AFC operation may be stopped by detecting the weak electric field reception time by the AGC signal. Further, as the electric field becomes weaker, the averaging period may be set longer (for example, 8 frame periods). In addition, the lamp may be turned on during the input period of the keyed AFC pulse signal to notify that it is in the MUSE broadcast receiving mode. Also, the synchronization signal or P in FIG.
By using the output of the terminal (50a) of the CM decoder (50), a lamp may be turned on to notify that the NTSC broadcast is being received.

Also, a MUSE decoder may be incorporated.

Further, a TV tuner for receiving UHF, VHF, CATV may be incorporated. At this time, the oscillator circuit (84) (1
The oscillation frequency of 12) is set to a frequency between channels so that it does not overlap the TV channel transmission band.

FIG. 8 shows another example. The same parts as those in FIG. 5 are designated by the same reference numerals, and the duplicated description will be omitted. In Figure 8, (1
30) is a gate array IC. So in this example,
The circuit is integrated. And this gate array (13
0) is to detect the presence or absence of the third IF and stop the AFC operation (hold the previous value) when the third IF is not present.

In other words, when the received signal is missing in the short term or the down converter (80) fails, the AFC malfunctions.
This gate array IC (130) employs a safety measure for stopping the AFC operation.

In FIG. 8, reference numeral (93 ') is a MUSE broadcast reception time determination circuit, which indicates that the MUSE reception is in progress by the tuning microcomputer (3
Notify 2 '). Further, the discrimination circuit (93 ') switches the switch (SW3'). That is, the switch (SW3 ′) normally connected to the N side is switched to the M side when receiving MUSE, and the keyed AFC pulse (pseudo second gate signal) (gate2 ′) shaped by the counter control signal generating circuit (97) is output. Input to the tuning microcomputer (32 ').

The tuning microcomputer (32 ') recognizes from the signal from the discriminating circuit (93') whether it is an NTSC reception or a MUSE reception, and executes the program for that mode. Then, the vertical synchronizing signal from the switch (SW3 ') or the pseudo second
Timing is set by the fall of the gate signal (gate2 ') and the data of the counter circuit (46) is fetched.

Reference numeral (120) is a D flip-flop showing the characteristics of this example. This D flip-flop (120) clock terminal (C
The third IF signal is supplied to K). That is, the D flip-flop (120) is connected to the second gate signal (gate) of FIG.
Pseudo second gate signal obtained by delaying 2) by the period of the third IF signal
Output (gate2 ′). If the third IF signal disappears, the D flip-flop (120) holds the value (usually 0) before the third IF signal disappears. Therefore, the channel selection microcomputer (32 ') is not provided with the pseudo second gate signal (gate2'), the channel selection microcomputer (32 ') does not capture data, and the AFC operation is substantially stopped. To do.

In other words, in FIG. 8, the second created in the same manner as in FIG.
The gate signal (gate2) is input to the D terminal of the D flip-flop (120). The third IF signal is a D flip-flop (12
When the third IF signal input to the clock terminal (CK) of (0) disappears, a normal output (pseudo second gate signal, gate) is output from the output terminal (Q) of the D flip-flop (120).
2 ') disappears. Then, this pseudo second gate signal (ga
Since the falling edge of te2 ') is used as a pulse for the data reading timing by the channel selection microcomputer (32'), the channel selection microcomputer (32 ') stops reading the data.

Therefore, the value of the PLL circuit (30) by the AFC operation when the third IF signal disappears is held.

As described above, in the example of FIG. 8, when the third IF signal is lost, the pseudo second gate signal (gate2 ') is selected by the microcomputer (32').
To stop the AFC operation.

In the above example, the D flip-flop (120) is provided between the gate signal generating circuit (110) and the switch (SW7), but this is the switch (SW7) and the switch (SW3 ').
It may be provided between and.

Also, in this example, one D flip-flop (120) is used as the third
A malfunction was prevented when the IF signal was lost. In addition to this, a third IF signal loss state detection circuit and a stop circuit that stops the AFC operation when the tuning microcomputer (32 ') receives MUSE by the output of this detection circuit And may be separately provided and implemented. By doing so, the reliability is improved. Also, the third
It can also be applied to the circuit shown in the figure, and NTS can be used even when receiving NTSC.
The C AFC operation may be stopped (holding the previous value).

In the above example, the AFC down converter circuit (80)
The frequency of the third IF signal output from the normal VHF built in this BS tuner or placed close to
In order not to adversely affect the UHF and CATV tuners,
For example, it is set as shown in FIG.

TV for receiving ordinary Japanese television broadcasting (terrestrial broadcasting)
, The frequency of the audio intermediate frequency signal SIF is 54.2.
The frequency of the video intermediate frequency signal VIF of 5 MHz is set to 58.75 MHz. When the frequency of the third IF signal (IF) output from the AFC down converter circuit (80) of the BS tuner is set to 24.78 MHz, the frequency of the second harmonic (IF2) of the third IF signal is 49.56 MHz. Become. In this way, the frequency of the third IF signal is set so that the frequency of the second harmonic of the third IF signal does not overlap with the frequencies of the audio intermediate frequency signal and the video intermediate frequency signal. In addition, the frequency of the third harmonic (IF3) of the third IF signal does not overlap with the frequencies of the audio intermediate frequency signal (SIF) and the video intermediate frequency signal (VIF), so that the third I
The frequency of the F signal is set.

Further, as shown in FIG. 10, the oscillation frequencies of the oscillation circuits (84) and (112) included in the AFC down converter circuit (80) are VHF band and U frequency in Japanese television broadcasting.
There is a free space (SR) between the HF band and the HF band. Therefore, the oscillation signal (O) output from the oscillation circuits (84) and (112)
SC) frequency is set between 222MHz and 470MHz. In this case, the frequency of the oscillation signal (OSC) is adjusted so that the second harmonic component (OSC2) of the oscillation signal (OSC) does not overlap with the frequencies of the video carrier (p) and the audio carrier (s) in any channel. Is set. For example, the frequency of the oscillation signal (OSC) is 378MHz
When set to, the frequency of the second harmonic component (OSC2) is exactly in the middle of the frequency of the video carrier (p) of 60 channels and the frequency of the audio carrier (s).

If a channel is assigned to an empty area between the VHF band and the UHF band as shown in FIG.
The frequencies of the oscillation signals output from (84) and (112) are set so as not to overlap the frequencies of the video carrier (p) and the audio carrier (s) in those channels. In FIG. 11, the frequency of the oscillation signal is set to 378 MHz between the frequency 377.75 MHz of the audio carrier (s) and the frequency 379.25 MHz of the video carrier (p). Also, this 378 MHz is just the frequency at the boundary between channels.

As described above, according to the above example, the second IF signal is converted into the third IF signal by the frequency mixing method. for that reason,
The fluctuation of the second IF signal is not divided. Therefore, the frequency fluctuation of the second IF signal can be detected with high accuracy, and high-precision AFC operation can be performed.

(G) Effect of the Invention According to the present invention, the AFC operation can be favorably performed in the channel selection device when the NTSC signal transmitted with the average value AFC is received.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention. FIG. 2 is a diagram showing a video period and a blanking period. FIG. 3 is a diagram showing a first embodiment of the present invention. FIG. 4 is a diagram for explaining this. FIG. 5 is a diagram showing a second embodiment. FIG. 6 and FIG. 7 are diagrams for explaining this. FIG. 8 is a diagram showing a third embodiment. FIG. 9, FIG. 10, and FIG. 11 are diagrams for explaining the operation. FIG. 12, FIG. 13, FIG. 14, FIG. 15, and FIG. 16 are views for explaining a conventional example.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-1-196912 (JP, A) JP-A-58-111522 (JP, A) JP-B-60-19846 (JP, B2)

Claims (1)

[Claims] 1. An FM video signal converted to a first intermediate frequency and an oscillation signal from a variable oscillating circuit are mixed to convert the FM video signal to a second intermediate frequency, and the second intermediate frequency. In the AFC method of the satellite broadcast receiving apparatus, which counts the signals, obtains a value of frequency deviation by comparing with a predetermined value, and controls the oscillation frequency of the variable oscillation circuit to correct the frequency deviation. The FM video signal of the intermediate frequency is demodulated to detect the synchronization component, and the count output (B) and (C) for counting are controlled by this detection output, and this count period is excluded except the vertical blanking period (VB). , And a video signal period including a horizontal blanking period (Y + H)
The satellite is characterized in that the whole area of the frequency shift is moved over the whole area divided into n areas, and the value of the frequency shift is detected based on the result of the plurality of counts detected at least in one cycle period of the energy spread signal. AFC method for broadcast receiver.