JPH0646412B2 - Data Flow Processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data flow processor in which a memory unit and an operation unit are connected by a pipeline bus and the operation order is controlled by a data flow method.

[Conventional technology]

Conventionally, there is a μPD7281 manufactured by NEC Corporation as a data flow processor.

The μPD7281 has a structure as shown in FIG. The token, which is a unit of data input to the device from the external bus, has a data value, a link table address for referring to the link table 92 after input, and a module number indicating the device to which the token is to be processed. ing.
The token input unit 91 inputs the token internally when the module number of the token passing through the external bus matches the device number, and otherwise outputs the token directly from the external bus through the token output unit 97. The entered token refers to the link table 92 by the table address of the token, and then the function table 93
Is obtained and the link table address for referring to the link table 92 next time is obtained, and then sent to the function table 93.

The token refers to the function table address in the function table 93. Therefore, the management information of the data memory 94 is referred to / updated, and at the same time, the processing code indicating the processing content in the processing unit 96 and the access address of the data memory 94 are obtained and sent to the data memory 94. Waits for operands to the other side of the term operation or reads the constant for constant operation. The queue memory 95 is a memory for temporarily holding the token when the processing unit 96 is processing the previous token and cannot input the next token, and when the processing unit 96 is not busy, the token is processed from the queue memory 95. It is sent to the unit 96 and, depending on the processing code, performs one of the operations such as arithmetic operation, logical operation, shift, comparison, bit inversion, priority encoding, shunting, numerical value generation, copy, and operation using internal register. receive. If the processing code of the token indicates output, the token is sent from the queue memory 95 by the token output unit 97, transformed into the form of the input token, and then output to the external bus. Processing unit 96
The token processed in (4) is sent to the link table 92, and again referred to by the link table address. In the same manner, it goes around the internal ring bus until the output instruction is executed, and receives the necessary processing for the data value.

[Problems to be solved by the invention]

Consider the case where the above-described data flow processor performs so-called convolution processing in which a certain coefficient is applied to each of a plurality of data in the external memory and the sum of their products is calculated. In the conventional data flow processor, there is only one arithmetic unit, and when the token goes around the inner ring and enters the processing unit, only one binary operation between the two data of the token can be performed. In the case of volume, N tokens must go around the inner ring and flow into the processing unit N times in order to perform multiplication of N data sets, and (N-1) times in order to perform addition of the result. However, there is a problem in that the processing time becomes long because the addition is performed serially in time. In the μPD7281, although a register is provided in the processing unit in order to speed up the addition of continuous data among the above problems, this cannot speed up the multiplication as well.

In addition, it generally takes time to input data from external memory in the form of token in the data flow processor, so it is desirable that the number of memory access is as small as possible.For this reason, data once read from external memory is held in internal memory and The method is referred to by shifting one by one as needed when performing the convolution of times. However, if this is done with a conventional data flow processor, both the data to be calculated and the coefficient are placed in the data memory, so in order to refer to them and operate in the processing unit, the token used for the operation uses an internal ring. There has been a problem that the processing speed is slowed down due to the necessity of making two rounds.

It is an object of the present invention to provide a data flow processor capable of performing such convolution processing only by the N tokens to be processed making one round in the inner ring, and realizing high-speed processing. It is in.

[Means for solving problems]

The present invention is a data flow processor that performs processing by flowing a token, which is a unit of data, to an internal ring bus, a link table that stores destination addresses of tokens, and an operand that controls operand fetch. A fetch table, a data memory that temporarily stores operand data used for operations, a function table that stores instruction code and coefficient data, a buffer queue that temporarily holds tokens, a processing unit that performs data processing on tokens, and the processing described above. A token output unit for sending a token to an external bus from the unit; and a token input unit for inputting a token from the external bus and sending it to the link table or the token output unit, the processing unit: A token generator that copies tokens, an arithmetic calculator that does not have an internal state, that performs comparison operations, etc., a register processor that has registers inside and that performs operations, and shaping of operation result tokens. And a token shaping unit for transmitting to the link table or the token output unit, the link table, the operand fetch table, the data memory, the function table, the buffer queue, and the processing unit , Which are sequentially connected to form the ring bus.

[Action]

When convolution Σw (i) × x (k) for N data is performed using the present invention, N coefficients w (i) (i = 0, 1, ...
.., N-1) is set in a portion that holds the state of the function table, and N pieces of data x (k) (k = 0, 1, ..., N-1) to be processed. ) Is a data memory.

When performing an operation, the token generation unit generates a set of talks, which is N consecutive tokens. Each token in the set token has the same link table address and an organization identifier for identifying each other, and is controlled so as to always flow continuously in the data flow processor.

These tokens go around the inner ring to obtain a data memory address for sequentially accessing the data memory in the operand fetch table, and then the data memory uses it to refer to the processing data x (k). Further, these tokens fetch the previously set coefficient w (i) corresponding to the position in the set of tokens in the function table, so that the two data are input to the processing unit. In the processing unit, these multiplications w are performed in the arithmetic operation section.
(I) × x (k) is performed, and the register processing unit receives the results one after another and adds them to the internal register. Since the group tokens flow continuously, multiple convolutions do not mix and produce incorrect results.The last token of the group token causes the register value at that time to be output as a result and the register to be cleared. 1
Finish two convolutions.

When performing convolution one after another while shifting the processing target one by one for continuous data, input the next required data x (k) from the external memory, set it in the data memory, and then access the data memory. The next set x (k) (k = 1, 2,
The same coefficient w (i = 0, 1, ...
, N-1) can be used for convolution.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an internal block diagram showing a configuration of a data flow processor 1 according to an embodiment of the present invention. The data flow processor 1 includes a token input unit 10, a link table 11, an operand fetch table 12, and a data memory.
13, a function table 14, a buffer queue 15, a processing unit 16, and a talk output unit 17. The link table 11, the operand fetch table 12, the data memory 13, the function table 14, the buffer queue 15, and the processing unit 16 are connected in a ring by a pipeline bus in this order as shown in the figure, and the token is It is transferred on the ring bus in synchronization with the pipeline lock in the data flow processor. Further, the processing unit 16 includes a talk generation unit 2
0, arithmetic calculation unit 21, register processing unit 22, token shaping unit 2
It consists of three.

FIG. 2 is an overall configuration diagram of an example of a data processing device using the embodiment of FIG. In this data processing device,
A plurality of data flow processors 1 and 2 and one memory interface circuit 3 are connected by an external bus 5, and the external bus 5 is connected to the external memory 4 via the memory interface circuit 3. The token is transferred asynchronously on the external bus 5 by the handshake method.

FIG. 3 shows the format of a token which is a unit of data. The token 60 on the external bus 5 includes a module number 61, an organization identifier 62, a link table address 63, and data 64.

The tokens used in this embodiment can be processed as a unit with a set token composed of one or more tokens. The group token always flows continuously in the data processing device, and the same module number is used.
It has the same link table address 63 as 61.

The organization identifier 62 is used to identify the token in a set token, and distinguishes "0" when the token constitutes a set token by itself, and distinguishes each other in a set token composed of a plurality of tokens. They can have different values if needed. However, the last token in the group token also has "0" as an organization identifier.

Further, 70, 75, 80, 85 are respectively the link table 11 to the operand fetch table 12, the operand fetch table 12 to the data memory 13, the data memory 13 to the function table 14, and the function table.
14 to buffer queue 15 and processing unit
The format of the token when input to 16 is shown.

The token input unit 10 fetches only tokens input from the preceding data flow processor or memory interface circuit, whose module number 61 is equal to the number given to the data flow processor, to the link table 11. The tokens are sent in synchronization with the pipeline cycle, and the other tokens are sent as they are to the token output unit 17 as passing tokens. However, link table 11
Alternatively, when the token output unit 17 is in the busy state during the processing of the group token as described below, the token is not transmitted, and the handshake acknowledge signal is not returned to the preceding data flow processor or memory interface circuit. Stop typing.

The link table 11 inputs a token from the processing unit 16 or the token input unit 10, but when both requests are made at the same time, the input from the token input unit 10 is usually prioritized. However, the processing unit 16 gives priority to it while the continuous token is being generated by the copy operation, and if the organization identifier of the token that is input is not “0” regardless of which token is input, the token is selected from multiple tokens. Since it is a token other than the last one of the group tokens and the rest of the group tokens are input continuously, inform the person who is not the source of those tokens that they are busy and input. By stopping, the entire tokens in the set are preferentially input continuously. This guarantees the continuity of the group token.

The link table 11 is referred to by the link table address 63 of the token 60 input from the processing unit 16 or the token input unit 10, and the token is used for referring to the operand fetch table address 71, the function table address 72 and the next link table 11. The link table address 73 is obtained and sent to the operand fetch table 12. However, for the function table address generation, the data obtained by referring to the link table and the organization identifier of the token are used.

The operand fetch table 12 is referred to by the link table 11 of the input token 70 or the read operand fetch table address 71, and the instruction code for reading / writing the data memory 13 at that address and controlling the binary queue control of data is referred to. Refers to and updates the information for state management. This causes the token to receive the data memory address 77 and the data memory code 76 indicating the operation in the data memory.

The data memory 13 is accessed by the data memory address 77 of the input token 75, and is used for waiting for the token having the binary operation data and the token having the data at the time of the write token output and the address as the need arises. Used as a queue or as a memory for storing constants for constant calculation. For example, the data input from the external memory to the data flow processor is held by being written in consecutive addresses in the order of the data memory, and when the arithmetic processing is performed thereafter, the data is read from the data memory by the data memory read token, and the first operand 81 Can be used for calculation in the processing unit 16 by adding to the token.

In the function table 14, the input token 80
The internal table is accessed by the function table address 72, and the flow is controlled by changing the link table address part of the token that flows as necessary while maintaining the internal state, and at the same time, the processing content of the processing unit 16 , That is, the token generation code 86, the arithmetic operation code 87, the register processing code 88, and the token shaping code 89 are added to the token. Further, instead of the flow control operation described above, the data in the internal state holding unit is added to the token as the second operand 82, and the data of the first operand 81 that was held when the function table 14 was input is also input to the processing unit 16. be able to.

The buffer queue 15 is a memory for temporarily holding the token before inputting the token to the processing unit 16, and the token generation unit of the processing unit 16.
20 stops the token input and the output to the processing unit 16 during the token copy operation.

As described above, the processing unit 16 is configured by serially connecting the four calculation units of the token generation unit 20, the arithmetic calculation unit 21, the register processing unit 22, and the token shaping unit 23, and the input tokens are It acts like a pipeline on this when passing through in sequence. The instruction codes 86, 87, 8 previously read in the function table 14
Reference numerals 8 and 89 are codes in which codes corresponding to respective parts of these arithmetic units are connected, and the respective arithmetic units operate independently according to these.

According to the token generation code 86, the token generation unit 20
Performs copy operation for one token input and outputs multiple tokens. At this time, the link table address of the input token can be used as it is as the link table address of the token to be copied, and a plurality of tokens that are continuously output by the copy operation form a group token as they are. Can also be operated. It is also possible to generate multiple tokens whose data forms an arithmetic progression.

The arithmetic calculation unit 21 performs a binary operation on the data held at the time of passing through the link table 11 and the data read from the data memory 13, or the binary operation of the data read from the data memory 13 and the data read from the function table 14. Arithmetic operation code
Execute according to 87 with no internal state. The operations include arithmetic operations including multiplication, logical operations, shifts, comparisons, bit operations and the like.

The register processing unit 22 has a register inside, and can operate the result data of the arithmetic calculation unit 21 on the register according to the register processing code 88. As an example, the sum of vector data can be obtained by adding data to a register, and the register can be cleared.

The token shaping unit 23 selects one of the result output of the arithmetic calculation unit 21 and the register contents of the register processing unit 22 as the result data of the processing unit 16 according to the token shaping code 89, and performs necessary transformation. Format the token and output it to the link table 11. When the token has an instruction code indicating that it should be output to the outside of the data flow processor, it adds the necessary module number to the token of the external bus and sends it to the token output unit 17. However, token output section 17
Is busy, stop output to it,
Input is also prohibited.

The token output unit 17 outputs the token input from the processing unit 16 or the token input unit 10 to the subsequent data flow processor or memory interface circuit via the external bus 5a. However, when there is a request from both the processing unit 16 and the token input unit 10 at the same time, the input from the token input unit 10 is usually given priority. However, the organization identifier of the entered token is "0" regardless of which one
If it is not, it is understood that the token is a token other than the last token of the group token consisting of multiple tokens, and the rest of the group tokens are input in succession. By notifying that it is busy and stopping the input,
Input all the group talks consecutively with priority. This guarantees the continuity of the group token.

Next, the operation in the case of performing convolution using, for example, nine data will be described using this embodiment.

Prior to the calculation, nine coefficients w (0) to w (8) are respectively assigned to c1 + 1, ..., C1 of the function table 14.
It is set in the internal state holding unit at each address of +8 and c1. Next, the data x (k) to be used for processing is sequentially input from the external memory 4 to the data flow processor via the memory interface circuit 3, and the address d of the data memory 13 is input.
Store in a continuous area starting from 1. When performing the convolution processing continuously, the data of x (0) to x (8) is the first convolution, and the data of x (1) to x (9) is the second convolution. Data of 9 points or more is prepared in the initial state, and data required for the next and subsequent ones are input one by one in synchronization with the completion of convolution of 9 points once at a time. Continue to write. Further, the register used for addition in the register processing unit 22 is cleared.

To obtain the convolution, first, a token having an instruction code for generating a group token of length 9 is input to the token generation unit 20, and a group token composed of nine tokens is prepared. These tokens have the same link table address a1 and the data d1 used to access the data memory 13, and as the organization identifier, the first token is "1", and hereinafter "2", "3", ...
-, "8", and the last token has "0".

These tokens are the arithmetic calculation unit 21, the register processing unit 22,
After passing through the token shaping unit 23, the link table 11 refers to the value of the link table address as an address. By this reference, the output token 70 of the link table has b1 as the operand fetch table address, and a2 and the function table address as the link table address that the result token after the convolution has to have. The function table address is generated by adding the organization table to the function table base address c1 written in the address a1 of the link table 11, and thus these 9
Each token in one set of tokens is c1 + 1, c1 + 2,
.., c1 + 8, c1.

In the operand fetch table 12, reference is performed using the operand fetch table address b1 of the input token 70, and the value in the state holding unit accessed by the addresses of the values d1 and b1 of the data portion of the token (initial value 0) The data memory access address d1 is generated by adding The value of the state holding unit is incremented by 1 each time a token is input to the operand fetch table 12 and the address is referenced, and when the first 8 tokens are input, the data memory access that they have The addresses are d1, d1 + 1, ...
・, D1 + 7. When the ninth token is input, the token receives d1 + 8 as the data memory access address, and at the same time, the value of the state holding unit is reset to 0. This value 9 is the cycle size of data memory read, and the operand fetch table
It is embedded in the instruction code of 12 addresses b1.

In the data memory 13, a read operation is performed on the access addresses d1, d1 + 1, ..., D1 + 8 obtained as described above, and each token is read in advance from the external memory 4 into the data memory 13 as the first operand. The fetched data x (0), x (1), ..., X (8).

In the function table 14, reference is made using the function table address 72 of the input token 80 as an address, and in this case, 9 tokens are c
Since they have values of 1 + 1, c1 + 2, ..., C1 + 8, c1, nine coefficients w (0), w (1), ..., W (8) which are the values of the internal state holding unit at each address. )
Is fetched as the second operand of each token. At the same time, the instruction code of the processing unit 16
86,87,88,89 are also fetched. Of the instruction codes, the arithmetic operation code 87 is the instruction code of multiplication, and the register processing code 88 is the instruction code of adding data to the register and deleting the tokens for the first to eighth tokens. An instruction code for adding data to a register and outputting the contents of the register is given to the token.

X (0), x (1), ..., x as the first operand
(8) as the second operand, w (0), w (1),
..., w (8), the nine tokens having "multiplication" as the arithmetic calculation code pass through the buffer queue 15 and the token generation unit 20 and enter the arithmetic calculation unit 21, where multiplication of two operands is performed. Done.

In the register processing unit 22, the multiplication result data x of these nine tokens is added to the register of the initial value 0 according to the register processing code of each token.
(0) × w (0), x (1) × w (1), ..., x
(8) × w (8) are added one after another, and the tokens from the beginning to the eighth are deleted after being added to the register. The result Σw (i) × x after the last token adds to the register
(K) is output to the token shaping unit 23, and the register is cleared for the next convolution operation.

In the token shaping unit 23, the result token is sent again to the link table 11 according to the program, or sent to the token output unit 17 and output outside the data flow processor.

As described above, the calculation of the convolution of 9 points is completed once. In the same manner, the next required input data x
(9), x (10), ... Are input from outside the data flow processor, and the addresses d1 + 9, d1 of the data memory 13 are input.
Continuously write to +10, ... And d as data
It is possible to continue the generation of a group token composed of the next nine tokens having 1 + 1, the operand fetch from the address d1 + 1 of the data memory by them, the operation, and the output of the result. At this time, the next data x (1), x (2), ...
.., convolution on x (9), and convolution on the next data x (2), x (3), ..., x (10) are started without waiting for the end of this convolution. It is possible to
The processing can be sped up by performing the processing as continuously as possible and shortening the time during which the processing unit does not operate.

The operation in the case of performing the convolution processing has been described above using the embodiment of the present invention. Further, by further using the present invention, it is possible to more efficiently perform the processing that generally targets a plurality of data as one unit. Can be executed.

As an example, a case will be described in which a double-precision operation that handles double-precision data having a bit width twice that of the data of the token is performed. The data is decomposed into high-rank words and low-rank words, and is represented by a group token consisting of two tokens in this order, a token having a lower word and a token having a higher word. This group token has an organizational identifier indicating it, The control mechanism as described above continuously flows through the data flow processor and the data processing device using the data flow processor. When using this to add double-precision data, for example, two pieces of data of a pair token having one data are continuously written to the data memory by a wait instruction of the operand fetch table, and a pair having the other data is written. The token is sent from the link table to the operand fetch table and the data memory, and the data written earlier here is the lower word,
By reading in the order of the upper word, the two tokens held by the lower words and the upper words are sent to the processing unit. In the processing unit, the arithmetic operation unit adds low-order words to each other and high-order words to each other, holds a carry generated by addition of the low-order words in an internal register of the register processing unit, and adds the high-order words to obtain the high-order word of the result. By performing such control, the input double precision data is added, and a pair token having the same format as the input data is output.

Similarly, complex number data having a real part and an imaginary part can be sent in a set token format and can be calculated by the processing unit.

〔The invention's effect〕

As described above, according to the present invention, (1) it becomes possible to fetch the coefficient data w (i) in the function table using the organization identifier of the set token, and x (k) and w (i). The token string generated by the token generator to fetch the
(2) Arithmetic calculation unit and register processing unit are arranged consecutively, which makes it possible to add them immediately after multiplication, and further add tokens in the ring bus between them. It is not necessary to make one round. (3) Moreover, there is an effect that the arithmetic performance is improved because the arithmetic calculation unit and the register processing unit can operate in parallel in a pipeline manner, which results in the program in the convolution processing. It is possible to reduce the burden on the server and increase the processing speed.

Furthermore, processing of double-precision data and complex number data, which had to be realized by conventional software and took a large number of steps to execute, was performed in the data flow processor in the form of a set token having those data using the present invention. It becomes possible to execute at high speed by flowing the.

[Brief description of drawings]

FIG. 1 is a block diagram of a data flow processor of the present invention, FIG. 2 is an overall block diagram showing an example of a processing device using the data flow processor of FIG. 1, and FIG. 3 is a token used for explaining the present invention. FIG. 4 is a diagram showing a format, and FIG. 4 is a diagram showing a configuration of a conventional data flow processor. 10 …… Token input section 11 …… Link table 12 …… Operand fetch table 13 …… Data memory 14 …… Function table 15 …… Buffer memory 16 …… Processing unit 17 …… Token output section 20 …… Token generation section 21 ...... Arithmetic calculation unit 22 ...... Register processing unit 23 ...... Token shaping unit

Claims (1)

[Claims] 1. A data flow processor that performs processing by flowing a token, which is a unit of data, to an internal ring-shaped bus, and controls a link table for storing a destination address of the token and an operand fetch. An operand fetch table, a data memory that temporarily stores operand data used for operations, a function table that stores instruction code and coefficient data, a buffer queue that temporarily holds tokens, and a processing unit that processes data for tokens, A token output unit for sending a token from the processing unit to an external bus; and a token input unit for inputting a token from the external bus and sending it to the link table or the token output unit, the processing unit: A token generator that copies tokens, an arithmetic calculator that does not have an internal state, that performs comparison operations, etc., a register processor that has registers inside and that performs operations, and shaping of operation result tokens. And a token shaping unit for transmitting to the link table or the token output unit, the link table, the operand fetch table, the data memory, the function table, the buffer queue, and the processing unit , And a data flow processor which is connected in sequence to form the ring bus.