JPH0646095A - Digital demodulator - Google Patents

Abstract

PURPOSE:To configure the digital demodulator in which accurate demodulation data are obtained through sure latch processing. CONSTITUTION:A signal subject to digital phase modulation is inputted to an input terminal 1 and the amplitude of the inputted signal is converted into a logic level by a limiter 2. On the other hand, A count of a counter 5 counting number of clock signals from an oscillator 3 is latched by a latch circuit 6 in response to an output signal of the limiter 2. In this case, the output signal of the limiter 2 is inputted to the latch circuit 6 via a 1st D flip-flop 15. The output of the latch circuit 6 is delayed at a delay circuit 7 by a time for one symbol period, a subtractor circuit 8 subtracts the output of the latch circuit 6 and the output of the delay circuit 7 to output phase change data. A phase compensation circuit 10 compensates the phase based on the phase change data and a decoding circuit 12 recovers the data. Furthermore, A PLL circuit 11 recovers a symbol clock and a data clock from the output of the subtractor circuit 8.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to digital demodulators.

[0002]

2. Description of the Related Art Conventionally, in order to efficiently use a transmission medium, a carrier signal is modulated and demodulated with a digital information signal (baseband signal). As such a modulation method, an amplitude modulation method (ASK) that changes the amplitude of a carrier signal according to a digital baseband signal,
Frequency modulation method (FSK) that shifts the frequency of the carrier wave according to the baseband signal, phase modulation method (PSK) that changes the phase of the carrier wave according to the baseband signal, and amplitude and phase of the carrier wave depending on the baseband signal Various schemes such as a quadrature amplitude modulation scheme (QAM) that independently changes the signal are used.

The carrier signal (modulated wave signal) S (t) thus modulated according to the baseband signal can be generally expressed as follows.

[0004]

[Equation 1]

As is clear from Equation 1, the modulated wave signal can be represented by two orthogonal components, and the baseband signal can be demodulated by a demodulation circuit such as a quadrature detector. The first term in the above equation is the in-phase (I-phase) of the modulated wave signal.
The component, the second term, is commonly referred to as the quadrature phase (Q phase) component of the modulated wave signal. As a digital demodulator for demodulating a digital phase modulation signal by an all-digital circuit, Japanese Patent Laid-Open No. 3-1887
There is a digital demodulator based on the demodulation method disclosed in the 37th report. FIG. 10 is a block diagram of a conventional example of a digital demodulator in the same system.

In FIG. 10, 101 is a digital phase modulation signal input terminal, 102 is a symbol clock signal input terminal, 103 is a limiter for making the amplitude of the input digital phase modulation signal constant, and 104 is a response to the output signal of the limiter 103. A synchronization circuit for sampling the symbol clock signal, 105 an oscillator oscillating an integer multiple frequency of the carrier signal, 106 a counter for counting based on the output of the oscillator 105, 107 an output of the counter 106 for the synchronization circuit 104 Latch circuit that latches in response to output, 10
8 is a latch circuit 1 in response to the output of the synchronization circuit 104.
A delay circuit for inputting and delaying the output of 07, 109 is a comparison operation circuit for inputting the output of the latch circuit 107 and the output of the delay circuit 108 and performing a comparison operation for the change in the phase of one symbol section, and 110 is a comparison operation circuit. A reproduction data output terminal for outputting reproduced data.

Next, the operation will be described. First, in Japan
Digital car telephone system standard (RCR
 Π / 4 shift QPS which is a modulation method of STD-27)
The K modulation method will be described. First, the input digital
The serial signal is a 2-bit parallel signal (X _k,
Y_k) Is converted to a symbol. Signal format
A modulation symbol is set every 2 bits from the first bit.

The conversion (binary / quaternary conversion) from the input serial signal to (X _k , Y _k ) is as follows.

[0009]

[Table 1]

Further, (X_k, Y_k) Is differentially encoded directly
Interchange signal (I_k, Q_k) Is converted to. (X _k, Y_k) To (I
_k, Q_k) Is converted into the following equation.

[0011]

[Equation 2]

However, ΔΦ (X _k , Y _k ) = ΔΦ _k is defined as shown in the following table.

[0013]

[Table 2]

The I _k and Q _k signals thus obtained are
Each of the I-phase components i is independently subjected to baseband band limitation by a low-pass filter and supplied to the quadrature modulator.
(T), Q-phase component q (t) is generated. Here, if the symbol period is T and the phase of t = kT is Φ (t) = Φ _k ,

[0015]

[Equation 3]

And one symbol before that, that is, t =
If the phase of kT−T is Φ (t) = Φ _k−1 ,

[0017]

[Equation 4]

[0018] From Equation 2, Equation 3, and Equation 4,

[0019]

[Equation 5]

[0020] Transforming Equation 5

[0021]

[Equation 6]

It becomes Therefore, from Equation 6, π / 4 shift
At the symbol decision point when demodulating the QPSK modulated signal
Phase Φ_kAnd the phase Φ one symbol before_k-1And phase Φ_k
More phase Φ_k-1By subtracting
Phase change ΔΦ (X_k, Y_k), The phase difference Δ
Φ (X_k, Y_k) From Table 2 X_k, Y_k, ...
a_n-1, A _n, A_{n + 1}, A_{n + 2}··· Restore the serial signal of
Can be adjusted.

The operation will be described with reference to FIG. 10. The limiter 103 limits the amplitude of the digital phase modulation signal input from the digital phase modulation signal input terminal 101, and converts it into a rectangular wave logic level. Further, the synchronization circuit 104 samples the symbol clock signal input from the symbol clock signal input terminal 102 in response to the rising edge of the output signal of the limiter 103. The symbol clock signal is a rectangular wave signal whose rising timing is defined as the data sampling timing (symbol determination point). The rising edge of the sampled symbol clock signal, that is, the output signal of the synchronization circuit 104 coincides with the zero-cross point of the digital phase modulation signal.

On the other hand, since the oscillator 105 is set to oscillate a clock signal having a frequency n times (n is an integer) the carrier frequency of the digital phase modulation signal, the clock of the oscillator 105 is divided by 1 / n. The output of the counter 106 is obtained by dividing the phase of one cycle of the carrier wave into n. The count value of the counter 106 that drives by inputting the clock signal of the oscillator 105 is held in the latch circuit 107 at the rising edge of the output of the synchronization circuit 104. This count value represents the phase Φ _k of the digital phase modulation signal of Expression 3.

The output of the latch circuit 107 is further input to the delay circuit 108 and held in the delay circuit 108 at the rising edge of the output of the synchronizing circuit 104. This delayed value represents the phase Φ _k-1 one symbol before in Equation 4. The output (Φ _k ) of the latch circuit 107 and the output (Φ _k-1 ) of the delay circuit 108 are input to the comparison operation circuit 109 to detect the phase change ΔΦ (X _k , Y _k ) in one symbol section, and According to the above, the symbol data is demodulated, and the 2-bit symbol data is converted into serial data by parallel / serial conversion to obtain demodulated data. The demodulated data is output to the reproduction data output terminal 110.

Since the frequency of the oscillator 105 is set to n times the carrier frequency of the digital phase modulation signal, the phase resolution is 2π / n. Therefore, if the frequency of the oscillator 105 is set sufficiently higher than the carrier frequency of the digital phase modulation signal, the necessary resolution for phase measurement can be obtained.

[0027]

However, when the phase is quantized by the above-mentioned conventional method, the latch circuit 107 responds in response to the rising of the output signal of the synchronizing circuit 104 when the counter 106 is in an undefined state. Because sometimes
There is a problem that accurate phase data cannot be obtained and accurate demodulated data cannot be obtained.

An object of the present invention is to construct a demodulator that can obtain accurate demodulated data by performing accurate phase quantization.

[0029]

In view of the above problems, the present invention provides a limiter section for converting the amplitude of a digital phase modulation signal into a logical level to generate a limiter output, and a clock signal input terminal to which a clock signal is input. A phase information output unit that outputs phase information based on the clock signal, and a holding unit that holds the phase information of the phase information output unit in response to rising or falling of the limiter output and generates a phase quantized output. In a differential detection type demodulation circuit which obtains phase change data and reproduces demodulated data by using the phase quantizing means, a synchronizing means for phase-shifting the limiter output to the clock signal and inputting it to the holding section is provided. Characterize.

[0030]

According to the present invention, the phase of limiting the amplitude of the digital phase modulation signal, synchronizing the amplitude limited signal of the digital phase modulation signal with the clock signal, and driving by the clock signal in response to the synchronized signal. Since the information output is latched (held), it is not latched when the phase information output is in an indefinite state, and accurate phase quantization is performed.

[0031]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 1 is an input terminal to which a digital phase modulation signal is input, 2 is a limiter for limiting the amplitude of the input digital phase modulation signal, and a limiter for converting it into a binary digital signal, and 3 is an oscillator for generating a clock signal. Reference numeral 4 is a clock signal input terminal to which a clock signal is input, 5 is a counter that counts based on the clock signal and outputs a count value as phase information, and 6 is a count value of the counter 5 in response to the output of the limiter 2. A latch circuit (holding means) for holding (phase information), a delay circuit 7 for delaying the count value held by the latch circuit 6 by a data clock signal having a multiplication relationship with the symbol clock for one symbol period, and 8 a latch A subtraction circuit for performing a subtraction process on the count value held by the circuit 6 and the count value delayed by the delay circuit 7 for one symbol period;
9 is a sampling circuit for sampling the phase change data of the output of the subtraction circuit 8 with a symbol clock of a predetermined cycle,
Reference numeral 10 is a phase compensation circuit that performs phase compensation on phase change data, 11 is a symbol clock signal by inputting the output of the subtraction circuit 8, a PLL circuit that reproduces a data clock signal obtained by multiplying the signal, and 12 is phase compensation The phase-compensated phase change data of the output of the circuit 10 is decoded to form and derive the symbol data, and the symbol data is parallelized / decoded.
A decoding circuit that performs serial conversion and outputs serial data as reproduced data. 13 is a reproduction serial data output terminal from which reproduction data output from the decoding circuit 12 is output,
Reference numeral 14 is a reproduction data clock output terminal to which the data clock signal output from the PLL circuit 11 is output. Reference numeral 15 is a first D-type flip-flop for synchronizing the output of the limiter with the clock signal, 16 is a second D-type flip-flop for synchronizing the data clock signal with the clock signal, 17 is an inverter for inverting the clock signal, and 18 is a direct phase quantization circuit. , 19 is a third D-type flip-flop, and 20 is a fourth
It is a D-type flip-flop.

Next, the operation will be described with reference to FIGS. Here, a π / 4 shift QPSK signal having a carrier frequency of 450 kHz at 42 kbit / s is considered as an input signal. When a digital phase modulation signal such as A in FIG. 2 is input to the input terminal 1, the digital phase modulation signal is converted by the limiter 2 into a binary digital signal such as B in FIG.

On the other hand, the counter 5 counts on the basis of the clock signal of the oscillator 3 and outputs the phase information as shown by C in FIG. For example, if the frequency of the clock signal of the oscillator 3 is 14.4 MHz, which is 32 times the carrier frequency of 450 kHz of the digital phase modulation signal, the counter 5 is 1/3.
The frequency is divided by 2 to obtain a 5-bit parallel count value. In this case, the phase information output which is the output of the counter 5 is C in FIG.
It is not a smooth value like that, but actually has a stepwise value as shown in FIG. The latch circuit 6 latches the count value of the counter 5 in response to the rising of the output of the limiter 2. However, as shown in B and C of FIG. 3, when the output of the counter 5 is indefinite, the limiter 2 The output of may rise. In order to prevent such an operation, in the present embodiment, the phase of the output of the limiter is shifted so that the counter latches in a stable state.

In order to perform such an operation, the limiter 2
First, the output of is input to the D terminal of the first D-type flip-flop 15. And the ck of the first D-type flip-flop 15
The inverted clock signal that has passed through the inverter 17 is input to the terminal. Since the D-type flip-flop holds the signal input to the D terminal at the rising edge of the signal input to the ck terminal, the output of the limiter 2 should be delayed according to the falling timing of the clock signal as shown in E of FIG. To be If the latch circuit 6 latches the value of the counter 5 in response to the rising of the output of the first D-type flip-flop 15, as shown in FIG. It is possible to hold and output the value of the counter 5. As a result, the latch output is output a little later than the falling edge of the clock signal, and the indefinite state of the latch output occurs within a half cycle after the falling edge of the clock signal.

Thus, the instantaneous phase data (latch output data) as shown by D in FIG. 2 is obtained. Then, when the instantaneous phase data held by the output of the latch circuit 6 is delayed by one symbol section by the delay circuit 7, the phase data one symbol before as shown by E in FIG. 2 is obtained. Also at this time, the data clock may rise when the output of the latch circuit 6 is indefinite, so that the data clock rises when the output of the latch circuit 6 is in a stable state.
The delay circuit 7 is operated reliably.

The data clock is input to the D terminal of the second D-type flip-flop 16, and the clock signal inverted through the inverter 17 is input to the ck terminal. As described above, since the D-type flip-flop holds the signal input to the D terminal at the rising edge of the signal input to the ck terminal, the data clock is a clock out of the indefinite timing of the latch output as shown by H in FIG. Delayed at the falling edge of the signal. This second D-type flip-flop 16
If the delay circuit 7 is driven in response to the rise of the output of the latch circuit 6, the output of the latch circuit 6 is in a stable state.
Does a definite move. However, in this embodiment, since the delay circuit 7 is operated in response to the data clock, the delay output is derived only in the data clock cycle, and is not derived in response to all rising outputs of the limiter output. Absent.

Next, the subtraction circuit 8 subtracts the phase data one symbol before the output of the delay circuit 7 from the instantaneous phase data output from the latch circuit 6, and the phase change data for one symbol time as shown by F in FIG. 2 is obtained. can get. The subtraction circuit 8 is composed of a logic circuit, and its output is in an indefinite state during both the indefinite period of the latch output and the indefinite period of the delayed output. When the phase change data output from the subtraction circuit 8 is synchronized with the symbol clock, the eye pattern shown in FIG. 5 is obtained. As shown in FIG. 5, the phase change data is 3π / 4, π / 4, −π / 4, −3π / at the symbol determination point (rising portion).
It converges to 4 values of 4.

Further, since the zero-cross point of the phase change data shown in FIG. 5 can be regarded as being located at the center between the symbol determination points on average, the PLL circuit 11 causes the phase change data to have the sign inversion timing and the symbol clock signal falling edge. The phase of the symbol clock signal is controlled so that the timings match on average. Further, the PLL circuit 11 forms a data clock signal obtained by multiplying (multiplying by 2) the symbol clock, and outputs this data clock to the clock output terminal 14.

An example of such a PLL circuit is shown in FIG. Input signal (sign inversion timing of phase change data) and output signal (symbol clock signal) by the phase comparison circuit 21.
The phase difference is detected and expressed as a binary value of "advance" and "delay", and the reversible counter 22 in which N is set as a preset value is added or subtracted. When the content of the reversible counter 22 becomes 2N, a control signal of − is generated, and when the content of the reversible counter 22 becomes 0, a value of the reversible counter is reset to N with the generation of this signal. The phase control circuit 24 inputs the input clock signal from the clock signal input terminal 4, and inputs the input clock signal to the reversible counter 22.
It controls the number of clock signals to pass according to the output of. That is, the phase control circuit 24 adds one pulse to the clock signal when the reversible counter 22 issues a + signal, and removes one pulse from the clock signal when the minus signal is issued to control the phase. The frequency dividing circuits 25 and 26 count the number of phase-controlled outputs whose pulse number is controlled, and control the phase timing of the frequency-divided output. In this way, the symbol clock signal and the code inversion timing of the phase change data are controlled so as to be almost synchronized on average.

The delay circuit 7 may be driven by an independent clock signal, but by using the data clock signal which is the output of the PLL circuit 11, the delay circuit 7, the subtraction circuit 8 and the PLL circuit 11 form a feedback loop. Configure and
You can expect reliable operation. On the other hand, the carrier frequency of the input digital phase modulation signal is the oscillator 3 as described above.
If the frequency is exactly 1/32, the sampling circuit 9
Latches the input phase change data at the rising edge of the symbol clock signal output from the PLL circuit 11, and 3π /
A latch output that is one of four values of 4, π / 4, −π / 4, and −3π / 4 is supplied to the decoding circuit 12 via the phase compensation circuit 10.

Of the irregular periods of the subtraction output described above, the first D-type flip-flop 15 has an indefinite period due to the latch.
Output, that is, the indeterminate period caused by the delay that occurs in the modulation signal cycle in conjunction with the falling timing of the clock,
Similarly, the output of the second D-type flip-flop 16, that is, it is generated in a half cycle of the symbol clock in conjunction with the falling timing of the clock. Therefore, the indefinite period occurs after the fall of the clock signal and before the rise thereof.

Therefore, in this embodiment, the symbol clock signal is input to the third D-type flip-flop 19 in order to delay the sampling phase to the clock falling timing so that the symbol clock does not rise at that timing, and the inverted clock is input. Is latching by. As a result, in the sampling circuit, sampling is performed at a timing outside the indefinite period.

Furthermore, the indefinite period of the sampling output described above is a period immediately after sampling, that is, after the falling edge of the clock signal, and the phase-compensated output of the sampling output becomes stable by the rising edge of the clock signal. Therefore, in the present embodiment, the phase of the input data clock is phase-shifted and phase-compensated by interposing the fourth D-type flip-flop 20 so that the decoding circuit 12 does not perform decoding during the irregular period of the phase-compensated output. The compensation is performed so that the decoding is performed during the stable period of the output, that is, the falling timing of the clock signal.

Therefore, the fourth D-type flip-flop 20
Inputs a data clock to the D terminal and an inverted clock signal to the ck terminal, and delays and outputs the data clock according to the falling edge of the clock signal. The decoding circuit 12 has phase changes of 3π / 4, π / 4, −π / 4, −.
The 2-bit symbol data corresponding to the 4 values of 3π / 4 is decoded according to Table 2, and the received real data is reproduced by parallel / serial conversion of the 2-bit symbol data and output to the output terminal 13. Even when the data clock is supplied to the decoding circuit 12, the data clock is supplied via the D-type flip-flop 20 so as to operate reliably.

Next, the compensation operation of the phase compensation circuit 10 will be described. FIG. 8 shows an example of the phase compensation circuit. Generally, in mobile communication, carrier frequency fluctuation due to the influence of random FM noise associated with fading and frequency deviation Δω _c due to the difference in frequency between the reference oscillators of the transmitter and the receiver occur. Considering the frequency deviation Δω _c , the formula 1 is as follows.

[0046]

[Equation 7]

From Equation 7, the phase when t = k · T is θ
If (t) = θ _k ,

[0048]

[Equation 8]

Becomes one symbol before, that is, t = k · T-
If the phase at T is θ (t) = θ _k−1 ,

[0050]

[Equation 9]

It becomes Phase change in one symbol interval Δθ _k
Is

[0052]

[Equation 10]

It becomes If there is a frequency deviation Δω _c T,
Since the output of the latch circuit 6 is θ _{k and} the output of the delay circuit 7 is θ _k-1 , the output of the subtraction circuit 8 is Δθ _k . Then, from Expression 10, the eye pattern of the phase change data when the carrier frequency of the input digital phase modulation signal has a frequency deviation Δω _c is as shown in FIG. As described above, when the carrier frequency of the input digital phase modulation signal has a frequency deviation Δω _c , the phase change data is 3π / 4 + Δω at the symbol determination point as shown in FIG.
_c T, π / 4 + Δω _c T, −π / 4 + Δω _c T, −3π /
4 + Δω _c T converges to four values, and the DC component Δω _c T is superimposed on all phase change data.

This DC component Δω _c T can be removed by a circuit as shown in FIG. △ case of obtaining the omega _c T, measured over several symbols in consideration △ omega _c T noise or the like,
By averaging this, it is possible to obtain an almost accurate Δω _c T. Then, Δω _c T obtained by averaging is subtracted from the output of the sampling circuit 9 to obtain phase change data having no frequency deviation, that is, DC component. It should be noted that this phase compensation may be performed after the sampling or before the sampling, and is effective even if it is adopted in a conventional configuration as long as it is a delay detection type demodulation circuit, and only in the configuration of this embodiment. It is added that it is not effective.

The demodulation circuit of the above-described embodiment employs the present invention in a demodulation circuit of a type that forms a symbol clock signal in the circuit, but it is similar to the conventional example in which a symbol clock formed in advance is used. It is of course possible to employ the present invention in a demodulation circuit, and FIG. 9 shows another embodiment in which the present invention is employed in the above-mentioned conventional demodulation circuit. Incidentally, FIG.
The respective constituent elements are disclosed as the constituent elements in FIGS. 1 and 10, and the common reference numerals are omitted to avoid duplication.

Thus, the operation according to the present invention is achieved, but it can also be realized by a digital phase modulation method other than the π / 4 shift QPSK signal of this embodiment. Further, although the present invention is configured by hardware in the present embodiment, it goes without saying that the present invention can be realized by replacing a part of the hardware with software. Furthermore, it should be added that this embodiment can be modified as necessary.

[0057]

According to the present invention, the amplitude of the digital phase modulation signal is limited, the amplitude limited signal of the digital phase modulation signal is synchronized with the clock signal, and the signal is driven by the clock signal in response to the synchronized signal. Holding the output of the phase information output means, delaying the held output by one symbol period by a signal serving as a reference for delay synchronized with the clock signal, and holding the held output and the delayed output. Since it is calculated, accurate demodulation can be performed.

Further, since the addition / subtraction is performed to perform the phase compensation after the above calculation, the frequency of the clock signal does not have to be set to an integral multiple of the carrier frequency of the digital phase modulation signal, and is accompanied by fading. Due to the influence of random FM noise, the transmission characteristics do not deteriorate even if the carrier frequency changes. Further, by having the PLL means, it is possible to have the symbol clock signal without inputting from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the present invention.

FIG. 3 is a diagram showing a timing chart of the present invention.

FIG. 4 is a diagram showing phase information output when the phase resolution of the present invention is 2π / 32.

FIG. 5 is a diagram showing an eye pattern of phase change data when the carrier frequency of the digital phase modulation signal of the present invention has no frequency deviation.

FIG. 6 is a diagram showing an eye pattern of phase change data when the carrier frequency of the digital phase modulation signal of the present invention has a frequency deviation of Δω _c .

FIG. 7 is a block diagram showing an example of a PLL circuit.

FIG. 8 is a block diagram showing an example of a phase compensation circuit.

FIG. 9 is a diagram showing another embodiment of the present invention.

FIG. 10 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 101 Digital phase modulation signal input terminal 2, 103 Limiter 3, 105 Oscillator 4 Clock signal input terminal 5, 106 Counter 6, 107 Latch circuit 7, 108 Delay circuit 8 Subtractor circuit 9 Sampling circuit 10 Phase compensation circuit 11 PLL circuit 12 Decoding circuit 13, 110 reproduction serial data output terminal 14 reproduction data clock output terminal 15 first D-type flip-flop 16 second D-type flip-flop 17 inverter 18 direct phase quantization circuit 19 third D-type flip-flop 20 fourth D-type flip-flop 104 Synchronization circuit 109 Comparison operation circuit

Claims (1)

[Claims] 1. An input terminal to which a digital phase-modulated signal is input, a limiter section for converting the amplitude of the signal input from the input terminal to a logical level and generating a limiter output, and a clock signal are input. A clock signal input terminal section, a phase information output section that outputs phase information based on a clock signal input from the clock signal input terminal section, and phase information of the phase information output section in response to rising or falling of the limiter output. Phase quantizing means having a holding part for holding and generating a phase quantized output, synchronizing means for phase-shifting the limiter output to a clock signal and inputting it to the holding part, and the phase quantized output for one symbol section. Delaying means for delaying by the time of, and subtracting means for subtracting the phase quantization output and the output of the delaying means,
A digital demodulator, comprising: a decoding unit that converts phase change data into symbol data.