JPH0644696A - Recording device for digital video signal - Google Patents

Abstract

PURPOSE:To obtain a recording device suitable for recording a compression- encoded video signal divided into plural segments. CONSTITUTION:Video data are compressed by DCT variable length encoding and are made data structure of a sync block. Recorded data for one frame are quartered into four. First recording data 9A are recorded on the area of a first channel CH1 of a first segment on the tape and next recording data 9B are recorded on the area of a second channel CH2 of the first segment. Third data 9C and fourth recording data 9D are recorded on the CH1 and the CH2 of a second segment, respectively. Thus, the head interleaf is performed by a segment unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording device for digital video signals which uses, for example, DCT as high efficiency coding.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head is known. Since the amount of information in digital video signals is large,
High-efficiency coding for compressing the amount of transmitted data is often adopted. Among various high efficiency coding, DC
Practical application of T (Discrete Cosine Transform) is progressing.

In the DCT, one frame image is converted into, for example, (8
X8) is converted into a block structure, and this block is subjected to cosine transform processing which is a kind of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to variable-length coding processing such as run-length coding and Huffman coding. At the time of transmission, in order to facilitate data processing on the reproducing side, a code signal, which is an encoded output, is inserted into the data area of a sync block of a certain length, and a sync signal, I
The sync block to which the D signal is added is framed.

FIG. 10 shows the structure of a recording circuit of a conventional digital VTR which does not use a compression code such as DCT. The input video signal is converted into a digital video signal by the A / D converter 11 and this digital video signal is supplied to the shuffling circuit 12. The shuffling circuit 12 makes the arrangement of data different from the original one on a sample-by-sample basis so as to make the influence of an error generated in the recording / reproducing process visually inconspicuous.

The output signal of the shuffling circuit 12 is supplied to the error correction code encoder 13. As the error correction code, a product code for coding the error correction code in each of the row direction and the column direction of the video data of the two-dimensional array is used. The video data from the encoder 13 and the parity of the error correction code are supplied to the sync block forming circuit 14. One sync block is formed by adding a block synchronization signal and an ID signal to a predetermined amount of video data or parity.

Record data of a sync block series is generated from the sync block forming circuit 14 and supplied to the head interleave circuit 15. The head interleaving circuit 15 is provided to interleave the recording data and supply the recording data to a plurality of recording heads (usually rotary heads). As an example, when one head clogs, a large amount of reproduced video data becomes error data and the quality of the reproduced image deteriorates significantly. Also, when a burst error occurs due to a scratch on the tape, the image quality is considerably deteriorated by the error. Although correction is performed by the error correction code, errors exceeding the capability are corrected by the interpolation process. The head interleave circuit 15 changes the data arrangement in order to prevent the error correction ability and the error correction ability from being lowered due to an error.

FIG. 11 illustrates an example of a conventional head interleave. In the recording data, sync blocks are continuous, and an ECC block (unit of product code) is formed by a plurality of sync blocks. The recording data of one frame is, for example, 2 channels (CH1 and CH2), 2
The segments are recorded on magnetic tape. Here, the channel corresponds to each of the rotary heads. That is, two rotary heads simultaneously scan the magnetic tape to form two first segments, and then two
The two rotary heads simultaneously scan the magnetic tape to form two second segments.

[0008]

The head interleave for distributing the recording data to each head in sync block units in the above-mentioned non-compression type digital VTR is as follows.
It is not suitable for a digital VTR using a compression code such as DCT and variable length coding. That is, the encoded data has a variable length and the code delimiter is ECC.
It does not match the block or sync block delimiter. Therefore, even if error-free data is obtained in sync block units, the compression code may not be decoded.

In order to solve this problem, EOB (end of block) is recorded at the break of the compressed block, but there is a drawback that the overhead increases. Normally,
A signal for cutting may be inserted in units of a plurality of compressed blocks. Even in this case, the restoration cannot be performed by the head interleave in sync block units, and the ECC
The block-based head interleaving increases the data that can be restored to some extent. However, it is still insufficient.

Therefore, an object of the present invention is to provide a recording apparatus for a digital video signal, which is adapted to perform head interleaving suitable for variable-length recording data generated by compression encoding.

[0011]

SUMMARY OF THE INVENTION According to the present invention, a digital video signal is encoded by orthogonal transformation and variable length coding, and one frame or one field of the encoded output is recorded as a plurality of segments on a recording medium. In the recording apparatus of the digital video signal described above, a head interleave circuit is provided for distributing the sync-blocked recording data in a unit different from the original order to the plurality of rotary heads. It is a recording device for a digital video signal.

[0012]

Since the head interleave is not a sync block unit but a larger segment unit, it is possible to prevent the image quality of a reproduced image from being affected by an error because the data that can be decoded is increased even with a variable length code. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a video data processing circuit provided on the recording side of a digital VTR. Figure 1
In, the input video signal is converted into a digital video signal by the A / D converter indicated by 1. This digital video signal is supplied to the encoder 2 of the compression code. An orthogonal transform code such as DCT can be used as the compression code.

In the case of DCT, raster scan order video data is converted into (8 × 8) DCT block structure data, and DCT conversion is performed by a conversion circuit to generate DC and AC coefficient data. To do. This coefficient data is quantized by a quantization circuit, and further variable length coding such as Huffman coding is performed. Therefore, as shown in FIG.
The amount of coefficient data generated differs for each DCT block.

The output of the compressed code encoder 2 is supplied to the shuffling circuit 3. In the shuffling circuit 3, for example, in order to prevent the concentration of errors and the conspicuous deterioration of the image quality, for example, in one frame, the spatial position is made different from the original one in units of DCT blocks, that is, Shuffling is done. The encoder 2 and the shuffling circuit 3 can be arranged in the order opposite to that shown in FIG.

The output data of the shuffling circuit 3 is supplied to the error correction code encoder 4. As shown in FIG. 3, the error correction code packs coefficient data into a two-dimensional area of a predetermined size in order from the first block, encodes the inner code in the horizontal (row) direction, and vertically The outer code is encoded in the (column) direction. A Reed-Solomon code or the like can be adopted as the inner code and the outer code. Further, the output data of the encoder 4 is supplied to the sync block forming circuit 5. In the sync block forming circuit 5, the block sync signal and the I signal are applied to the data (or the outer code parity) and the inner code parity of each column.
The D signal is added to form a sync block.

4 and 5 illustrate the shuffling process performed by the shuffling circuit 3. It is assumed that the DCT blocks are numbered within one frame as shown in FIG. FIG. 5A shows the data of one frame before shuffling, and the coefficient data of the DCT block is located in order. Due to the shuffling, as shown in FIG. 5B, the order of data is changed in DCT block units from the original order (FIG. 5A).

This embodiment is a 2-channel 2-segment digital VTR in which the tape pattern shown in FIG. 6 is formed. Channel 1 on magnetic tape 7
The (CH1) rotary head and the channel 2 (CH2) rotary head simultaneously form two oblique tracks, that is, two segments. The first segment formed is called the first segment. Similarly, the next scan forms the second segment of CH1 and the second segment of CH2.

FIG. 7 conceptually illustrates the method of head interleaving in this embodiment. The recording data is a series of sync blocks. The recording data 8 of one frame is divided into four equal parts in order from the beginning, and the divided data 9
A, 9B, 9C and 9D are formed. The first divided data 9A is recorded in the first segment (track) of CH1, and the second divided data 9B is recorded in the first segment of CH2. Similarly, the divided data 9C and 9D are recorded in the second segment of each channel.

FIG. 8 shows an example of the head interleave circuit 6 for performing such processing. The input data from the sync block forming circuit 5 is input registers 21, 22, 2
3 and 24. A write clock synchronized with the input data is commonly supplied to the input registers 21 to 24. Outputs of the input registers 21 to 24 appear when the output enable signals OE1 * to OE4 * (* means inversion) are at a low level.

Segment memories 31, 32, 33 and 34 are connected to the input registers 21 to 24, respectively. Each of the segment memories 31 to 34 has a capacity capable of storing recording data for one segment. A common write address and read address are supplied from the address generation circuit 35 to these segment memories 31 to 34. A control signal WP for controlling write / read is also commonly supplied to the segment memories 31 to 34. Further, the segment memories 31 to 34 are respectively supplied with chip select signals CS1 * to CS4 * in order to selectively enable the memories.

For the segment memories 31 to 34,
Output registers 41, 42, 43 and 44 are connected respectively. A read clock is commonly supplied to the output registers 41 to 44. The output enable signal OE5 * is commonly supplied to the output registers 41 and 42, and the output enable signal OE is commonly supplied to the output registers 43 and 44.
6 * is supplied. The outputs of the output registers 41 and 43 are the output data of the first channel CH1, and the outputs of the output registers 42 and 44 are the output data of the second channel CH2.

FIG. 9 is a timing chart showing the operation of the head interleave circuit 6 shown in FIG. Output enable signal OE1 * for the input registers 21-24
As shown in FIG. 9, OE4 * are sequentially set to a low level in a section obtained by dividing one frame into four. Input register 21
˜24 can output the input data when the output enable OE * (* means inversion) is low level. Therefore, each of the segment memories 31 to 34 has 1
The recording data for one segment of 1/4 of the frame is supplied.

Since the chip select signals CS1 * to CS4 * are respectively supplied to the segment memories 31 to 34, the recording data via the above-mentioned input registers 21 to 24 are sequentially written in the segment memories. In the period of the first segment, the print data is output from the output registers 41 and 42 by the output enable signal OE5 *. Therefore, the first divided data and the second divided data of the recording data of one frame are CH1 and C.
It is recorded on the tape as H2. In the next second segment period, the recording data is output from the output registers 43 and 44 by the output enable signal OE6 *. Therefore, the third divided data and the fourth divided data of the recording data of one frame are CH1 and CH2.
Is recorded on tape as. In this way, the head interleave shown in FIG. 7 is performed.

In the present invention, the head interleave circuit 6 is provided with a segment memory for parallelizing recording data and interleaving. However, parallelization is performed at an earlier stage, for example, at the shuffling circuit ○, Head interleaving may also be performed by using a memory for shuffling.

[0026]

According to the present invention, since a segment is selected as a unit of head interleaving, it is possible to prevent the code of the variable length code from being divided in the middle by the head interleaving and to effectively use the reproduced data. .

[Brief description of drawings]

FIG. 1 is a block diagram of a recording data processing circuit of a digital VTR to which the present invention is applied.

FIG. 2 is a schematic diagram used to describe data generated by compression encoding.

FIG. 3 is a schematic diagram used to describe an example of error correction encoding.

FIG. 4 is a schematic diagram showing a positional relationship of DCT blocks in one frame.

FIG. 5 is a schematic diagram used to explain shuffling.

FIG. 6 is a schematic diagram of an example of a track pattern on a magnetic tape.

FIG. 7 is a schematic diagram conceptually showing a head interleave according to the present invention.

FIG. 8 is a block diagram of an example of a head interleave circuit.

FIG. 9 is a timing chart for explaining the operation of the head interleave circuit.

FIG. 10 is a block diagram of an example of a configuration on a recording side of a conventional digital VTR.

FIG. 11 is a schematic diagram for explaining an operation of a head interleave of a conventional digital VTR.

[Explanation of symbols]

 2 encoder for compression code 3 shuffling circuit 4 encoder for error correction code 6 head interleave circuit

Claims (1)

[Claims] 1. Recording of a digital video signal, wherein a digital video signal is encoded by orthogonal transformation and variable length code, and one frame or one field of the encoded output is recorded as a plurality of segments on a recording medium. In the apparatus, recording of a digital video signal is characterized by having a head interleave circuit for allocating the sync-blocked recording data to the plurality of rotary heads in the above-mentioned segment unit in an order different from the original order. apparatus.